JP2000200498A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device in which flow of an over-current can be surely prevented when an anti-fuse is blown and made low resistance. SOLUTION: A capacitor 2 and a MOS transistor 3 are connected between one side electrode of an anti-fuse 51 and terminals T1, T2 respectively, and the other side electrode of the anti-fuse 51 is grounded through a MOS transistor 57. High voltage is applied between the terminals T2 and T1, while after the MOS transistor 3 is conducted for the prescribed time and the capacitor 2 is charged, the MOS transistor 57 is conducted and the anti-fuse is blown. Even when the anti-fuse 51 is made low resistance, as only a charging current to the capacitor 2 is made to flow in a circuit. an over-current never be made to flow in a circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an anti-fuse whose resistance decreases when blown.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a configuration of a conventional dynamic random access memory (hereinafter, referred to as DRAM) 30. Referring to FIG.
0 includes a clock generation circuit 31, a row and column address buffer 32, a row decoder 33, a column decoder 34, a redundant column decoder 35, a memory mat 36, an input buffer 40, and an output buffer 41. A redundant memory array 38 and a sense amplifier + input / output control circuit 39 are included.

A clock generation circuit 31 selects a predetermined operation mode based on externally applied signals / RAS and / CAS, and controls the entire DRAM 30.

[0004] Row and column address buffer 32 is provided with a row address signal RA0 based on externally applied address signals A0 to Ai (where i is an integer of 0 or more).
To RAi and column address signals CA0 to CAi, and generated signals RA0 to RAi and CA0 to CAi
To the row decoder 33 and the column decoders 34 and 35, respectively.
Give to.

The memory array 37 is arranged in a matrix.
Each memory cell includes a plurality of memory cells each storing 1-bit data. Each memory cell is arranged at a predetermined address determined by a row address and a column address.

[0006] Row decoder 33 includes row address signals RA 0 to RA provided from row and column address buffer 32.
In response to i, the row address of the memory array 37 is specified. The column decoder 34 includes a row and column address buffer 3
2 designates a column address of the memory array 37 in response to the column address signals CA0 to CAi given from 2.

Column decoder 34 and redundant column decoder 35
A fuse group (not shown) for programming a column address including a defective memory cell in the memory array 37 and a column address of a redundant memory cell 35 to be replaced with the column address is provided therein. . When column address signals CA0 to CAi corresponding to the defective column address programmed by the fuse group are input, column decoder 34 does not specify the column address, and redundant column decoder 35 sets the program instead of the column address. The column address of the redundant memory array 38 is designated. That is, a defective memory cell column including a defective memory cell in the memory array 37 is replaced with a normal memory cell column in the redundant memory array 38.

A sense amplifier + input / output control circuit 39 connects a memory cell at an address designated by a row decoder 33 and a column decoder 34 (or a redundant column decoder 35) to one end of a data input / output line pair IOP. The other end of the data input / output line pair IOP is connected to the input buffer 40 and the output buffer 41. In a write mode, input buffer 40 applies data input from the outside to a selected memory cell via data input / output line pair IOP in response to an externally applied signal / W. Output buffer 41
Outputs read data from a selected memory cell to an external device in response to a signal / OE externally input in a read mode.

FIG. 9 is a partially omitted circuit block diagram showing the structure of the memory mat 36 of the DRAM shown in FIG.

Referring to FIG. 9, a memory array 37 includes a plurality of memory cells MC arranged in a matrix, a word line WL provided corresponding to each row, and a bit line provided corresponding to each column. Line pair BL, / BL.

Each memory cell MC is a well-known memory cell including an N-channel MOS transistor for access and a capacitor for storing information. The word line WL is connected to the row decoder 3
3 to activate the memory cells MC in the selected row. Bit line pair BL, / BL inputs and outputs a data signal to and from selected memory cell MC.

The redundant memory cells 38 have a smaller number of columns than the memory array 37, except that the number of columns is smaller than that of the memory array 37.
It has the same configuration as. The memory array 37 and the redundant memory array 38 have the same number of rows, and the word line WL is shared by the memory array 37 and the redundant memory array 38.

The sense amplifier + input / output control circuit 39 includes a column selection gate 42, a sense amplifier 43, and an equalizer 44 provided corresponding to each column. Column selection gate 42
Are a pair of bit lines BL, / BL and a pair of data input / output lines IO,
/ IO includes a pair of N-channel MOS transistors. The gate of each N-channel MOS transistor is connected to column decoder 34 or 35 via column select line CSL. When column select line CSL is raised to the selected level "H" level by column decoder 34 or 35, a pair of N-channel MOS transistors are rendered conductive,
Bit line pair BL, / BL and data input / output line pair IO, / I
O is combined.

Sense amplifier 43 has sense amplifier activation signals SE and / SE at "H" level and "L" level, respectively.
Level, the bit line pair BL, / BL
The small potential difference between them is amplified to the power supply voltage Vcc. Equalizer 44 changes the potentials of bit line pair BL and / BL to bit line potential VBL (= Vcc /
Equalize to 2).

Next, the operation of the DRAM shown in FIGS. 8 and 9 will be briefly described. In the write mode, column decoder 34 or 35 supplies column address signal CA
The column selection line CSL of the column corresponding to 0 to CAi is raised to the activation level “H” level, and the column selection gate 42 is turned on.

In response to signal / W, input buffer 40 supplies external write data to bit line pair BL, / BL of the selected column via data input / output line pair IOP. Write data is applied as a potential difference between bit lines BL and / BL. Next, row decoder 33 raises word line WL of the row corresponding to row address signals RA0-RAi to an activation level of "H" level, and memory cell M of that row is activated.
The C N-channel MOS transistor is turned on. The bit line BL is connected to the capacitor of the selected memory cell MC.
Alternatively, an amount of charge corresponding to the potential of / BL is stored.

In the read mode, first, bit line equalize signal BLEQ falls to "L" level, and equalization of bit lines BL and / BL is stopped. Row decoder 33 raises word line WL of the row corresponding to row address signals RA0-RAi to the selected level “H”. The potentials of bit lines BL and / BL change by a small amount according to the amount of charge of the capacitor of activated memory cell MC.

Next, a sense amplifier activation signal SE, /
SE becomes “H” level and “L” level, respectively, and sense amplifier 43 is activated. When the potential of bit line BL is slightly higher than the potential of bit line / BL, the potential of bit line BL is raised to "H" level, and the potential of bit line / BL is lowered to "L" level. Conversely, when the potential of bit line / BL is slightly higher than the potential of bit line BL, the potential of bit line / BL is raised to "H" level and the potential of bit line BL is lowered to "L" level. Can be

Next, column decoder 34 or 35 applies column selection line CS of the column corresponding to column address signals CA0-CAi.
L is raised to the "H" level of the selection level, and the column selection gate 42 of that column is made conductive. Data of the bit line pair BL, / BL of the selected column is applied to output buffer 41 via column select gate 42 and data input / output line pair IO, / IO. Output buffer 41 externally connects read data in response to signal / OE.

When column address signals CA0-CAi correspond to columns including defective memory cells MC, writing and reading are performed only by selecting columns of redundant memory array 38 instead of columns including defective memory cells MC. The operation is performed similarly.

As described above, in a memory integrated circuit such as a DRAM, in order to improve the rate of non-defective chips on a wafer, a method of replacing a defective row or column with a spare row or column is adopted. A program circuit is provided for pre-programming the addresses of various rows and columns.

In the conventional program circuit, a defective row or column address is programmed depending on whether or not each of a plurality of fuses is cut. However, since a laser device is used to cut the fuses, the device is not used. There were problems such as high cost and poor fuse cutting accuracy.

Therefore, a program circuit using an antifuse that does not require a laser device has been studied. This antifuse has a capacitor type structure,
Although it is a capacitor, that is, an open circuit as it is, when a high voltage (about 10 V or more) is applied and blown, a conductive path is generated in the insulating layer, and the resistance element has a resistance of about several kΩ.

FIG. 10 is a circuit diagram showing a configuration of a fuse circuit 50 including an antifuse and its blow circuit. Such a fuse circuit is disclosed, for example, in US Pat.
No. 31,862.

Referring to FIG. 10, this fuse circuit 50
Are anti-fuse 51, P-channel MOS transistors 52-54, N-channel MOS transistors 55-5
9 and an inverter 60. MOS transistor 5
Reference numerals 2, 54, and 55 denote a power supply potential Vcc line and a node N.
55 are connected in series. The gate of P-channel MOS transistor 52 receives signal TRAS. Signal TR
AS is a trigger signal that is at the “L” level during the address detection period and is at the “H” level during other periods.

P channel MOS transistor 54 has its gate connected to the ground potential GND line and is always in a conductive state. The channel length and channel width of P-channel MOS transistor 54 are set such that the conduction resistance of P-channel MOS transistor 54 is about 300 kΩ. N channel MOS transistor 55
Receive signal DVCE. Signal DVCE is an enable signal for the fuse circuit, and is set to laser Vcc / 2, which is 1/2 of power supply potential Vcc, when blowing antifuse 51 and detecting an address. The channel length and channel width of N-channel MOS transistor 55 are set such that current driving capability of N-channel MOS transistor 55 is larger than that of P-channel MOS transistor 54.

The inverter 60 is connected to the MOS transistor 5
It is connected between a node N54 between 4 and 55 and the gate of P-channel MOS transistor 53. Inverter 6
The output signal of 0 becomes the output signal FR of this fuse circuit. The signal FR becomes an input signal of a NOR type or NAND type address comparison circuit that compares an input address signal with a programmed address signal ADDR.

N-channel MOS transistor 56 is connected between node N55 and a line of ground potential GND, and has a gate receiving reset signal RST. Reset signal RST is set to “H” level when setting the initial state of the fuse circuit. N-channel MOS transistors 57 and 58 are connected in series between node N55 and a line of ground potential GND, and have respective gates receiving address ADDR and signal FR, respectively.

N channel MOS transistor 59 is connected between node N55 and one electrode of antifuse 51, and has its gate connected to the line of power supply potential Vcc. The N-channel MOS transistor 59 prevents the voltage higher than the withstand voltage of the gate oxide film from being applied between the source and the gate or between the drain and the gate of the N-channel MOS transistors 55 to 57 when the antifuse 51 is blown. MOS transistors 55 to 57
To protect.

The other electrode of the antifuse 51 is connected to a terminal T
51. The ground potential GND is applied to the terminal T51 in the normal operation mode, and a high voltage is applied to blow the antifuse 51.

Next, the operation of the fuse circuit will be described. When programming a defective address, first, signal TRAS is set to "H" level, signal RST is set to "H" level, nodes N54 and N55 are set to "L" level, and signal FR is set to "H" level. Raise signal RS
Return T to the “L” level.

Next, the address signal ADDR corresponding to the defective address is set to "H" level, and the antifuse 5
1 are connected to N-channel MOS transistors 59 and 5
7, 58 to ground. Next, a high voltage is applied to the terminal T51 to blow the antifuse 51.

When the antifuse 51 is blown, the antifuse 51 and the N-channel
Ground potential GN via S transistors 59, 57, 58
A current flows through the line D, and as the current increases, the node N
The potentials of 54 and N55 increase. When the potential of the node N54 rises above the logic threshold potential of the inverter 60,
When signal FR attains the "L" level, N channel MOS transistor 58 is rendered non-conductive, and the current path to the ground potential GND line is cut off. This prevents an excessive current from flowing through the circuit when the antifuse 51 is blown.

In the normal operation mode, the terminal T51
Are grounded, and signal TRAS attains an “L” level. If the antifuse 51 is not blown, the node N
54 and N55 become “H” level, and the signal FR becomes “L”.
Latched to level.

When the antifuse 51 is blown, the node N55 is at the ground potential GND because the fuse 51 is a resistance element of several kΩ. Since N-channel MOS transistor 55 has a higher current driving capability than P-channel MOS transistor 54, the potential of node N54 becomes lower than the logical threshold potential of inverter 60, and signal FR attains the "H" level. When an address corresponding to an address detection circuit block in which signal FR is at "H" level is input, it is determined that a defective address has been input, and a corresponding defective row or column is replaced with a spare row or column. You.

[0036]

As described above, in the conventional fuse circuit 50, a protection circuit for preventing an overcurrent from flowing through the circuit when the resistance value of the antifuse 51 decreases, that is, an N-channel MOS transistor 58
And the inverter 60 are provided. However, the N-channel MOS transistor 58 and non-conduction of the N-channel MOS transistor 58 are delayed due to variations in the logical threshold potential of the inverter 60, and the overcurrent cannot be prevented. Could be destroyed.

As shown in FIG. 11, n (where n is an integer of 2 or more) fuse circuits 50.1
~ 50. When the n terminal T51 is connected to the common terminal T52, and a high voltage is applied to the common terminal T52 for a certain period of time to simultaneously cut a plurality of antifuses 51, a current flows through one antifuse 51 blown first. In some cases, the voltage of the common terminal T52 drops and the other antifuse 51 cannot be blown.

Therefore, a main object of the present invention is to provide a semiconductor device capable of reliably preventing an overcurrent from flowing when an antifuse is blown and its resistance is reduced.

[0039]

The invention according to claim 1 is
A semiconductor device provided with an antifuse whose resistance value is reduced by being blown, comprising a capacitor, a first switching element, a second switching element, and program means. The capacitor is connected between one electrode of the antifuse and the first node and has a predetermined capacitance value. The first switching element is connected between one electrode of the antifuse and the second node. The second switching element is connected between the other electrode of the antifuse and a line of the reference potential. The program means applies a high voltage between the second and first nodes and conducts the first switching element for a predetermined time to charge the capacitor, and then conducts the second switching element to blow the antifuse. I do.

According to the second aspect of the present invention, the program means according to the first aspect of the present invention is characterized in that, after charging the capacitor, the second switching element is turned on and the first switching element is connected between the first node and the reference potential line. A predetermined voltage is applied, the voltage between the electrodes of the antifuse is increased, and the antifuse is blown.

According to a third aspect of the present invention, a third switching element and a current detecting means are further provided in the first or second aspect of the present invention. The third switching element is connected in series to the second switching element. The current detector turns off the third switching element in response to the current flowing through the antifuse exceeding a predetermined value.

In the invention according to claim 4, claims 1 to 3
The invention according to any one of the above, further includes a resistance element, a fourth switching element, and a reading unit. The resistance element and the fourth switching element are connected in series between the other electrode of the antifuse and the first power supply potential line. The read means applies the second power supply potential to the second node and makes the fourth switching element conductive, so that the potential of the other electrode of the anti-fuse is closer to any one of the first and second power supply potentials. It is determined that the antifuse is not blown when it is close to the first power supply potential, and it is determined that the antifuse is blown when it is close to the second power supply potential.

According to a fifth aspect of the present invention, a plurality of the antifuses according to the first aspect of the present invention are provided, and a capacitor, a first switching element, and a second switching element are provided corresponding to each antifuse. A plurality of the second nodes are provided and commonly connected to the third node, and the semiconductor device further includes a selection unit for selecting one or more desired antifuses from the plurality of antifuses. The program means applies a high voltage between the third and first nodes, and conducts the first switching element corresponding to the antifuse selected by the selection means for a predetermined time to charge the corresponding capacitor. The second switching element corresponding to the antifuse is turned on to blow the antifuse.

According to a sixth aspect of the present invention, there is provided a semiconductor device having an antifuse whose resistance value is reduced by being blown, comprising a high resistance element, a first switching element, and program means. The high resistance element is connected between one electrode of the antifuse and the first node and has a predetermined high resistance value. The first switching element is connected between the other electrode of the antifuse and a line of the first power supply potential. The program means is
A high voltage is applied between the first node and the first power supply potential line, and the first switching element is turned on to blow the antifuse.

According to a seventh aspect of the present invention, there is further provided the resistance element, the second switching element, and the reading means in the sixth aspect of the invention. The resistance element and the second switching element are connected in series between one electrode of the antifuse and a line of the second power supply potential. The read means sets the first node to a high impedance state and conducts the first and second switching elements to set the potential of the other electrode of the antifuse to any one of the first and second power supply potentials. It is determined whether or not the antifuse is blown when it is close to the first power supply potential, and it is determined that the antifuse is not blown when it is close to the second power supply potential.

In the invention according to claim 8, a plurality of antifuses according to the invention according to claim 6 are provided, the high resistance element and the first switching element are provided corresponding to each antifuse, and the first node is The semiconductor device further includes a selection unit that selects one or more desired antifuses among the plurality of antifuses, the plurality being provided and commonly connected to the second node. The program means applies a high voltage between the second node and the line of the first power supply potential, and conducts the first switching element corresponding to the antifuse selected by the selection means, thereby turning off the antifuse. To blow.

[0047]

[First Embodiment] FIG. 1 is a circuit diagram showing a configuration of a fuse circuit 1 according to a first embodiment of the present invention, which is compared with FIG.

Referring to FIG. 1, fuse circuit 1 is different from fuse circuit 50 of FIG.
The point is that the S transistors 56 and 58 and the terminal T51 are removed, and the capacitor 2, the N-channel MOS transistor 3, and the terminals T1 and T2 are provided. The capacitance value of the capacitor 2 is selected so that the current flowing through the circuit after the antifuse 51 is blown falls within a level that does not destroy the circuit. Capacitor 2 is connected between the other electrode of antifuse 51 and terminal T1. N
The channel MOS transistor 3 includes an antifuse 51
Is connected between the other electrode and the terminal T2, and the gate thereof receives the signal CG.

The ground potential GND is applied to the terminal T1. The terminal T2 has a ground potential GN in a normal operation mode.
D is applied, and when charging the capacitor 2, a high voltage VH is applied. Signal CG attains an "H" level during normal operation mode and when capacitor 2 is charged to high voltage VH.

Next, the operation of the fuse circuit 1 will be described. The enable signal DVCE is supplied to the fuse circuit 1
Is set to Vcc / 2. When programming a defective address, first, the signal TRAS is set to “H” level, the address signal ADDR is set to “L” level, and
The transistors 52 and 57 are turned off.

Then, as shown in FIG. 2, at time t1, signal CG is set to "H" level to turn on N-channel MOS transistor 3 and to apply high voltage VH to terminal T2.
Is applied. Thereby, the capacitor 2 is charged, and the node N1 between the capacitor 2 and the antifuse 51 becomes the high voltage VH.

Next, at time t2, the signal CG is set at "L" level to turn off the N-channel MOS transistor, and the terminal T2 is returned to the ground potential GND.
Address signal ADDR corresponding to the defective address is set to "H"
Level to make the N-channel MOS transistor 57 conductive. As a result, the high voltage VH is applied between the electrodes of the antifuse 51, and the antifuse 51 is blown. At this time, since N-channel MOS transistor 3 is nonconductive, no overcurrent flows from terminal T2 to the ground potential GND line via antifuse 51 and N-channel MOS transistors 59 and 57.

In the normal operation mode, the terminal T2 is grounded, the signal CG is set to "H" level, and the N-channel
The S transistor 3 is turned on, the signal TRAS is set to the “L” level, and the P-channel MOS transistor 52 is turned on. When the antifuse 51 is not blown, the nodes N54 and N55 go to "H" level, and the signal FR goes to "L" level.

When the antifuse 51 is blown, the node N55 is at the ground potential GND because the antifuse 51 is a resistance element of several kΩ. N channel M
Since OS transistor 55 has a higher current driving capability than P-channel MOS transistor 54, the potential of node N54 becomes lower than the logical threshold potential of inverter 60, and signal FR attains the "H" level. Signal FR is "H"
If an address corresponding to the address detection circuit block at the level is input, it is determined that a defective address has been input, and the corresponding defective row or column is replaced with a spare row or column.

In this embodiment, the capacitor 2 having a predetermined capacitance value is charged to the high voltage VH, and the charged voltage VH of the capacitor 2 is applied to the antifuse 51 to blow. Therefore, even if the antifuse 51 is blown to lower the resistance, only the charge charged in the capacitor 2 flows in the circuit, and no overcurrent flows in the circuit.

As shown in FIG. 3, n fuse circuits 1.1 to 1.. Even when the n terminal T2 is connected to the common terminal T3, a plurality of antifuses 51 can be blown simultaneously and reliably. More specifically, the fuse circuit 1.1
~ 1. n gates of N-channel MOS transistors 57 are supplied with address signals ADDR1 to ADDRn, respectively, and fuse circuits 1.1 to 1.. n N-channel MOs
Signals CG1 to CG are provided at the gate of the S transistor 3, respectively.
Gn is provided. Fuse circuits 1.1-1. n outputs signals FR1 to FRn, respectively.

When programming a defective address, M
After turning off the OS transistors 52 and 57, the fuse circuits 1.1 to 1.. n to fuse the antifuse 51 (for example, 1.1 and 1..
n) (in this case, CG1 and CGn) are set to the “H” level to set the fuse circuits 1.1, 1.. The n-channel MOS transistor 3 is turned on, and the high voltage VH is applied to the common terminal T3 so that the fuse circuits 1.1,
1. The n capacitors 2 are charged.

Next, N-channel MOS transistor 3
Of the fuse circuits 1.1, 1.. address signal ADDR corresponding to n
1, ADDRn is set to "H" level, and N-channel MOS
The transistor 57 is turned on. Thereby, the fuse circuits 1.1, 1. The high voltage VH is separately applied between the electrodes of the n antifuses 51, and the antifuses 51 are blown. At this time, the fuse circuits 1.1 to 1.. N of n
The channel MOS transistor 3 is rendered non-conductive and the fuse circuits 1.1 to 1.. Since the n-th antifuse 51 and the common terminal T3 are separated from each other, current flows intensively through one antifuse 51 from the common terminal T3 as shown in the circuit of FIG. Never end.

Although the ground potential GND is applied to the terminal T1 in this embodiment, the ground potential GND is applied to the terminal T1.
A potential other than D may be applied. For example, by applying an intermediate potential VH / 2 between the high potential VH and the ground potential GND to the terminal T1, the voltage between the electrodes of the capacitor 2 can be suppressed to VH / 2 or less, and the capacitor 2 is destroyed by the high voltage VH. Can be prevented.

In this embodiment, the terminal T1 is fixed at the ground potential GND. However, as shown in FIG.
In step 2, the potential may be raised from the ground potential GND to a predetermined potential V1. In this case, the voltage between the electrodes of the anti-fuse 51 can be increased to VH + V1, so that the anti-fuse 51 can be blown more reliably. Also in this case, the voltage between the electrodes of the capacitor 2 is suppressed to VH / 2 or less by boosting the terminal T1 from the intermediate potential VH / 2 between the high potential VH and the ground potential GND to the predetermined potential V1, thereby insulating the capacitor 2 Destruction can be prevented.

[Second Embodiment] FIG. 5 is a circuit diagram showing a configuration of a program circuit according to a second embodiment of the present invention, which is compared with FIG.

Referring to FIG. 5, the program circuit comprises:
Fuse circuit 50.1-50. n, capacitors 5.1 to 5. n, switches 6.1 to 6. n, terminals T5.1 to T5.1
5. n, and a common terminal T6.

Fuse circuits 50.1 to 50. n has the same configuration as the fuse circuit 50 of FIG. Fuse circuit 50.1-50. n are the signals FR1 to FR1, respectively.
Output FRn. Fuse circuit 50.1-50. The address signals ADDR1 to ADDRn are applied to the gates of the n-channel MOS transistors 57, respectively, and the fuse circuits 50.1 to 50. Signals FR1 to FRn are connected to the gates of n-channel N-channel MOS transistors 58, respectively.
Is given.

Terminals T5.1 to T5. n is the ground potential GN
D is applied. In the normal operation mode, the ground potential GND is applied to the terminal T6, and the capacitors 5.1 to 5. n
Is charged, a high voltage VH is applied. Capacitors 5.1-5. n is the fuse circuit 50.1 to
50. n terminal T51 and terminals T5.1 to T5. n. Switches 6.1 to 6. n are fuse circuits 50.1 to 50. n is connected between the terminal T51 and the common terminal T6. Switches 6.1 to 6. n is
In the normal operation mode and when the capacitors 5.1-5. Conducts when n is charged to the high voltage VH.

When programming a defective address, M
OS transistors 52, 56, 57 are turned off and MOS
After the transistors 55 and 58 are turned on, the fuse circuits 50.1 to 50. n of the fuse circuits (for example, 50.1 and 5
0. n) (in this case, 6.1, 6..
n), and the high voltage VH is applied to the common terminal T6.
To give capacitors 5.1, 5. Charge n.

Next, the switches 6.1, 6. n and the common terminal T6 are grounded, and the fuse circuit 5
0.1,50. n of the address signal ADDR1,
ADDRn is set to “H” level to make N-channel MOS transistor 57 conductive. Thereby, the fuse circuits 50.1, 50. The high voltage VH is separately applied between the electrodes of the n antifuses 51, and the antifuses 51 are blown.

At this time, the switches 6.1 to 6. n are rendered non-conductive and fuse circuits 50.1 to 50. Since the antifuse 51 and the common terminal T6 are separated from each other, FIG.
As in the circuit of No. 1, current intensively flows from the common terminal T6 to one antifuse 51 and the other antifuse 51
Blows never fail.

When the resistance value of antifuse 51 decreases and the current flowing through the circuit increases, the potentials of nodes N54 and N55 rise, signals FR1 and FRn fall to "L" level, and N-channel MOS transistor 58 operates. It becomes non-conductive and the blowing of the antifuse 51 ends.

In this embodiment, terminal T5.1 is used.
~ T5. n is applied with the ground potential GND, but the terminal T5.
1 to T5. A potential other than the ground potential GND may be applied to n. For example, intermediate potential VH / 2 between high potential VH and ground potential GND is applied to terminals T5.1 to T5. n, the capacitors 5.1 to 5.. nH between electrodes
/ 2 or less, and the capacitors 5.1 to 5.
It is possible to prevent n from being destroyed by the high voltage VH.

Also in this embodiment, fuse circuits 50.1 to 5 to blow antifuse 51 should be used.
0. n corresponding to terminals T5.1 to T5. n may be raised from “L” level to “H” level together with address signals ADDR1 to ADDRn. In this case, the voltage between the electrodes of the antifuse 51 can be increased to a voltage higher than the high voltage, so that the antifuse 51 can be blown more reliably. Note that also in this case, the terminals T5.1 to T5. n is boosted from the intermediate potential VH / 2 between the high potential VH and the ground potential GND to a predetermined potential V1, whereby the capacitors 5.1 to 5.1
5. n of the capacitors 5.1 to 5. n can be prevented from being broken down.

[Third Embodiment] FIG. 6 is a circuit diagram showing a configuration of a fuse circuit 10 according to a third embodiment of the present invention, which is compared with FIG.

Referring to FIG. 6, fuse circuit 10 is different from fuse circuit 50 of FIG.
The point is that the OS transistors 56 to 58 and the terminal T51 are removed, and the N-channel MOS transistors 11, 12 and the terminals T11 to T13 are provided.

P channel MOS transistor 11 is connected between one electrode of antifuse 51 (source of N channel MOS transistor 59) and terminal T11.
Its gate is grounded. The conduction resistance value of the P-channel MOS transistor 11 is selected so that the current flowing through the circuit after the antifuse 51 is blown falls within a level that does not destroy the circuit. N-channel MOS transistor 12 is connected between the other electrode of antifuse 51 and the line of ground potential GND, and has its gate connected to terminal T12. Terminal T13 is an N-channel MOS
Connected to the gate of transistor 59.

The terminal T11 receives the high voltage VH when blowing the antifuse 51, and is brought into a high impedance state in a normal operation mode. The terminal T12 is supplied with an address signal ADDR of "H" level when blowing the antifuse 51, and is supplied with the power supply potential Vcc in a normal operation mode. The terminal T13 is supplied with the ground potential GND when blowing the antifuse 51, and is supplied with the power supply potential Vcc in the normal operation mode.

Next, the operation of the fuse circuit 10 will be described. The enable signal DVCE is set to Vcc / 2 when the fuse circuit 10 operates. When programming a defective address, first, the signal TRAS is set to the "H" level to turn off the P-channel MOS transistor 52, and the ground potential GND is applied to the terminal T13 to turn off the N-channel MOS transistor 59.

Then, an "H" level address signal ADDR is applied to terminal T12 to turn on N-channel MOS transistor 12, and high voltage VH is applied to terminal T11.
To blow the antifuse 51. At this time,
Since the high-resistance P-channel MOS transistor 11 is provided between the terminal T11 and the anti-fuse 51, even if the resistance of the anti-fuse 51 is reduced, the P-channel MOS transistor 11, the anti-fuse 51 and the N-channel MOS transistor An overcurrent does not flow through the line of the ground potential GND via the line 12.

In the normal operation mode, the signal TRA
S is set to the “L” level to turn on the P-channel MOS transistor 52, and the power supply potential Vcc is applied to the terminals T12 and T13.
Is applied to make the N-channel MOS transistors 12 and 59 conductive, and the terminal T11 is brought into a high impedance state. When the antifuse 51 is not blown, the nodes N54 and N55 are at "H" level, and the signal FR is at "L" level.

When the antifuse 51 is blown, the node N55 is at the ground potential GND because the antifuse 51 is a resistance element of several kΩ. N channel M
Since OS transistor 55 has a higher current driving capability than P-channel MOS transistor 54, the potential of node N54 becomes lower than the logical threshold potential of inverter 64, and signal FR attains "H" level. Signal FR is "H"
If an address corresponding to the address detection circuit block at the level is input, it is determined that a defective address has been input, and the corresponding defective row or column is replaced with a spare row or column.

In this embodiment, the high voltage VH is applied to the antifuse 51 via the high-resistance P-channel MOS transistor 11, so that even if the antifuse 51 is blown to lower the resistance, an overcurrent flows through the circuit. Never.

Further, since the polarity of the voltage applied to the anti-fuse 51 is the same between when the anti-fuse 51 is blown and during the normal operation mode, it is possible to read the signal FR with high reliability. In the fuse circuit 50 shown in FIG. 10, the polarity of the voltage applied to the anti-fuse 51 is reversed between when the anti-fuse 51 is blown and in the normal operation mode, so that the reliability of reading the signal FR is low. Become. This is because the resistance value of the blown antifuse 51 may differ depending on the polarity of the voltage applied between the electrodes.

As shown in FIG. 7, n fuse circuits 10.1 to 10. n terminal T11 to common terminal T14
Can be blown simultaneously and reliably. More specifically, the fuse circuits 10.1 to 10. n N-channel MOS transistors 12 have terminals T12.1 to T12. n are connected, and the fuse circuits 10.1 to 10.. n N-channel MOs
Terminals T13.1 to T1 are connected to the gate of S transistor 59.
3. n is connected. Fuse circuits 10.1 to 10. n
Output signals FR1 to FRn, respectively.

When programming a defective address, M
After the OS transistors 52 and 59 are turned off, the fuse circuits 10.1 to 10. Antifuse 51 of n
Circuit (for example, 10.1)
And 10. n) corresponding to the terminals T12.1, T12. n are supplied with address signals ADDR1 and ADDRn of “H” level, and fuse circuits 10.1, 10. n N channels M
The OS transistor 12 is turned on, and the high voltage VH is applied to the common terminal T14.

Thus, the fuse circuits 10.1, 1
0. The high voltage VH is applied to the n antifuse 51,
The antifuse 51 is blown. At this time, the common terminal T14 is connected to the high-resistance P-channel MOS transistor 11
Is connected to the antifuse 51 via the
The common terminal T14 is kept at the high voltage VH even after the resistance values of the two antifuses 51 have decreased, and the other antifuses 51
It will not hinder the blow. Therefore, a plurality of antifuses 51 can be reliably blown simultaneously.

It should be noted that the embodiments disclosed this time are illustrative in all aspects and are not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0085]

As described above, according to the first aspect of the present invention, a capacitor having a predetermined capacitance value is connected between one electrode of the antifuse and the first node, and one electrode of the antifuse is connected to the second electrode. The first switching element is connected between the node and the node, and the second switching element is connected between the other electrode of the antifuse and the line of the reference potential.
Then, the program means applies a high voltage between the second and first nodes, charges the capacitor by turning on the first switching element for a predetermined time, and then turns on the second switching element to turn on the anti-static switch. Blow the fuse. Therefore, even if the antifuse is blown to lower the resistance, only the electric charge charged in the capacitor flows to the circuit, so that no overcurrent flows to the circuit.

According to the second aspect of the present invention, the program means of the first aspect of the present invention is configured such that, after charging the capacitor, the second switching element is turned on and the first switching element is connected between the first node and the reference potential line. A predetermined voltage is applied, the voltage between the electrodes of the antifuse is increased, and the antifuse is blown. In this case, a higher voltage can be applied between the electrodes of the antifuse, so that the antifuse can be blown reliably.

According to a third aspect of the present invention, in the first or second aspect, the current flowing through the third switching element connected in series to the second switching element and the antifuse exceeds a predetermined value. Current detecting means for turning off the third switching element in response to the control signal. In this case, an overcurrent can be more reliably prevented from flowing through the circuit.

According to the fourth aspect of the invention, the first to third aspects are described.
And a fourth switching element connected in series between the other electrode of the antifuse and the first power supply potential line, and a second power supply potential applied to the second node. And the fourth switching element is turned on to detect which one of the first and second power supply potentials is closer to the potential of the other electrode of the antifuse, and the antifuse is blown based on the detection result. Reading means for determining whether or not the reading is performed is further provided. In this case, it can be easily detected whether or not the antifuse is blown.

In the invention according to claim 5, a plurality of the antifuses according to the invention according to claim 1 are provided, and the capacitor, the first switching element and the second switching element are provided corresponding to each antifuse. A plurality of two nodes are provided and commonly connected to the third node, and the semiconductor device further includes a selection unit for selecting one or more desired antifuses from the plurality of antifuses. Then, the program means applies a high voltage between the third and first nodes, and conducts the first switching element corresponding to the antifuse selected by the selection means for a predetermined time to charge the corresponding capacitor. Thereafter, the second switching element corresponding to the antifuse is turned on to blow the antifuse.
In this case, since the charging voltage of the corresponding capacitor is applied independently to each anti-fuse, a current is applied to one anti-fuse as in the conventional case where a high voltage is simultaneously applied to a plurality of anti-fuses from a common node. Concentrated blows of other antifuses never fail. Therefore, a plurality of antifuses can be reliably blown simultaneously.

In the invention according to claim 6, a high-resistance element having a predetermined resistance value is connected between one electrode of the anti-fuse and the first node, and the other electrode of the anti-fuse is connected to the first power supply potential line. The first switching element is connected between the two. Then, the program means applies a high voltage between the first node and the line of the first power supply potential, makes the first switching element conductive, and blows the antifuse. Therefore, even if the antifuse is blown to lower the resistance, the upper limit of the current flowing in the circuit is limited by the high resistance element, so that no overcurrent flows in the circuit.

According to a seventh aspect of the present invention, in the sixth aspect of the invention, there is provided a resistance element and a second switching element connected in series between one electrode of the antifuse and a line of the second power supply potential, The first node is set to a high impedance state and the first and second switching elements are turned on to detect which of the first and second power supply potentials the potential of the other electrode of the antifuse is closer to. Further, there is further provided reading means for determining whether or not the antifuse is blown based on the detection result. In this case, it can be easily detected whether or not the antifuse is blown.

In the invention according to claim 8, a plurality of the antifuses according to the invention according to claim 6 are provided, the high-resistance element and the first switching element are provided corresponding to each antifuse, and the first node is provided. The semiconductor device further includes a selection unit that selects one or more desired antifuses among the plurality of antifuses, the plurality being provided and commonly connected to the second node. Then, the programming means applies a high voltage between the second node and the line of the first power supply potential, and conducts the first switching element corresponding to the anti-fuse selected by the selection means, thereby causing the anti-fuse to conduct. Blow the fuse. In this case, a high-resistance element is connected between the second node and one electrode of each anti-fuse, so that even if one anti-fuse has a low resistance, the high voltage of the second node does not decrease. It is possible to reliably blow multiple antifuses simultaneously.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a fuse circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the fuse circuit illustrated in FIG. 1;

FIG. 3 is a circuit diagram for explaining an effect of the fuse circuit shown in FIG. 1;

FIG. 4 is a time chart for explaining a modification of the first embodiment.

FIG. 5 is a circuit diagram showing a configuration of a program circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a fuse circuit according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram for explaining an effect of the fuse circuit shown in FIG. 6;

FIG. 8 is a block diagram showing an entire configuration of a conventional DRAM.

FIG. 9 is a circuit block diagram showing a configuration of a memory mat shown in FIG.

FIG. 10 is a circuit diagram showing a configuration of a conventional fuse circuit.

11 is a circuit diagram for explaining a problem of the fuse circuit shown in FIG.

[Explanation of symbols]

1,10,50 fuse circuit, 2,5 capacitor,
3,12,55-59 N channel MOS transistor,
6 switches, 11, 52 to 54 P-channel MOS transistors, 30 DRAMs, 31 clock generation circuits, 32 row and column address buffers, 33 row decoders, 34 column decoders, 35 redundant column decoders, 36
Memory mat, 37 memory array, 38 redundant memory array, 39 sense amplifier + input / output control circuit, 40
Input buffer, 41 output buffer, 42 column selection gate, 43 sense amplifier, 44 equalizer, 51
Anti-fuse, 60 inverter, T terminal.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroki Shimano 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5B024 AA01 AA03 BA18 BA29 CA07 5F064 CC09 CC22 CC23 DD39 FF45 FF46 5L106 AA01 CC04 CC13

Claims (8)

[Claims] 1. A semiconductor device having an anti-fuse whose resistance value is reduced by being blown, comprising: a predetermined capacitor connected between one electrode of the anti-fuse and a first node. A capacitor having a value, a first switching element connected between one electrode of the antifuse and a second node, a second switching element connected between the other electrode of the antifuse and a line of a reference potential. After applying a high voltage between the switching element and the second and first nodes and conducting the first switching element only for a predetermined time to charge the capacitor, the second switching element is made conductive. A semiconductor device comprising program means for blowing the antifuse. 2. The program means, after charging the capacitor, turns on the second switching element and applies a predetermined voltage between the first node and a line of the reference potential. 2. The semiconductor device according to claim 1, wherein the antifuse is blown by increasing a voltage between electrodes of the antifuse. 3. The third switching element connected in series with the second switching element, and the third switching element in response to a current flowing through the antifuse exceeding a predetermined value. 3. The semiconductor device according to claim 1, further comprising: a current detection unit configured to turn off the current. 4. 4. A resistance element and a fourth switching element connected in series between the other electrode of the antifuse and a line of a first power supply voltage, and a second power supply potential at the second node. And the fourth switching element is turned on to detect which of the first and second power supply potentials the potential of the other electrode of the antifuse is closer to, the first power supply potential If the anti-fuse is close to the second power supply potential, it is determined that the anti-fuse is not blown.
The semiconductor device according to claim 1. 5. A plurality of antifuses are provided, the capacitor, the first switching element, and the second switching element are provided corresponding to each antifuse, and a plurality of second nodes are provided. 3, the semiconductor device further includes selection means for selecting one or two or more desired antifuses from the plurality of antifuses, and wherein the program means includes the third and first antifuses. A high voltage is applied between the nodes and the first switching element corresponding to the antifuse selected by the selection means is turned on for a predetermined time to charge the corresponding capacitor, and then the second switching element corresponding to the antifuse is charged. Conducts the switching element and blows its antifuse.
The semiconductor device according to claim 1. 6. A semiconductor device comprising an antifuse whose resistance value is reduced by being blown, wherein the semiconductor device is connected between one electrode of the antifuse and a first node and has a predetermined high value. A high-resistance element having a resistance value; a first switching element connected between the other electrode of the anti-fuse and a first power supply potential line; and a line between the first node and the first power supply potential And a program means for applying a high voltage between the first and second switching elements and conducting the first switching element to blow the antifuse. 7. A resistance element and a second switching element connected in series between one electrode of the antifuse and a line of a second power supply potential, and the first node are set to a high impedance state. The first and second switching elements are turned on to detect which of the first and second power supply potentials the potential of the other electrode of the antifuse is closer to, and the first power supply 7. The semiconductor according to claim 6, further comprising a reading unit that determines that the antifuse is blown when the potential is close to the potential, and determines that the antifuse is not blown when the potential is close to the second power supply potential. apparatus. 8. A plurality of the antifuses are provided, the high resistance element and the first switching element are provided corresponding to each antifuse, and a plurality of the first nodes are provided and shared by a second node. Connected, the semiconductor device further includes a selection unit that selects one or two or more desired antifuses from the plurality of antifuses, and the program unit includes the second node and the first power supply. 7. The semiconductor device according to claim 6, wherein a high voltage is applied between the anti-fuse and a first switching element corresponding to the anti-fuse selected by the selection means, and the anti-fuse is blown.