JPS6226932U - - Google Patents
Info
- Publication number
- JPS6226932U JPS6226932U JP1985118080U JP11808085U JPS6226932U JP S6226932 U JPS6226932 U JP S6226932U JP 1985118080 U JP1985118080 U JP 1985118080U JP 11808085 U JP11808085 U JP 11808085U JP S6226932 U JPS6226932 U JP S6226932U
- Authority
- JP
- Japan
- Prior art keywords
- detection circuit
- level detection
- output
- automatic gain
- gain adjustment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Circuits Of Receivers In General (AREA)
- Superheterodyne Receivers (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Description
第１図は本考案の一実施例よりなるＰＬＬシン
セサイザーチユーナーのブロツク図、および第２
図は従来のＰＬＬシンセサイザーチユーナーのブ
ロツク図である。
１……ミキサーおよび局部発振器、５……ＡＧ
Ｃアンプ、７……レベル検波回路、８……マイコ
ン、９……比例回路。
FIG. 1 is a block diagram of a PLL synthesizer tuner according to an embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional PLL synthesizer tuner. 1...mixer and local oscillator, 5...AG
C amplifier, 7...level detection circuit, 8...microcomputer, 9...proportional circuit.
Claims (1)
を検波する回路を有するＰＬＬシンセサイザーチ
ユーナーにおいて、自動利得調整アンプおよび前
記レベル検波回路の出力を切り換える手段を設け
、スキヤン状態あるいはシーク状態か否かに応じ
て前記レベル検波回路の出力と自動利得調整アン
プとを切り換えて出力し、かつ、自動利得調整ア
ンプの選択中は前記レベル検波回路の動作を止め
るように構成したことを特徴とするＰＬＬシンセ
サイザーチユーナー。 A PLL synthesizer tuner having a circuit for detecting the level of an intermediate frequency signal passed through a bandpass filter is provided with means for switching the output of an automatic gain adjustment amplifier and the level detection circuit, and the output of the level detection circuit is changed depending on whether the scan state or the seek state is selected. A PLL synthesizer tuner characterized in that the output of a level detection circuit and an automatic gain adjustment amplifier are switched and outputted, and the operation of the level detection circuit is stopped while the automatic gain adjustment amplifier is selected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985118080U JPS6226932U (en) | 1985-08-02 | 1985-08-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985118080U JPS6226932U (en) | 1985-08-02 | 1985-08-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6226932U true JPS6226932U (en) | 1987-02-18 |
Family
ID=31004193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985118080U Pending JPS6226932U (en) | 1985-08-02 | 1985-08-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6226932U (en) |
-
1985
- 1985-08-02 JP JP1985118080U patent/JPS6226932U/ja active Pending
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