JPS6226522A - Service interruption detection and power recovery control system - Google Patents
Service interruption detection and power recovery control systemInfo
- Publication number
- JPS6226522A JPS6226522A JP60167035A JP16703585A JPS6226522A JP S6226522 A JPS6226522 A JP S6226522A JP 60167035 A JP60167035 A JP 60167035A JP 16703585 A JP16703585 A JP 16703585A JP S6226522 A JPS6226522 A JP S6226522A
- Authority
- JP
- Japan
- Prior art keywords
- power
- service interruption
- power source
- processor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
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Abstract
Description
【発明の詳細な説明】
〔概要〕
マイクロプロセッサ等に電源を供給する制御を行う電源
制御方式において、電池により常時サポートされている
独立した電源を用いて、停電が検出されてからの時間を
監視し、停電が検出されてから、所定の時間が経過する
まで、復電時における電源投入信号の出力を抑止するよ
うにし、瞬断等によるマイクロプロセッサ等の誤動作発
生を防止している。[Detailed Description of the Invention] [Summary] In a power supply control method that controls the supply of power to a microprocessor, etc., the time elapsed after a power outage is detected is monitored using an independent power supply that is constantly supported by a battery. However, the output of a power-on signal upon power restoration is suppressed until a predetermined period of time has elapsed after a power outage is detected, thereby preventing malfunctions of microprocessors and the like due to instantaneous power outages.
本発明は停電検出・復電制御方式、特にマイクロプロセ
ッサやその他の論理回路に対する電源を制御する回路で
あって、停電後における復電時の再起動に関する動作を
保障する停電検出・復電制御方式に関するものである。The present invention relates to a power outage detection/recovery control method, particularly a circuit that controls power to a microprocessor and other logic circuits, and which guarantees restart operations when power is restored after a power outage. It is related to.
マイクロプロセッサ等は、逐次、所定の命令をフェッチ
して実行し、予めプログラムされたデータ処理制御を行
う。従って、停電が起きた場合。A microprocessor or the like sequentially fetches and executes predetermined instructions to perform preprogrammed data processing control. Therefore, if a power outage occurs.
一般にマイクロプロセッサ等の動作は保障されず復電時
には、イニシャルクリアを行った後、再起動する必要が
ある。また5停電により装置の交流(A C)人力が切
断された場合、投入状態を保持し、記t=シておく必要
がある。Generally, the operation of microprocessors and the like is not guaranteed, and when power is restored, it is necessary to perform an initial clear and then restart. In addition, if the alternating current (AC) power of the device is cut off due to a power outage, it is necessary to maintain the on state and write down.
従来、停電に関する状態を保持するため2例えば投入信
号自体をスイッチ等の機械的なものにより、固定するよ
うにされていた。また、投入信号がパルス状のもので、
AC入力切断により、消滅してしまう場合には1例えば
ラッチングリレー等により状態を保持するようにされて
いた。Conventionally, in order to maintain the state related to a power outage, for example, the input signal itself has been fixed using a mechanical device such as a switch. In addition, the input signal is in the form of a pulse,
If it disappears due to the AC input being cut off, the state is maintained using a latching relay or the like, for example.
上記従来の方式によれば、AC人力が切断された場合に
おける状態をメカニズム的に保持するようにされている
ため、信頼性が充分ではなく、また、停電後すぐに復電
したような場合、即ち、瞬断の場合には、マイクロプロ
セソザ等力福呉動作を起こす可能性があった。According to the above-mentioned conventional method, since the state is mechanically maintained when AC power is cut off, reliability is not sufficient, and when power is restored immediately after a power outage, That is, in the case of a momentary power outage, there is a possibility that the microprocessor may malfunction.
本発明は上記問題点の解決を図り、電池により常時サポ
ートされている電源を用いて、停電検出状態の保持およ
び瞬断時におけるマイクロプロセッサ等の誤動作防止を
同時に実現する。The present invention aims to solve the above-mentioned problems, and uses a power supply that is always supported by a battery to simultaneously maintain a power failure detection state and prevent malfunctions of a microprocessor, etc. in the event of a momentary power failure.
第1図は本発明の基本構成ブロック図である。FIG. 1 is a basic configuration block diagram of the present invention.
第1図において、10はAC入力により動作し。In FIG. 1, 10 operates with AC input.
プロセッサ等に供給する電源の制御を行う電源制御回路
、11はAC入力のパワー等により停電を検出する停電
検出部、12は電源のオン/オフを制御する投入信号を
出力する電源オン/オフ部。A power supply control circuit that controls the power supplied to the processor, etc., 11 a power failure detection unit that detects a power outage based on AC input power, etc., and 12 a power on/off unit that outputs a power supply signal that controls power on/off. .
13は復電時にイニシャルクリア信号を出力するイニシ
ャルクリア部、14は復電再起動保障回路であって、停
電検出部11により停電が検出されてから、所定の時間
が経過するまで、復電時における電源投入信号の出力を
抑止する信号を出力するもの、15(ま上記停電後にお
ける所定の時間経過を計測するタイマ用カウンタ、16
は復電再起動保障回路14に対し直流(D C)電源を
与える電池サポート部、17は電源オン/オフ部12か
らの投入信号に基づき、プロセッサその他の論理回路に
直流を供給する電源部、18は命令をフェッチして実行
するプロセッサを表す。Reference numeral 13 denotes an initial clear unit that outputs an initial clear signal when the power is restored, and 14 is a power recovery restart guarantee circuit, which operates until a predetermined time elapses after the power failure detection unit 11 detects the power failure. 15 (also a timer counter for measuring the elapse of a predetermined period of time after the power outage, 16)
17 is a battery support unit that supplies direct current (DC) power to the power recovery restart guarantee circuit 14; 17 is a power supply unit that supplies DC to the processor and other logic circuits based on the input signal from the power on/off unit 12; 18 represents a processor that fetches and executes instructions.
復電再起動保障回路14の動作電源は、AC入力とは独
立に、電池ザボート部16によってサポートされる。復
電再起動保障回路I4は、停電が起きると、タイマ用カ
ウンタ15によって、カウント動作を開始し、所定のカ
ウント値を計数するまで、電源再投入の可能状態を示す
信号RESTATをオフにするようになっている。The operating power supply of the power recovery restart guarantee circuit 14 is supported by the battery server unit 16 independently of the AC input. When a power failure occurs, the power recovery restart guarantee circuit I4 starts a counting operation using a timer counter 15, and turns off a signal RESTAT indicating a state in which power can be restarted until a predetermined count value is counted. It has become.
AC入力で動作している電源制御回路10が。 A power supply control circuit 10 operates with AC input.
停電検出部11により停電を検出すると、その停電が起
きる一瞬の間に、停電検出は号■、■を復電再起動保障
回路14へ送出する。復電再起動保障回路14は、電池
ナボート部16により、動作電源が保障されているので
、その停電状態を認識し、保持しておくことができる。When a power outage is detected by the power outage detection unit 11, the power outage detection sends the numbers (2) and (2) to the power recovery restart guarantee circuit 14 during the moment when the power outage occurs. Since the power recovery restart guarantee circuit 14 is guaranteed an operating power source by the battery nabort section 16, it can recognize and maintain the power failure state.
復電再起動保障回路I4は、タイマ用カウンタ15等に
よるタイマ回路を持つことにより、停電が瞬断てあって
AC入力が即時に復電しても、停電から所定の時間が経
過するまでは、電源の再投入を禁止する信号を電源オン
/オフ部12に対して送り続ける。即ち、タイマ設定時
間より短い瞬断では、タイマ設定時間経過後に、プロセ
ッサ18に対する電源の再投入が行われ、タイマ設定時
間より長い停電後の復電では、即時に電源の再投入が行
われる。The power recovery restart guarantee circuit I4 has a timer circuit including a timer counter 15, etc., so that even if the AC input is immediately restored after a momentary power outage, the power recovery restart guarantee circuit I4 will not operate until a predetermined period of time has passed since the power outage. , continues to send a signal to the power on/off unit 12 that prohibits turning on the power again. That is, in the case of a momentary power outage that is shorter than the timer setting time, the power to the processor 18 is turned on again after the timer setting time has elapsed, and when the power is restored after a power outage that is longer than the timer setting time, the power is immediately turned on again.
第2図は本発明に係る復電再起動保障回路の−実施例回
路図、第3図は本発明の一実施例タイムチャートを示す
。FIG. 2 is a circuit diagram of an embodiment of a power recovery restart guarantee circuit according to the present invention, and FIG. 3 is a time chart of an embodiment of the present invention.
第2図において、符号14.15は第1図のものに対応
し、20はオア回路、21はフリップフロップ(FF)
を表す。In FIG. 2, numerals 14 and 15 correspond to those in FIG. 1, 20 is an OR circuit, and 21 is a flip-flop (FF).
represents.
例えば第3図に示すタイムチャートのように。For example, like the time chart shown in Figure 3.
AC入力に瞬断が生じたとする。第1図図示停電検出部
11は、ACをDCに変換する際における中間電圧でも
って、その電圧の減少を検出すると。Assume that a momentary interruption occurs in the AC input. The power failure detection unit 11 shown in FIG. 1 detects a decrease in the intermediate voltage when converting AC to DC.
直ちに復電再起動保障回路14に対する出力信号■を“
L”レベルに落とし、その後すぐに出力信号■を“°L
”レベルに落とす。復電再起動保障回路14は、内部ク
ロック信号CLOCKに同期して、出力信号■を第2図
図示フリップフロップ21に取り込み、そのフリップフ
ロップ21の出力は、“H”レベルとなる。Immediately send the output signal ■ to the power recovery restart guarantee circuit 14 as “
After dropping the output signal to “°L” level, immediately
The power recovery restart guarantee circuit 14 takes the output signal ■ into the flip-flop 21 shown in FIG. 2 in synchronization with the internal clock signal CLOCK, and the output of the flip-flop 21 goes to the "H" level. Become.
フリップフロップ21の出力が“H″レベルなると、タ
イマ用カウンタ15はイネーブル状態となり、カウント
動作を開始する。同時に、クリア信号をイニシャルクリ
ア部13に送出し、プロセッサ18をクリアする。タイ
マ用カウンタ15は、所定のクロック・パルス数をカウ
ントすると。When the output of the flip-flop 21 goes high, the timer counter 15 becomes enabled and starts counting. At the same time, a clear signal is sent to the initial clear section 13 to clear the processor 18. The timer counter 15 counts a predetermined number of clock pulses.
電源オン/オフ部12に対する信号RESTATを”H
″レベルする。The signal RESTAT for the power on/off unit 12 is set to “H”.
``Level up.
電源オン/オフ部12は、信号RESTATが“TI”
レベルになったことにより、電源部17に対す°る電源
オン/オフ信号を’ If”レベルにし。The power on/off unit 12 has a signal RESTAT of “TI”.
When the level is reached, the power on/off signal for the power supply section 17 is set to the 'If' level.
電源投入を指示する。これにより、プロセッサ18等に
対するDC出力が開始されることになる。Instructs to turn on the power. As a result, DC output to the processor 18 and the like is started.
以上説明したように1本発明によれば、停電検出状態を
保持し、瞬断による復電時に、電源投入までの時間を、
停電から所定の時間引き伸ばし。As explained above, according to the present invention, the power failure detection state is maintained, and when the power is restored due to a momentary power interruption, the time until the power is turned on is
Extend the specified time after a power outage.
プロセッサ等の誤動作を防止することができるようにな
る。Malfunctions of processors, etc. can be prevented.
第1図は本発明の基本構成ブロック図、第2図は本発明
に係る復電再起動保障回路の一実施例回路図、第3図は
本発明の一実施例タイムチャートを示す。
図中、10は電源制御回路、11は停電検出部。
12は電源オン/オフ部、13はイニシャルクリア部、
14は復電再起動保障回路、15はタイマ用カウンタ、
16は電池ザボート部、17は電源部、18はプロセッ
サを表す。
特許出願人 パナファコム株式会社
代理人弁理士 森1)寛(外1名)
本剃目←某オ橿へ°プ072B
IK 1 図
第 2 図FIG. 1 is a basic configuration block diagram of the present invention, FIG. 2 is a circuit diagram of an embodiment of a power recovery restart guarantee circuit according to the present invention, and FIG. 3 is a time chart of an embodiment of the present invention. In the figure, 10 is a power supply control circuit, and 11 is a power failure detection section. 12 is a power on/off section, 13 is an initial clear section,
14 is a power recovery restart guarantee circuit, 15 is a timer counter,
Reference numeral 16 represents a battery server unit, 17 represents a power supply unit, and 18 represents a processor. Patent Applicant Panafacom Co., Ltd. Representative Patent Attorney Hiroshi Mori 1) (and 1 other person) Honshaved eyes ← To a certain angler 072B IK 1 Figure 2
Claims (1)
御方式であって、 交流入力電源についての停電を検出する停電検出部(1
1)と、 上記プロセッサ(18)を含む装置に対する電源のオン
/オフを制御する電源オン/オフ部(12)と、上記停
電検出部(11)の出力信号に基づき、停電が検出され
てから、所定の時間が経過するまで、復電時における上
記電源オン/オフ部(12)による電源投入信号の出力
を抑止する信号を出力する復電再起動保障回路(14)
と、 該復電再起動保障回路(14)を動作させる直流電源を
、上記交流入力電源とは独立にサポートする電池サポー
ト部(16)とを備えたことを特徴とする停電検出・復
電制御方式。[Claims] A power supply control method for supplying power to a device including a processor (18), comprising a power failure detection unit (18) that detects a power failure regarding an AC input power source.
1), a power on/off unit (12) that controls power on/off of the device including the processor (18), and a power outage detection unit (11) based on output signals from the power outage detection unit (11). , a power recovery restart guarantee circuit (14) that outputs a signal that suppresses output of a power-on signal by the power on/off unit (12) at the time of power recovery until a predetermined time has elapsed;
and a battery support unit (16) that supports a DC power source that operates the power recovery restart guarantee circuit (14) independently of the AC input power source. method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60167035A JPS6226522A (en) | 1985-07-29 | 1985-07-29 | Service interruption detection and power recovery control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60167035A JPS6226522A (en) | 1985-07-29 | 1985-07-29 | Service interruption detection and power recovery control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6226522A true JPS6226522A (en) | 1987-02-04 |
Family
ID=15842178
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60167035A Pending JPS6226522A (en) | 1985-07-29 | 1985-07-29 | Service interruption detection and power recovery control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6226522A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04271421A (en) * | 1990-07-16 | 1992-09-28 | Internatl Business Mach Corp <Ibm> | Keyboard lock-out preventing circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5323230A (en) * | 1976-08-14 | 1978-03-03 | Fujitsu Ltd | Power closing control system |
JPS5972928A (en) * | 1982-10-20 | 1984-04-25 | 沖電気工業株式会社 | Power source circuit |
-
1985
- 1985-07-29 JP JP60167035A patent/JPS6226522A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5323230A (en) * | 1976-08-14 | 1978-03-03 | Fujitsu Ltd | Power closing control system |
JPS5972928A (en) * | 1982-10-20 | 1984-04-25 | 沖電気工業株式会社 | Power source circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04271421A (en) * | 1990-07-16 | 1992-09-28 | Internatl Business Mach Corp <Ibm> | Keyboard lock-out preventing circuit |
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