JPS62262166A - Information processor - Google Patents

Abstract

PURPOSE:To reduce a software overhead by totaling an amount corresponding to the transmission rate of an input/output device which is being used, comparing it with a prescribed amount, and controlling the use request of a bus. CONSTITUTION:The control part of each input/output device generates automatically a signal for displaying a fact that a data is being transferred. A voltage level corresponding to each transmission rate based on a data transfer request signal REQij (i, j = 1, 2...) determined from the bus use rate of each input/ output device is summed up to the voltage level VX of an input A through a diode D1 and resistances R1, R2. The level VX is compared with the B input voltage V11 of a prescribed value for showing an allowable bus band width by a comparing circuit IC1, and in case of VX>V11, it is informed to a software by an interruption, the subsequent transfer request is set to a waiting state, and when it is known that the prescribed value is V12>VX by a comparing circuit IC2, an instruction is executed to the software, and the waiting state is released.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to means for managing the amount of data transferred between components of an information processing device.

〔overview〕

In the system bus management means of an information processing device, the present invention monitors the bus trust status of each input/output device connected to the bus and determines acceptance of a bus usage request from each input/output device. This makes it possible to make maximum use of the bus bandwidth of the system bus.

[Conventional technology]

In the information processing device, as shown in FIG. 4, a main processor (hereinafter referred to as CPU) 1, a main memory 2, and various input/output control units 3 to 9 are arranged on a system bus 10.
In many cases, it is controlled under the control of the CPUI. In the example of FIG. 4, the input/output control units include a magnetic disk control unit 7, a floppy disk control unit 28, a local area network control unit 9, a GPIB interface control unit 3, and a general-purpose high-speed input/output unit.

Kai9-7z-xl1m! richiko, high school 1110. :say. )4, and general-purpose low-speed input/output interface control unit (hereinafter referred to as low-speed I/O interface) such as R3-232G interface.
It's called 10. ) 5 and 6 etc. are connected. Control units that require high-speed data transfer generally use a direct memory access transfer method, while those that require relatively low-speed data transfer generally use program transfer using the CPUI. On the other hand, the data transfer capacity of the system bus 10 is finite, and its value depends on the access time of the main memory 2, the speed of the direct memory access circuit (hereinafter referred to as DMA), the width of the data bus, and the bus contention management method. Determined by etc. This system bus 1
The bus bandwidth, which is the data transfer capacity of 0, is BBW,
In addition, the specific bus bandwidth is set to BWI or B depending on the speed of each input/output device of each element on the system bus 10.
W, then there is excess transfer capacity on the system bus, and system bus 1
There is no problem if all the control units on the 0 operate simultaneously, but there are many high-speed control units on the system bus 10, which exceeds the transfer capacity of the system bus 10, and the CP
A fatal problem occurs in which the U l processing is not completed in time or data underruns and overruns occur.

In the conventional device, ■ the type and number of control units that can be connected simultaneously on the system bus 10 are limited; ■ the operating system limits the number of tasks that simultaneously activate each input/output control unit using software; ■ the system bus This problem was avoided by increasing the transfer capacity (increasing the memory speed, widening the data width, etc.).

[Problem that the invention seeks to solve]

However, method (2) above is undesirable as it limits system expandability, method (2) is not economical as it increases hardware costs, and method (2) is not effective in single-user systems. However, multi-user and multi-process systems have drawbacks such as complicated operation system management and reduced throughput due to task weights.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus having a bus bandwidth management means that can perform efficient bus management with less software overhead.

[Means for solving problems]

The present invention provides a system bus having a unique bus bandwidth, an input/output device connected to the system bus and having a unique transmission speed, and a program that manages reception of requests for use of the system bus by the input/output device. In the information processing apparatus, the input/output device includes means for generating a usage signal indicating that the system bus is in use, and the input/output device generates a usage signal corresponding to the transmission speed of the input/output device that is generating the usage signal. a calculation means for generating a value of 1 and summing the values; a comparison means for comparing the output value of the calculation means with a second value corresponding to the bus bandwidth; The present invention is characterized by comprising a control means for operating the program control means based on the program control means.

[Effect]

Each input/output control section automatically generates a signal indicating that data is being transferred. Based on the transmission speed of the input/output control unit that generated this signal, the hardware constantly calculates and monitors the overall usage rate of the system bus bandwidth. If the system bus is used in excess of the specified bus bandwidth during this monitoring, the software is notified by an interrupt and is placed in a wait state for subsequent diode transfer requests from various tasks.

If the bus bandwidth continues to be less than the specified bus bandwidth, the software is notified by interrupting again, and the data transfer request in the waiting state is activated.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit connection diagram showing the configuration of a bus bandwidth management circuit according to an embodiment of the present invention.Table 0 is based on the bus usage rate of the system bus of each input/output control unit of the state processing device shown in FIG. This shows the determined data transfer request signal REQti, which corresponds to the data transfer request signal RBQ=j shown in FIG. Here, the bus usage rate is the ratio between the transfer speed in the table and the bus band congestion of 1500 kw/s.

(Hereinafter referred to as the margin of this page) Next, the operation of this embodiment circuit will be explained.

Symbols IC and IC are level determination circuits using differential amplifiers. Level judgment circuit IC+ and IC.

The relationship between the input impedance ZI on the side and the impedance Z RE@ on the bus request level input side is 21>>2
□0, and the diode is 0. If we ignore the on-voltage of
V, <V□. In the range of i, the voltage level of input A is v,l
is ・−・−−−−−−(1), where, if Rt = 2Rz, +□(
v□. 4. +v□. 4ri+□ (V□.S++V□., ri+(V It@!I + V @t@R1)+
(Vs+to+t + Vi+to+z)・・−
・−・−(2) holds true. Therefore, data transfer request signal REQ+
The bus bandwidth of each level of j is REQs #3
3%, R1! Qa) 25%, REQs I=120%,
REQg” 12.5%, RH (1, #7%.

The B input voltage V + + of the level determination circuit IC is preset to a threshold value indicating the permissible bus bandwidth of this system, as shown in FIG.

>V++, the level determination circuit IC is turned on, a bus bandwidth overflow occurs, and the generation of this overflow signal (OVF) is used as a trigger to interrupt and notify the software. On the other hand, the B input voltage V+Z of the level judgment circuit IC2 is set in advance to a value below the allowable bus bandwidth, and it is intended to have a hysteresis characteristic as V, , < ■ I2, so V, < Vl □. In this case, the level determination circuit IC.

turns on and a bus bandwidth tender low occurs.
Similarly, the occurrence of this underflow signal (ODA) is used as a trigger to interrupt and notify the software.

Data transfer request signals from each input/output control section are generated by the circuit shown in FIG. The DMA data transfer request signal OR port is a signal generated every transfer cycle. This DMA
The data transfer request signal OR port sets the cent reset type flip-flop Fl, and the data transfer request signal R
EQ and J occur.

Resetting of data transfer request signal R8,j is performed by terminal count signal TC generated at the end of DMA transfer, error occurrence ERR during data transfer, and initialization signal R3T. This data transfer request signal REQ,j
is connected to a predetermined data transfer request level of the bus bandwidth management circuit according to the bus usage rate of each input/output control unit as shown in the table.

〔Effect of the invention〕

As explained above, the present invention prevents the occurrence of data undruns or overruns, and allows fine control of bus usage rate, allowing efficient data transfer by making maximum use of the allowed bus bandwidth with less hardware. There are effects that can be achieved.

[Brief explanation of drawings]

FIG. 1 is a circuit connection diagram showing the configuration of a bus bandwidth management circuit included in an embodiment of the present invention. FIG. 2 is an explanatory diagram showing the operation of the level determination circuit of FIG. 1. FIG. 3 is a circuit connection diagram showing the configuration of a data transfer request signal generating means included in the input/output control section. FIG. 4 is a block diagram showing the configuration of the information processing device. 1... Main processor (CPU), 2... Main memory, 3... GPIB interface control unit (GPIB
C), 4... General-purpose high-speed input/output interface control unit (high-speed l10), 5.6... General-purpose low-speed input/output interface control unit (low-speed l10), ? ... Magnetic disk control unit (DISKC), 8... Floppy disk control unit (FDDC), 9... Local area network control unit (LANC), 10... System bus, 13 to 16... Input Output device (Ilo), 17...
・Magnetic disk, 18...Floppy disk, 19
... Local area network (LAN), 23.
24.27-29... Direct memory access circuit (DMA), IC,, IC,... Level judgment circuit, Fl... Set/reset type flip-flop.

Claims (1)

[Claims] (1) A system bus having a unique bus bandwidth, an input/output device connected to this system bus and having a unique transmission speed, and a program control that manages reception of requests for use of the system bus by this input/output device. In the information processing apparatus, the input/output device includes means for generating a usage signal indicating that the system bus is in use, and a first signal corresponding to the transmission speed of the input/output device generating the usage signal. a calculation means for generating a value and summing the values; a comparison means for comparing the output value of the calculation means with a second value corresponding to the bus bandwidth; and the above-mentioned program based on the output of the comparison means. An information processing device characterized by comprising a control means for operating a control means.