JPS62261203A - Poly-phase signal generator - Google Patents

Abstract

PURPOSE:To simplify the waveform storage to a ROM by providing the RIM whose address is designated by an output signal of the 1st counter and plural packet pre-gate device connected to plural output terminals of the 2nd counter through a pulse input terminal and connected in series with an output stage of the ROM sequentially. CONSTITUTION:An address of the ROM 5 is designated sequentially by a pulse signal from the 1st counter 3 and the storage content of the ROM 5 is outputted to a DAC 8 and the 1st BBD 6. A signal from the ROM 5 is retarded respectively by the 1st BBD 6 and the 2nd BBD 7 connected in series with the output stage of the ROM 5. The timing is taken by inputting a pulse outputted from output terminals A0, A1 of the 2nd counter 4 to pulse input terminals P0, P1 of the 1st BBD 6 and the 2nd BBD 7 and they are retarded by 120 deg. each. Thus, the output from the DACs 8-10 receiving the signal is a sinusoidal wave.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a multiphase signal generation circuit used in inverter devices and the like.

Conventional technology In recent years, inverter devices have been widely used for variable speed motors, but in the market there are many dissatisfied with the size and price of the devices.
There was a strong desire for devices to be smaller and lower in price.

Hereinafter, a conventional multiphase signal generation circuit will be explained with reference to the drawings.

Fig. 3 is a block diagram of a conventional multiphase signal generation circuit, Fig. 4 is a basic circuit diagram of an inverter device, Fig. 5 is a signal waveform diagram showing the principle of PWM signal generation, Fig. 6 is a PWM signal waveform diagram,
Figure 7 is an output waveform diagram of the multiphase signal generation circuit, and Figure 8 is the same R
FIG. 9 is a timing chart showing the contents of data written to the OMK.

In FIG. 4, 19 is a DC power supply, and 20 to 26 are power transistors connected to the DC power supply 19.

From this configuration, the PWM signal shown in FIG. 6, which is a comparative output of the sine wave a shown in FIG. However,
In a three-phase inverter device as shown in FIG. 4, it is necessary to apply a PWM signal to the base terminals of the power transistors 20 to 26, in which a sine wave whose phase is shifted by 120 degrees from each phase is compared with a triangular wave. A circuit shown in FIG. 3 has been used to generate such three-phase sine waves with a phase shift of 120 degrees. In Figure 3, 1 is a frequency setting section that sets the frequency, 2 is an oscillation section that oscillates pulses at a frequency determined by the signal from frequency setting section 1, and 3 is a frequency division of the pulse signal from oscillation section 2 to a preset value. 11 is a second counter that sequentially outputs one pulse from the three output stages each time it receives a pulse signal from the oscillation section, and 12 is an address that is sequentially specified by the output signal of the first counter 3. 16 to 1 are connected in parallel to the output stage of the ROM, and the latch timing terminals 13 to 16 are connected to the second
Output terminal Ao of counter 11.

AI and A2 are connected to the 9 latches, 8 to 1° are the D/A converters (hereinafter DAC) connected to the latches 16 to 18.
). Next, the operation of the above configuration will be explained. A frequency setting section 1 sets a frequency, and an oscillation section 2 that receives a signal from the frequency setting section 1 oscillates a pulse according to the signal from the frequency setting section 1. The first counter 3 divides this signal. Similarly, the second counter 11 receives this pulse signal and sequentially outputs one pulse from the three output terminals Ao, A1 and A2 each time a pulse signal is input, as shown in FIG. The address of the ROM 12 is specified by the signal frequency-divided by the first counter 3, but the RO
As shown in Figure 8, which shows the contents of the data written in M12, if the values of the three-phase waveform signals at the same time tH are successively input in order, and the value of tN+1 is similarly input in sequence, oscillation will occur. By the pulse signal of section 2, the data of U phase, ■ phase, and W phase are transmitted to the U phase,
The signals are sequentially output to the phase latches 16 to 18. Here, the output terminals Ao, A1 . When the output from A2 is applied, the output of ROM12 is changed to DACs~10
Output to. After that, the latch timing terminal 13~
15 to the output terminals Ao, A1 . Latch 16 the output of ROM12 until a pulse is applied from A2.
~18 is retained. By inputting the outputs of the latches 16 to 18 to the DACs to 1o, respectively, the outputs were sine waves having a phase shift of 120 degrees as shown in FIG.

Problems to be Solved by the Invention In such conventional circuits, in order to create a multiphase signal generation circuit, multiple waveforms must be stored in the ROM. A latch was also required for each phase, making it difficult to reduce costs.

It is an object of the present invention to provide a multiphase signal generation circuit that can simplify memory storage, reduce the capacity of a ROM, and reduce the cost of the circuit.

Means for Solving the Problems In order to solve the above problems, the present invention provides a frequency setting section that emits a frequency setting signal, and a frequency setting section connected to the frequency setting section,
and an oscillation unit that oscillates pulses at a frequency determined by a frequency setting signal from the frequency setting unit; and an oscillation unit that is connected to the oscillation unit and divides the frequency of the pulse signal from the oscillation unit, and is preset when a preset value is reached. a first counter; a second counter that is connected to the oscillation section and generates one pulse sequentially from a plurality of output terminals each time it receives a pulse signal from the oscillation section; and a second counter that is connected to the first counter; It consists of a ROM whose address is designated by the output signal of the first counter, and a plurality of BBDs that are sequentially connected in series to the output stage of the ROM and whose pulse input terminals are connected to the plurality of output terminals of the second counter. It is something.

Function: With this configuration, the oscillator oscillates a pulse at a frequency determined by the signal from the frequency setting section, divides this pulse signal by the first counter, and sequentially specifies the address of the ROM.
Outputs the waveform stored in ROM to BBD. Further, in response to a pulse signal from the oscillator, a second counter sequentially generates a pulse signal, and a multiphase signal is generated by sequentially delaying the output from the ROM using a plurality of BBDs.

EXAMPLE An example of the present invention will be described below with reference to FIGS. 1 and 2. Components that are the same as those in FIG. 4 of the conventional example are designated by the same numbers and explanations thereof are omitted.

In FIG. 1, reference numeral 1 denotes a frequency setting section that generates a frequency setting signal, and an oscillation section 2 that oscillates a pulse at a frequency determined by the signal from the frequency setting section 1.
The frequency is divided by the counter 3, and when a predetermined value (for example, 1024) is counted, it is preset. Next, each time a pulse signal is received from the oscillator 2, one pulse is sequentially outputted from the two output terminals Ao and A1 of the second counter 4, as shown in FIG. The addresses of ROMrs are sequentially specified by the pulse signal from the first counter 3, and the ROM
5 is output to the DAC 8 and the first BBD 6. R
Delay the signal from OM5 and send the signal to the first BBDes
The signal is output from the output stage BO to the DAC 9 and the second BBD7, and the further delayed signal is output from the output terminal B1 of the second BBD7 to the D
Output to AClo. The signal from ROM5 is
The first BBDe and the second B are connected in series to the output stage of 5.
Each is delayed in BD7. This timing is the second
The pulses output from the output terminals AO and AI of the counter 4 are transferred to the pulse input terminals PO and P1 of the first BBD6 and the second BBD7.
, and are delayed by 120 degrees each. Therefore, DACa~10 to which that signal is input
A sine wave as shown in FIG. 8 is obtained from the output.

As described above, according to this embodiment, by using the BBD, waveform storage in the ROM becomes easy, and the ROM
The memory capacity of the circuit can be reduced, and the cost of the circuit can be reduced.

In the embodiment, the output from the ROM and the output from two BBDs connected in series to the output stage of the ROM are each 1.
The phase was shifted by 20 degrees, but the number of BBDs connected in series with the ROM was increased or decreased, and the output terminal of the second counter that inputs pulses to the pulse input terminal of the BBD was changed to BB.
By increasing or decreasing the number of D, different multiphase signals can be generated without causing any difference in their effects.

Effects of the Invention As described above, according to the present invention, with the above configuration, a multiphase signal can be freely generated from a single waveform stored in the ROM, and waveform storage in the ROM is simplified. Man-hours can be reduced. In addition, since the storage capacity of the ROM is small, costs can be reduced and a great practical effect can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a multi-phase signal generation circuit according to an embodiment of the present invention, Fig. 2 is a timing chart of the same, Fig. 3 is a block diagram of a conventional multi-phase signal generation circuit, and Fig. 4 is a block diagram of an inverter device. Basic circuit diagram, Fig. 6 is a signal waveform diagram showing the principle of PWM signal generation, Fig. 6 is a PWM signal waveform diagram, Fig. 7 is an output waveform diagram of the multiphase signal generation circuit, and Fig. 8 is a signal waveform diagram written in the same ROM. FIG. 9 is a timing chart showing the contents of the data. 1... Frequency setting section, 2... Oscillation section,
3...First counter, 4...Second counter, 6...ROM. 6...1st BBD? ...Second B
B D0 Agent's name Patent attorney Toshio Nakao and 1 other person Figure 1 Figure 2 vl Yo latitude → Figure 3 Figure 4 H two PWM bu τ2i Figure 7

Claims (1)

[Scope of Claims] A frequency setting section that emits a frequency setting signal; an oscillation section that is connected to the frequency setting section and that oscillates pulses at a frequency determined by the frequency setting signal from the frequency setting section;
a first counter that is connected to the oscillation section and divides the pulse signal from the oscillation section and is preset when a preset value is reached; and a first counter that is connected to the oscillation section and receives the pulse signal from the oscillation section. a second counter that sequentially generates one pulse from a plurality of output terminals each time a pulse is received;
A ROM connected to a counter and whose address is specified by the output signal of the first counter, and a second ROM connected in series to the output stage of the ROM and having a pulse input terminal.
A polyphase signal generation circuit consisting of multiple bucket brigade devices connected to multiple output ends of a counter.