JPS6225453A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To suppress a software error due to alpha-rays and to realize high integration by forming a well for forming a transistor to form an FF shallower than a well for forming a transfer gate and a peripheral circuit or in high impurity density. CONSTITUTION:A p-well 11 of an FF of a memory cell, a transfer gate,and a p-well 12 of a peripheral circuit are formed in an n-type Si substrate 1. The well 11 is formed in higher density and/or shallower than the well 12. N-channel transistors are formed in the wells 11, 12. When the well 11 is shallow, the alpha-ray passing distance in the well is shortened to suppress a software error due to the alpha-ray of the memory cell. The area of the memory cell can be reduced to raise the integration. If the well 12 is deep, it can suppress a latchup phenomenon due to a parasitic thyristor of P-N-P-N structure formed in the substrate. If the density of the well 11 is high, information is hardly inverted. When the well 12 is further low in density, its turning OFF operation is accelerated to accelerate the device.

Description

[Detailed Description of the Invention] [Summary] Wells forming flip-flop portions of memory cells are formed with high concentration and/or shallowly, and transfer gates,
By forming the well forming the peripheral circuit part at a low concentration and/or deeply, it is possible to suppress soft errors caused by alpha rays in the memory cell part and increase the degree of integration, and to suppress rough growth and increase the speed of the peripheral circuit part.

[Industrial application field]

The present invention provides at least a portion of a memory cell portion and a peripheral circuit portion formed within a semiconductor substrate and inverted with respect to the semiconductor substrate.
The present invention relates to a structure of a semiconductor memory device formed in a well having a mold.

The storage capacity of large-scale integrated circuit (LSI) memories is increasing year by year, and circuit patterns are becoming increasingly finer as the degree of integration increases.

Additionally, the scale of peripheral circuits has increased, and in order to reduce power consumption, they are often made of CMOS.

Since a CMOS needs to be composed of a p-channel transistor and an n-channel transistor, a well of a conductivity type opposite to that of the substrate is formed in the substrate, and transistors of opposite conductivity types are formed in the substrate and well, respectively.

In the above-mentioned LSI memory in which the peripheral circuit is composed of CMOS, in order to simplify the process, if the well of the peripheral circuit part is formed in the same process as the optimized well of the memory cell part, the peripheral circuit part will be formed in the same process as the optimized well of the memory cell part. Countermeasures are required to reduce the operating speed and cause failures due to the latch amplifier phenomenon even though the thyristor action is insufficient.

[Conventional technology]

FIG. 2 is a schematic cross-sectional view of a well portion of a conventional semiconductor memory device in which at least a portion of a memory cell portion and a peripheral circuit portion are formed within a well.

The left side of the figure represents the peripheral circuit section, and the right side represents the memory cell section.

In the figure, reference numeral 1 denotes a semiconductor substrate, which is an n-type silicon (Si) substrate, on which a p-type well (p-well) 2, which is shared by the peripheral circuit section and the memory cell section, is formed.

In this well 2, transistors of one conductivity type (n channel) for the peripheral circuit section and the memory cell section are formed.

3.4 is an n° type source and drain region, 5 is a gate insulating layer, and 6 is a gate electrode, which constitute a transistor in the memory cell portion.

7.8 is an n-type source and drain region, 9 is a gate insulating layer, and 10 is a gate electrode, which constitute a transistor in the peripheral circuit section.

The figure shows an example in which both transistors are formed in the same well, but the peripheral circuitry operates vigorously and generates various noises that affect the memory cell area, so the well is separated as shown by the dotted line in the figure. Often separated.

Even in this case, the separated individual wells were formed in the same process to simplify the process.

[Problem that the invention seeks to solve]

In an LSI memory in which at least part of the memory cell section and the peripheral circuit section are formed in a well, the transfer gate and the well of the peripheral circuit section are formed in the same process as the well of the flip-flop section of the memory cell, which is optimized. This reduces the operating speed of the transfer gate and the peripheral circuitry, and causes a latch-up phenomenon that causes electrical conduction between the well and the substrate.

Conversely, the well of the flip-flop part of the memory cell is
If the wells of the optimized transfer gate and peripheral circuit section are formed in the same process, soft errors caused by alpha rays in the memory cell section will become a problem, and will also impede high integration.

[Means for solving problems]

A solution to the above problem is to include a memory cell having a pair of transistors that are cross-connected to form a flip-flop, a pair of transfer gates connected to the flip-flop, and a peripheral circuit, and to form the flip-flop. This is achieved by the semiconductor memory device according to the present invention, in which the well forming the pair of transistors is shallower than the well forming the transfer gate and the peripheral circuit, or is a well having a higher impurity concentration.

[Effect]

Regarding the optimization of the flip 707.1 portion of the memory cell, the transfer gate, and the well of the peripheral circuit portion, the concentration and depth will be considered.

(1) Depth 1-1) The flip-flop portion of the memory cell should be shallow.

When the well is shallow, the distance through which α rays pass through the well becomes smaller, and therefore the number of carriers ionized by the passage of α rays decreases, and errors in information storage caused by such carriers, so-called soft errors, are suppressed.

If the well is shallow, transistors of both conductivity types can be formed close to each other when the memory cell portion is CMOS, so the area of the memory cell can be reduced and the degree of integration of the LSI can be increased.

(1-2)) Transfer gates and peripheral circuits should be deep.

When the well is deep, it is possible to suppress a conduction phenomenon between the well and the substrate due to a pnpn parasitic thyristor formed in the substrate by transistors of both conductivity types, that is, a so-called launch amplifier phenomenon. This is because if the well is deep, the thickness of each layer of the pnpn structure can be increased, thereby preventing conduction of parasitic silicon risks.

The transfer gate part is not a problem even if it is affected by alpha rays, and since it is connected to bit green, which has potential fluctuations, launch-up is likely to occur, so the well should be deep.

(2) Concentration (2-1) The flip-flop portion of the memory cell is made high.

If the concentration is high, parasitic capacitance will be attached to the drains of the cross-connected transistors, making it difficult for information to be inverted.

(2-2)) Lower the transfer gate and peripheral circuit section.

The transfer gate part is turned on when the concentration is lower.
The turn-off operation is performed quickly, which is advantageous for increasing the speed of the device.

If the concentration in the peripheral circuit portion is also low, the junction capacitance of the parasitic capacitance that acts as a load on the transistor is reduced, so that the operating speed of the transistor can be improved.

For the above reasons, optimization is possible by forming the flip-flop section and transfer gate of the memory cell, and the well of the peripheral circuit section through different processes.

〔Example〕

FIG. 1 is a schematic cross-sectional view of a well portion of a semiconductor memory device according to the present invention, in which at least a portion of a memory cell portion and a peripheral circuit portion are formed within the well.

The left side of the figure represents a transfer gate and a peripheral circuit section, and the right side represents a flip-flop section of a memory cell.

In the figure, reference numeral 1 denotes a semiconductor substrate, which uses an n-type Si substrate, and includes a p-well 11 and a transfer gate in the flip-flop section of the memory cell, and a p-well 12 in the peripheral circuit section.
is formed.

The well 11 in the flip-flop section of the memory cell is made higher in concentration and/or shallower than the well 12 in the transfer gate and peripheral circuit section.

A flip-flop portion of the memory cell is formed in the well 11, a transfer gate is formed in the well 12, and an n-channel transistor in the peripheral circuit portion is formed.

3.4 is an n° type source and drain region, 5 is a gate insulating layer, and 6 is a gate electrode, which constitute a transistor in the flip-flop section of the memory cell.

7.8 is an n-type source and drain region, 9 is a gate insulating layer, and 10 is a gate electrode, which constitute a transfer gate and a transistor in the peripheral circuit section.

Next, an outline of a process example for creating a difference in concentration and depth in well formation will be explained.

Regarding the concentration, when implanting impurity ions of the opposite conductivity type to the substrate, it is necessary to
The ion implantation is performed twice for the peripheral circuit portion, with a larger dose for the former and a smaller dose for the latter.

Alternatively, the first ion implantation is performed simultaneously on the flip-flop section, transfer gate, and peripheral circuit section of the memory cell, and the second ion implantation is performed only on the flip-flop section of the memory cell by masking the transfer gate and peripheral circuit section. to be done.

In the above manner, the concentration of the well in the flip-flop portion of the memory cell is increased.

Regarding the depth, the first ion implantation is performed in the transfer gate and peripheral circuit area, heated and annealed, and then the second ion implantation is performed in the flip-flop area of the memory cell and heated again to improve the transfer gate depth. , and deepen the wells in the peripheral circuit area.

In the above explanation, a case has been described in which a p-type well is formed on an n-type Si substrate, but the present invention can also be applied to a case where an n-type well is formed on a p-type Si substrate. I can do it.

The same applies to the case where both an n-type well and a p-type well are formed on an n-type or p-type substrate.

FIG. 3 is a block diagram showing the configuration of a static random access memory (SRAM) to which the present invention is applied.

In the figure, 31 is a cell array, and 32 to 41 are peripheral circuits.

Addresses AO+AI+ .

The addresses Aj+ AM+ . . . +An are decoded by the column decoder 33 through the respective address buffers 35, and enter the bit line (BL) of the cell array 31 through the input/output (Ilo) transfer gate 36.

Data input D1.4 is buffer 40, write amplifier 39
, Ilo) The data enters the BL of the cell array 31 through the transfer gate 36 to perform writing.

The write amplifier 39 is controlled by a write control circuit 41 based on a signal from a write enable terminal.

Data output. LIT is from BL of cell array 31,
The signal is outputted via the I10 transfer gate 36, sense amplifier 37, and buffer 38, and is subsequently output.

FIG. 4 is a circuit diagram of a two-resistor, four-transistor SRAM cell and a row decoder driver output stage.

In the figure, VCC is a power supply voltage and VSS is a ground voltage. The memory cell is a cross-connected transistor T2.
, load resistors R1 and R2, and transfer gate transistors T3 and T4.

The row decoder driver output stage includes transistors T6 and T6.
This is a CMOS inverter consisting of:

FIGS. 5(1) to 5(3) are a plan view and a cross-sectional view of the circuit of FIG. 4 to which the present invention is applied as an example of a memory cell and a peripheral circuit.

FIG. 5 (11 is a plan view, (2) is an AA sectional view, and (3) is a BB sectional view.

According to the invention, p-well 1 of the flip-flop part of the cell
1 is formed shallower (and/or with higher concentration) than the transfer gate and the p-well 12 in the peripheral circuit section.

In the figure, 51 is the n layer of the source/drain region of the n-channel transistor, 52 is the p+ layer of the source/drain region of the p-channel transistor, and 53 is the gate electrode/wiring material made of polycrystalline silicon (JSi). The layer 54 is an interlayer insulating layer made of phosphosilicate glass (PSG), 55 is an aluminum (^l) wiring layer, 56 is a cover layer and is a PSG layer, and 57 is a contact hole opened in the PSG layer 54.

T, -T, correspond to the transistor in Fig. 4, and to avoid complexity, the display of the load resistances R1s and Rz is omitted, and some A1 cotton layers such as BL and Vss that extend in a straight line are also omitted. It was displayed in this form.

〔Effect of the invention〕

As described in detail above, according to the present invention, in an LSI memory in which at least a part of a memory cell part and a peripheral circuit part are formed in a well, a flip-flop part and a transfer gate part of a memory cell, and a part of a peripheral circuit part are formed in a well. By forming the wells in separate steps, it is possible to suppress soft errors caused by alpha rays in the memory cell area and achieve higher integration, and to suppress the rough drop phenomenon and increase speed in the transfer gate area and peripheral circuit area.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a well section of a semiconductor memory device in which at least a part of a memory cell section and a peripheral circuit section are formed in a well according to the present invention, and FIG. 2 is a schematic cross-sectional view of a memory cell section and a peripheral circuit section according to a conventional example. FIG. 3 is a block diagram showing the configuration of an SRAM to which the present invention is applied; FIG. Circuit diagram of row decoder driver output stage, Figure 5 (11 to (3)
) are a plan view and a sectional view in which the present invention is applied to the circuit of FIG. 4 as an example of a memory cell and peripheral circuit. In the figure, 1 is a semiconductor substrate, an n-type Si substrate, 11 is a p-well in the memory cell section, 12 is a p-well in the peripheral circuit section, 3.4.7.8 is an n+ type source and drain region, 5 .9 is a gate insulating layer, 6.10 is a gate electrode 31 is a cell array, 32 is a row decoder, 33 is a column decoder, 34 is an address buffer, 35 is an address eight sofa, 36 is an I10 transfer gate, 37 is a sense amplifier, 38 39 is a data output cover sofa, 39 is a write amplifier, 40 is a data input cover sofa, 51 is an n'' layer of the source/drain region of an n-channel transistor, 52 is a p'' layer of the source/drain region of a p-channel transistor, 53 is a gate electrode・The wiring material is the Bo'JSi layer, 54 is the insulating layer between the eyebrows and the PSG layer, 55 is the AI wiring layer, 56 is the cover single layer and is the PSC layer, 57 is the contact hole No. Figure 4

Claims (1)

[Scope of Claims] A memory cell having a pair of transistors that are cross-connected to form a flip-flop, a pair of transfer gates connected to the flip-flop, and a peripheral circuit, and the flip-flop is formed. A semiconductor memory device characterized in that a well forming a pair of transistors is a well shallower than a well forming the transfer gate and the peripheral circuit, or a well having a higher impurity concentration.