JPS62254537A - Multimedium synchronization detecting circuit for television satellite broadcast receiver - Google Patents

Abstract

PURPOSE:To surely identify plural media sent from a broadcast satellite with a simple circuit constitution by providing an information bit extraction circuit, a demultiplexer and an error detection circuit. CONSTITUTION:The titled circuit is provided with an information bit extraction circuit 14 extracting an information bit from an independent data frame received by the BS tuner of a television satellite broadcast receiver 1, a demultiplexer 16 outputting a signal selecting a decoder 18 provided corresponding to each medium based on the information bit extracted by the extraction circuit 14, and an error detection circuit 20 detecting the error of a frame synchronizing part included in the independent data frame and starting the demultiplexer 16 when no error exists. Further, the error detection circuit 20 includes a latch circuit 22 and a comparator 24. Thus, the kind of media of the transmission data in the television satellite broadcast is recognized surely by the simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a multimedia synchronization detection circuit for a television satellite broadcasting receiver. (1
B.5) This invention relates to a multimedia synchronization detection circuit that uses a cyclic code such as an error correction code.

(Prior art) The standard method for Japanese television satellite broadcasting was established in 1981.
The Radio Technology Council issued a report in February, and data services are now being provided using broadcasting satellites.

Regarding the transmission method of PCM audio signals in this data service, there are A mode and B mode, and in both of these modes, the data parts and services of various broadcast media such as future teletext and facsimile broadcasts are taken into account. In order to enable these data transmissions, independent data frames are secured for transmitting data of various broadcast media independently of PCM audio signals.

That is, as shown in FIG. 3, the independent data frame ID is coded according to each broadcast media, with respect to the data part ID that includes information from various broadcast media such as text broadcasting and facsimile broadcasting. It is configured by adding a frame synchronization section ID2 containing information bits B and an error correction section ID3 for error correction of the data section [D].

This independent data frame ID is then multiplexed with the PCM audio signal and broadcast. These contents can be found in ``Broadcasting New Media and Reception Technology'' published by Denshi Gijutsu Publishing Co., Ltd. (published November 6, 1980) and NHK Technical Research 1986. “Development of television satellite broadcasting standard system” (No. 37)
Volume 1, Volume 167, page 14 onwards), etc.).

The data format of the data section ID in this independent data frame ID differs depending on the content of the media, but the data format of the frame synchronization section IDt is common to all media, and the BCII (16, 5) error A cyclic code such as a correction code is used. Here, 16 in parentheses above is the total code length of the frame synchronization part IDt,
5 is the code length of information bit B.

Incidentally, various methods of decoding +3 CH (16,5) codes have been proposed in the past. For example, when the number of error corrections is small, a method of generating a syndrome and using a ROM table, a method of calculating the coefficients of the error locator polynomial as a function of the syndrome, and a method of calculating the coefficients of the error locator polynomial as a function of the syndrome, and a method of using Pe
terson algorithm, Be r 1
The e k a m p -M asse Y algorithm, which is based on the Euclid algorithm, is generally well known. Each of these methods aims at error correction of the B CH (16,5) code, and the circuit configuration for implementing them is considerably complicated. Now, the 16-bit length frame synchronization part ID, h(1
When a bit is erroneous, the error probability is independent data frame ID
If the data section ID and the total ID of the error correction section, +ID, are 272 bits long, then 272/16=17, and there is a possibility of a 17-bit error. Therefore, when correcting l-bit errors in the frame synchronization section, a 17-bit correction function is required as an error correction circuit for the data section ID, which is not practical.

By the way, if the purpose is only to identify multiple media transmitted from broadcasting satellites, B CH (
16,5) There is no need to decode the code and perform error correction,
It is only necessary to detect information bits coded according to each broadcast media. Therefore, B CH(
+6.5) The circuit configuration for media synchronization detection should be simpler than the code error correction circuit.

(Object of the Invention) The present invention has been made in view of the above j;*, and an object of the present invention is to enable reliable identification of a plurality of media transmitted from a broadcasting satellite with a simple circuit configuration.

(Structure of the Invention) In order to achieve the above-mentioned object, the multimedia synchronization detection circuit of the television satellite broadcasting receiver of the present invention detects information bits from independent data frames received by the BS tuner of the television satellite broadcasting receiver. a demultiplexer that outputs a signal for selecting a decoder provided corresponding to each media based on the information bits extracted by the information bit extraction circuit; and an error detection circuit that detects an error in a frame synchronization section that is transmitted and activates the demultiplexer when there is no error.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of a television satellite broadcast receiver according to an embodiment of the present invention. In the same figure, code 1
indicates a television satellite receiver, 2 indicates a 12GHz
4 is a BS converter that converts and outputs the broadcast radio waves received by the BS antenna 2 to the first intermediate frequency band of the IGHz band; 6 is a BS antenna for selecting the desired reception channel. This is a BS tuner that extracts a video signal and a PCM audio signal including an independent data frame ID.

8 extracts the independent data frame ID contained in the PCM audio signal from the BS tuner 6, and also extracts the frame synchronization part I in the independent data frame ID.
This is a sampling circuit that extracts Dt, and utilizes the fact that the independent data frames included in the PCM audio signal and the frame synchronization parts in the independent data frames have a certain timing relationship, and performs the sampling operation using, for example, a counter. conduct.

10 is a multimedia synchronization detection circuit section which is a main part of the present invention. In this multimedia synchronization detection circuit section 10, 12 directly extracts the 16-bit length data of the BCH (16, 5) error correction code of the frame synchronization section tDt included in the independent data frame ID extracted by the extraction circuit 8. /Serial-to-parallel conversion circuit for parallel conversion, 14 extracts information bit B consisting of 5 bits from the serial-to-parallel converted frame synchronization part ID; 16 is this information bit extraction circuit! Information bit B extracted in step 4
This is a demultiplexer that outputs a signal for selecting a decoder 18 provided corresponding to each media such as text broadcasting and facsimile broadcasting based on the following. Further, 20 is an error detection circuit that detects an error in the frame synchronization unit ID and activates a demultiplexer when there is no error. This error detection circuit 20 includes a latch circuit 22 that latches code data given from a CPU (not shown), etc. when the code of the frame synchronization part ID set for each broadcast medium is known, and a frame synchronization part IDt The comparator 24 compares the data latched by the latch circuit 22 with the data latched by the latch circuit 22.

Therefore, in this multimedia synchronization detection circuit 10, the 16-bit frame synchronization part IDt extracted by the extraction circuit 8 is converted into parallel data by the serial/parallel conversion circuit 12, and this data is extracted from the information bits. circuit 1
4 and the error detection circuit 20. The information bit extraction circuit 14 extracts the information bit B from the frame synchronization section IDt and supplies the information bit B to the demultiplexer 16.

On the other hand, the latch circuit 22 of the error detection circuit 20 latches 16-bit code data set in advance for each broadcast media, and this code data is applied to the comparator 24. Therefore, the comparator 24 compares the data of the frame synchronization unit IDt and the data latched by the latch circuit 22, and if both data match,
A low level signal is output as a start signal for the demultiplexer 20. As a result, the demultiplexer 20
becomes operational and outputs a signal for selecting a decoder 18 provided corresponding to each medium based on information bit data provided from the information bit extraction circuit 14. That is, now the demultiplexer 16 is
If it has two output terminals, a low level signal is output from one of the output terminals depending on the type of information bit B. Then, only the decoder 18 that receives this low level signal is activated. As a result, for example, when a facsimile broadcast is received, the decoder 18 dedicated to the facsimile broadcast operates, and the data portion ID included in the independent data frame ID extracted by the extraction circuit 8 is decoded by the decoder 18. Ru.

FIG. 2 is a block diagram showing another embodiment of the invention.

The embodiment shown in Fig. 1 is applied when the code of the 16-bit frame synchronization part hDt is known in advance, but in the embodiment shown in Fig. 2, the code included in the frame synchronization part IDt is The structure is such that it can operate if only the code of the 5-pit information bit B is known.

That is, in this embodiment, the error detection circuit 32 of the multimedia synchronization detection circuit 30 is connected to the
It consists of a parity check circuit 36 and an OR gate circuit 38, and the other basic configuration is the same as that of the embodiment shown in FIG.

The controller circuit 34 is a circuit that detects errors in the data by determining the remainder of the generator polynomial from the data of the 16-bit frame synchronization unit ID, and if there is no error, the outputs of all the registers become low level. The parity check circuit 36 is a circuit that checks the even parity of the data in the frame synchronization unit ID, and if there is no error, its output becomes low level. Therefore, if there is no error in the frame synchronization section (D), a low level signal is output from the OR gate circuit 38, and the demultiplexer I6 is activated. Therefore, in this embodiment, if the code of information bit B is known in advance, the decoder 18 corresponding to each medium will be selected.

(Effects of the Invention) As described above, according to the present invention, excellent effects such as being able to reliably recognize the type of media of transmission data in television satellite broadcasting with a simple circuit configuration can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the invention, FIG. 2 is a block diagram of another embodiment of the invention, and FIG. 3 is a configuration diagram of an independent data frame. DESCRIPTION OF SYMBOLS 1... Television satellite broadcasting receiver, 8... Extraction circuit, 10, 30... Multimedia synchronization detection circuit, +4... Information bit extraction circuit, 16... Demultiplexer, 18... Decoder, 20.32...Error detection circuit. Sharp Corporation

Claims (1)

[Claims] (1) An independent data frame to which a frame synchronization section containing information bits coded according to each broadcasting medium is added to the data section containing information from various broadcasting media such as teletext and facsimile broadcasting is voiced. A circuit for identifying the information bits of a television satellite broadcasting receiver that receives television satellite broadcasting that is multiplexed into a signal and transmitted, the independent data received by a BS tuner of the television satellite broadcasting receiver. an information bit extraction circuit that extracts the information bits from the frame; a demultiplexer that outputs a signal for selecting a decoder provided corresponding to each medium based on the information bits extracted by the information bit extraction circuit; A multimedia synchronization detection circuit for a television satellite broadcasting receiver, comprising: an error detection circuit that detects an error in the frame synchronization section included in an independent data frame and activates the demultiplexer when there is no error. .