JPS62254513A - Filter circuit - Google Patents

Abstract

PURPOSE:To prevent a short width noise included in an input signal, if any, from appearing at an output by using three flip-flops so as to give a common clock input and a clear input. CONSTITUTION:A signal D1 is inputted to an input D of the 1st flip-flop (FF) 1 and a clock pulse CLOK is inputted to a clock CK of the FFs 1, 2 and 3. A CLEAR input is connected to a clear terminal CL to clear at once the FFs 1, 2 and 3. A Q2 output of the FF 2 and the Q1 output of the FF 1 are inputted to a NAND gate 4, the Q1 output of the FF 1, the Q2 output of the FF 2 are inputted to a NOR gate 6. The output of the NAND gate 4 in connected to the input of a NAND gate 5. An inverted output Q3 of the FF 3 is connected to the other input of the NAND gate 5. Thus, the output is unchanged even to a short width noise included in the input signal D1 and only a correct input signal change is extracted.

Description

DETAILED DESCRIPTION OF THE INVENTION (7) Technical Field The present invention relates to a filter circuit that can correctly detect the rising edge of a pulse.

This filter circuit can be used, for example, for signal processing of a vehicle speed sensor of an automobile. When a long signal pulse with a certain width is generated periodically, it is necessary to differentiate it and generate a short pulse every time the pulse rises.

A differential circuit can be made by combining flip-flops, for example.

In such a circuit, it is necessary to prevent noise from entering. Noise is much narrower than signal pulses, but
Since the differentiator circuit does not detect pulse width, it generates short count pulses in response to noise as well.

) Conventional technology FIG. 3 shows a conventional signal processing circuit.

This is a circuit used in an automobile speed measuring device.

It uses two D flip-flops and one Noah gate.

D1 human power, such as the output of a sensor, is input to the D input of the first stage. This is a pulse waveform in which ゞO' and ``1#'' alternate at a relatively long period. Since we need to count the number of pulses, we will make this a short count pulse.

The Q output (written as Ql) of the first flip-flop 111 is input to the D input of the second flip-flop 70 block 112.

A CLOK input is input to either clock terminal GK.

A CLEA input is connected to the clear terminal CL.

(Noake) 11B is Ql and the second flip-flop 1
12 output Q2 is NORed. Noah Gate 113
The desired short pulse is obtained at the output. It has a pulse width equal to the clock pulse interval.

FIG. 4 shows examples of voltage waveforms at various parts of the circuit element shown in FIG. 3.

(a) is C: LEAR input, ('b) is the signal D1
Human power, (C) is Kurotsuta CLOK input, (d) is Q1 output of the first flip-flop, (e) is Q1 output, (f)
is the Q2 output of the second flip-flop, and (2) is the output of the NOR gate.

When the CLEAR input goes high (rising edge of 50), the flip-flop begins to function.

The D1 input is the output of a rotary encoder such as a vehicle speed sensor, and is a waveform in which H and L alternate at a slow speed (compared to the clock). Pulse rising 51.52.53
・・・・・・ Pulse falling 54.55.58...
Assume that ... is replaced.

The D flip-flop outputs the D input as it is to the Q when a clock input is applied, and stores this value when no clock is applied. Therefore, if there is a rising edge 51 between clocks 59 and 60, Q
l becomes H.

After that, while D1 is H, Ql is H. D1 human power changes to L at fall 54. Ql changes to L in synchronization with the clock pulse 61 input immediately after (fall of 65).

Similarly, the Ql output rises to 66.68,...
...Fall 67.69, and so on.

However, suppose that noise enters D1's human power. The noise is a short negative pulse consisting of a falling edge 56 and a rising edge 57, but it is assumed that a clock pulse 62 enters between 56.570 and 570. Times like this are a problem. Noise is Dl
Even if it enters when it is in a resting state, the same thing will happen if it is caught in the Koreka Flock Pulse.

Since there is a clock pulse 62, the Ql output falls synchronously with it (76). Then the next clock pulse 6
3, it will rise again (77).

Thus, noise pulses (76, 77) are generated in Ql.

Since Ql is simply the inversion of Ql, the falling edge is 70.7
2,... Rise 71, 7B, 75...
In addition to normal pulse changes, noise pulses consisting of a rising edge 78 and a falling edge 79 are included.

The Q2 output is simply the QlQ value delayed by one clock. In addition to the rising edges 80, 82, 84, . . . , it includes falling edges 86 and rising edges 87 due to noise.

The Noah gate 13 calculates the Noah between Ql and Q2. When both are true, the output of the NOR gate becomes H.

Between falling 70 and rising 80, falling 72 and rising 82
Between the falling edge 74 and rising edge 84, Ql, Q2
Both become L. Therefore, pulses 91, 92, and 93 for one clock are generated during this time. This is a normal count pulse.

However, in addition to these, Ql and Q2 also become L between the falling edge 79 and the rising edge 87. Therefore, a pulse 94 due to noise is generated here.

If such a noise pulse 94 exists, the count number will increase. This means that the measured values will not be counted accurately.

(1) Purpose Even if the input signal contains short noise,
It is an object of the present invention to provide a filter circuit that eliminates this and prevents it from appearing in the output.

) configuration A filter circuit of the present invention is shown in FIG.

Three flip-flops are used. Flip-flop 1.2 is a D flip-flop, and flip-flop 3 is a JK flip-flop.

A signal D1 is input to the D input of a first flip-flop (hereinafter abbreviated as FF) 1. FF1, 2.8 clock GK
A clock pulse CLOK is input to.

The CLEAR input is connected to the clear terminal CL,
These FF1, 2.3 can be cleared all at once.

The output Q (written as Q, 1) of the first FFI is
Connect to the D input of F2. Q2 output of FF2 and FFI
91 output is input to the NAND gate 4.

The Q1 output of FFI and the Q2 output of FF2 are input to the NOR gate 6. The output f of the NOR gate 6 is connected to the input of the FFI.

The output of NAND gate 4 is connected to the input of NAND gate 5. Connect the inverted output terminal of the JK flip-flop 8 to the other input of the NAND gate 5. Q3 is the output.

(b) Production FIG. 2 is a waveform diagram of each part of the circuit of FIG. 1.

(a) is CLEARl (b) is signal input D1, (C) is clock pulse, (d) is FFI cQQ, 1 output, (
Q5) is the waveform of the Q2 output of FF2, (f') is the input to FF3, (2) is the J input of FF3, and (h) is the waveform of the Q3 output of FF3. (i) is the output waveform of the NAND gate 4.

Assume that the CLEAR pulse rises (7) and FF1.2.3 starts functioning.

The signal input D1, which is a slow pulse (compared to the clock), such as a vehicle speed sensor, has a rising edge of 8.9 lOl.
..., falling 11, 12, 1B, etc. are alternating signal pulses.

Suppose that a short noise is included in the DI pulse.

Here, the noise is composed of a falling edge 14 and a rising edge 15.

Clock pulse CLOK transfers the value of the D flip-flop input to the Q output. This value is saved until the next clock. A clock pulse is also input to FF3, which is a JK flip-flop, and provides the timing for changing the outputs Q3 and Q3.

Dl becomes H at rising edge 8, and the value of DI is transmitted to ql by clock pulse 16. The output Q1 of FF1 is
Stand up here (20). Also, since Dl becomes L at falling edge 11, Ql falls in synchronization with the next clock pulse 17 (23).

In this way, the output Q1 corresponds to Dl and the rising edge 2
0.21.22, ... Falling 23.24.25
, . . . become pulses that occur alternately.

Since the clock pulse 18 is present during the noise 14.15, Ql falls here. Because it is a short noise,
The time at L is one clock. Although it is for one clock, a noise pulse 19 is mixed into Ql at this time.

The Q2 output of FF2 is the D input shifted every four clock pulses, and since the D input is connected to Ql, Q2 follows the Ql delayed by one clock, and the rising edge of Q2 is 26.27 . 28,...and falling 2
9, 30, 31, . . . are alternating waveforms.

Furthermore, noise also appears in 92 with a delay of one clock. This is the noise corresponding to the falling edge 32 and rising edge 33.

Since the Noah gate 6 calculates the Noah of Ql and 92, Q
It becomes H only when l and Q2 are L, and is L otherwise.

In synchronization with the falling edge of Ql, the output f'(
K input) falls. After this, Q1=L and Q2=L occur between the falling edge 29 and the rising edge 21, between the falling edge 30 and the rising edge 22, etc. by this,
The output f of the NOR gate 6 is 34.35.36, ・
. . . , the rising edge is 37, 38, 39, . . . The waveform is alternated.

What should be noted is that the influence of noise has disappeared here.

The noise 19 on Ql lasts only one clock.

The noise of Q2 is one clock's worth of Alx (Q9-?'LQ))-frL-01)-0 after 19 disappears.
9) I 7:4: There is a difference in time. For this reason,
No noise appears in the output of the NOR gate.

If the noise lasts for two clocks, this noise cannot be erased. However, such long noises rarely occur.

The output of the NOR gate is the input to FF3.

The output of the NAND gate 4 is the NAND of Ql and Q2.

This is shown in FIG. 2(i). In synchronization with the rising edge 26 of Q2, the falling edge 100 . 101, which rises in synchronization with the falling edge 23 of Ql. Since it is a NAND gate, it becomes L only when both Ql and Q2 are H.

Nocilus changes such as 102, 105, 106, 107, 108 are normal, but the rise 103 and fall 1
04 corresponds to noise.

Now, the J input of FF3 is the output i of NAND gate 4,
It is given by the NAND output of FF3.

The output depends on the J input.

Therefore, the J input and h output are not determined immediately. Suppose that h output (grinding) is done. Assume that i is H. J input is H. If J and K are both H, then J
The K flip-flop has a period of 1/2 of the clock pulse.

That is, at the next clock pulse, the h output (Q3) changes to H. Then, the J input becomes L. J is high, K is high
becomes. In this case, when the next clock pulse enters Q3
becomes H. Since this is already H, 6, that is, the h output does not change. In other words, the state where J=L1,=H,)1=l() is stable.

Therefore, the h output is initially H. However, the K input suddenly changes at the falling edge 34. Both are input to J. In this case, the state remains unchanged on the next clock pulse. Therefore, the h output remains at H.

Next, the NAND gate output i falls (100), so
J input rises (40). Then, since J=H and K=t, the h output changes to L at the next clock (45). After this, the output (Q3) remains at L.

Even if the K input rises (37), the output does not change at this time. At the next clock, the h output becomes H (48).

Here, the h output becomes H because both J and J are H, which functions as a 1/2 frequency divider of the clock pulse.

When the h output becomes H, the J input becomes L (43).

Then, J=L1 becomes=H. Therefore, when the h output is H, it is a stable state. From then on, b=H continues.

Even if the K input falls at 35, the same state continues. but,
Since the NAND gate output i falls at 102, the J input changes to H at 41. Since it becomes ±L when J=81, the h output falls at the next clock (46).

Next, the rise of the NAND gate output i (10
8). However, since the h output is L, both NANDs remain at H, and the J input does not change.

Therefore, the influence of noise does not appear on the h output.

, K input rises at 38. Since both Jl are at H, the h output changes at the next clock. In other words, if h
The J input therefore falls (44). J==L, ni=H
Therefore, the state in which the h output is H becomes stable, and this state can be maintained.

In this way, the rise of the h output of FF3 is 48.49,...
What governs is the input to . The K input is completely unaffected by the noise (14, 15) introduced into the H portion of the initial signal D1. Therefore, the h output does not rise due to such noise.

It is the output i of the NAND gate that governs the fall of the h output of FF3, and this is affected by the influence of noise 108.10
4 is mixed in. However, since the output is L at this time,
No noise enters the J input.

In the end, the noise (14, 15) entering the H part of Dl is
It can be cut.

Noise (not shown) that enters the DI part,
With respect to the noise of the upward pulse, the K input will contain noise. This is because K calculates the Noah of Ql and Q2. However, the output i of the NAND gate does not contain noise. This means that the J input, which is the NAND of Ql, force and NAND gate output i, does not contain noise.

The K input includes downward noise between 37 and 35 and between 38 and 36. However, during this time, the J input is at L. Due to noise, r = t, , = L, but both inputs are L.
When , the JK flip-flop maintains its previous state, so the output (h) remains unchanged.

In this way, no matter where noise enters, h output (Q
It can be seen that the effect does not appear in 3).

Effect: Even with short noises contained in the input signal D1, the output does not change at all, and only correct input signal changes can be extracted.

Therefore, a circuit without counting errors can be constructed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a filter circuit of the present invention. FIG. 2 is a waveform diagram of each part in the circuit of the present invention. FIG. 3 is a circuit diagram showing a conventional circuit. FIG. 4 is a waveform diagram of each part of the circuit of FIG. 3. Inventor Hiroshi Ishii Direct Patent Applicant Sumitomo Electric Industries, Ltd.-1J::1r”ljT:
;1 Application agent Patent attorney Shigeru Kawase, j'・・1

Claims (1)

[Claims] A first D flip-flop FF1 has an input signal D1 with alternating signal values H and L connected to its D input, and a second D flip-flop has a Q1 output of the first D flip-flop FF1 connected to its D input. FF2, the Q1 output of the first D flip-flop FF1, and the Q2 output of the second D flip-flop FF2. JK flip flop F
Calculate the NAND of F3, the output of NAND gate 4, and the @Q3@ output of JK flip-flop FF3, and apply the output to FF.
A filter circuit comprising a NAND gate 5 which is input to the J input of No. 3, and a common clock input and clear input are applied to flip-flops FF1, FF2, and FF3.