JPS6225351A - Page history memory processing system - Google Patents

Abstract

PURPOSE:To save a hardware by providing an initial setting means and setting an address array to a proper value, and setting a data array and a page history memory so that pages are neither referred to nor changed. CONSTITUTION:An initializing means 500 sends a request to initialize all addresses of a page history memory 400 to a page address register (PA1) 103 and a data register (DR1) 104 continuously through selecting means (SEL) 101 and 102. The minimum value of a page address is registered in the address array (AA) 105 in response to the request to initialize; and the data array (DA) 206 has both a reference (R) bit and a change (C) bit set to '0' and the page history memory 400 has its R bit and C bit to set both '0'. Then, subsequent processing is performed after the initialization while it is considered that the AA 105, DA 206, and page history memory 400 are all effective.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a page history memory processing method, and particularly to initial settings in a cache-based page history memory processing method.

[Conventional technology]

Conventionally, this type of page history memory processing method has a valid bit (hereinafter abbreviated as ■ bit) in addition to the address in the address array that indicates whether the entry is valid. ■ All bits are 0'
It is also configured to set the data array and page history memory to a parity-matched state for parity checking, etc.

[Problem that the invention seeks to solve]

The conventional page history memory processing method described above has the disadvantage that since v bits are provided in the address array, additional memory for the address array is required for the V bits, and the amount of hardware increases. be.

In addition, since all V bits are disabled at the time of initial setup, the system will be in a miss-hit state for quite some time after the initial setup, resulting in performance degradation due to a large number of accesses to the page history memory. There are drawbacks.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment to which the page history memory processing method of the present invention is applied, in which a secondary storage device 30 for storing information, a central processing unit (hereinafter abbreviated as CPU) 10, Input/output device (hereinafter abbreviated as IOP) 20
, a memory access processing device 40, a page history memory processing device 50, and a main memory device (hereinafter abbreviated as MMtJ) 60. The memory access processing device 40 includes a request reception section 41 and a memory access control section 42.

When a memory access request is issued from cputo or l0P20 to the memory access processing device 40, the memory access processing device 40 accepts the request in the request reception unit 41, and responds to the request in the memory access control unit 42. A memory access request is sent to the MMU 60.

The page history memory processing device 50 has a reference focus (hereinafter abbreviated as the R bit) indicating whether the page on the MMU 60 has been referenced, and a change bit (hereinafter abbreviated as the C bit) indicating whether the page has been rewritten. ) are stored in page units, and updated and read in response to requests for updating and reading the R bit and C bit from the memory access processing device 40.

In response to a memory access request from CPUl0 or l0P20, the memory access processing device 40 accepts the request at the request reception unit 41, and in parallel with issuing an access request from the memory access control unit 42 to the MMU 60, the memory access processing device 40 records the page history. A request is made to the memory processing device 50 to update the R bit and C bit.

In other words, the request from CPUl0 or l0P20 is
60, the R bit of the corresponding page is set to "l", and if the request is a write request, the R bit and C bit of the corresponding page are both set to "l".

Next, details of the page history memory processing device 50 will be explained based on FIG. 1.

The page history memory processing device 50 includes a page history memory 400 composed of an R bit indicating a page reference and a C bit indicating a page change;
Data array (hereinafter abbreviated as DA) that holds a copy of 0
) 206 and the DA 206 is the page history memory 400
an address array (hereinafter abbreviated as AA) 105 having information on which part of the above is to be retained;
A selection means (hereinafter referred to as S
A first stage page address register (hereinafter abbreviated as PAI) 103 and a first stage data register (hereinafter abbreviated as PAI) 101 and 102 (abbreviated as EL) 101 and 102
(abbreviated as DRl) 104, Uke is taken.

Next, the AA105 is indexed using the page address of the PA1103, and its contents are compared with the page address of the PA1103 by a comparing means (hereinafter abbreviated as CMP) 106, and the result is stored in a comparison result register (hereinafter abbreviated as CMR). ) 202 to the control circuit 207 to check whether the R bit and C bit of the corresponding page are present in the DA 206. In parallel with the above operations, PA
The contents of 1103 and DR 1104 are transferred to a second stage page address register (hereinafter abbreviated as PA2) 203 and a second stage data register (hereinafter abbreviated as DR2) 204, respectively.

If it is found in the previous operation that the R bit and C bit of the corresponding page exist in the DA 206 (this case is called hi, t), the data is sent to the PA 220 via the 5EL 205.
The contents of DR2 are not shown at address 3, and R bit 7 bit or C
Write the bit to DA206.

In addition, in the case of reading the R bit and the C bit, similarly read the DA206 to the reply register (hereinafter abbreviated as RPR) 304 using the address of the PA2203,
The data is sent to the memory access processing device 40 via the 5EL 306, and further sent to the request source.

Also, the R bit and C bit of the corresponding page are DA
206 (this case is called a miss), the reception of the next update request for the R bit and C bit is stopped, and the contents of AA 105 are transferred to the second stage address array read register ( The data is read out to the address array read register (hereinafter abbreviated as AA3) 301 of the third stage.

In parallel, the request source page address of PA2203 is stored in the page address register of the third stage (hereinafter referred to as PA3).
Furthermore, the contents of DA206 are read to the third stage data register (hereinafter abbreviated as DR3) 303 at the address PA:2203. Then, a part of each of AAR3301 and PA3302 is selected by 5EL305 and sent to the page history memory 400, and at the same time, the contents of DR3 are also sent, and the contents of DR3 are written to the corresponding address of the page history memory 400. , 5EL305 is switched to the PA3302 side, the contents of PA3302 are sent to the page history memory 400, and the contents are read. The contents read out from the page history memory 400 are sent to the DR 22 via the SEL 107.
04, where it is combined with the contents of the initial R bit and C bit update request and written to the DA 206 at the address of the PA 2203.

In this case, if it is a read request, the contents read from the page history memory 400 are sent to the memory access processing device 40 via the 5EL 306, and further sent to the request source.

In the page history memory processing device 50 that performs such operations, the DA 206. Since the AA 105 and the page history memory 400 are generally composed of RAM, the contents of the RAM become undefined immediately after the power is turned on, and if processing is performed as is, the operation may be logically inconsistent. It will end up being put away. Therefore, it is usually necessary to initialize the RAM.

In this embodiment, initialization means 500 is provided to
105 indicates a specific page address, and DA
206 and page history memory 400 are initialized to indicate that the page has not been referenced or modified.

The initialization means 500 continuously updates all addresses of the page history memory 400 via the SEL 101.102 to the PAI 103. A request for initialization is issued to the DRI 104.

In response to this initialization request, the AA 105 registers the minimum value of the page address, the DA 206 sets both the R bit and the C bit to 0° (a state indicating that the page has not been referenced or modified), and the page Since both the R bit and C bit of the history memory 400 are set to "0°," the AA 105 has the smallest page address in response to an initialization request for all addresses, and the DA 20
6 and page history memory 400, R=O and C-0 are registered, respectively.

After initializing in this way, AA 105. D.A.
206, subsequent processing is performed assuming that all page history memories 400 are valid.

When the page history memory processing method described above is adopted, in a normal information processing device, a small MMU address is often used for processing such as various initial settings after startup. Most of the R bit and C bit updates can be processed using hints, improving performance. Furthermore, hardware can be saved by eliminating the need for the v bit of AA.

Some information processing devices do not use addresses with a small MMU during processing after startup, but in any case, specific addresses are often used intensively, so AA
If you set that address to
Bit and C-bint updates can be handled as hints.

〔Effect of the invention〕

As explained above, in the page history memory processing method, the present invention provides an initial setting means to set the address array to an appropriate value and check the data array and page history memory to confirm that the page has not been referenced or changed. By setting as shown, it is possible to save hardware by omitting the valid bits of the address array, and also to enable hit processing even after initial setting.

[Brief explanation of the drawing]

The first part is a block diagram showing details of a page history memory processing device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an overview of the entire page history memory processing device. In the figure, 10... central processing unit, 20... input/output device, 30... secondary storage device, 40... memory access processing device, 50...
-Page history memory processing device, 60... Main memory device, 101.102, 107, 205, 305.306
...Selection means, 103, 203, 302...
・Page address register, 104.204,303
...Data register, 105 ...Address array, 106 ...Comparison means, 201.301 ...Address array read register, 202 ...Comparison result register, 206
...Data array, 207 ...Control circuit, 304 ...Reply register, 400
... Page immediate memory, 500 ... Initial means.

Claims (1)

[Scope of Claims] A secondary storage device that stores information, a main memory device that stores the information in page units, and a reference bit that indicates whether or not the information has been referenced on the main memory device and whether or not the information has been rewritten. a page history memory that stores change bits indicating whether or not the page has changed on a page-by-page basis; a data array that holds a part of the copy of this page history memory; and an address array indicating whether a reference bit or a change bit of the page history memory corresponding to a page reference or rewrite exists in the data array; then update the reference bit or modified bit in this data array, and if it does not exist, read the corresponding part on the page history memory, update it as the page is referenced or rewritten, and write the page to the data array. In a historical memory processing scheme, initialization initializes the page history memory and the data array to a state indicating that no pages have been referenced or modified, and sets the address array to indicate a particular page. A page history memory processing method characterized by having a means.