JPS62250729A - Diversity receiver - Google Patents

Diversity receiver

Info

Publication number
JPS62250729A
JPS62250729A JP61095167A JP9516786A JPS62250729A JP S62250729 A JPS62250729 A JP S62250729A JP 61095167 A JP61095167 A JP 61095167A JP 9516786 A JP9516786 A JP 9516786A JP S62250729 A JPS62250729 A JP S62250729A
Authority
JP
Japan
Prior art keywords
circuit
signal
antenna
switching
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61095167A
Other languages
Japanese (ja)
Inventor
Atsuya Yokoi
敦也 横井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Communication Equipment Co Ltd
Original Assignee
Toyo Communication Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Communication Equipment Co Ltd filed Critical Toyo Communication Equipment Co Ltd
Priority to JP61095167A priority Critical patent/JPS62250729A/en
Publication of JPS62250729A publication Critical patent/JPS62250729A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To secure the high quality communications and to substantially improve reliability by operating a switching means based on a control signal and transmitting a delay output from a delay circuit by blocking a signal from an A/D converting circuit. CONSTITUTION:If fading occurs in a time t1, a control circuit 5 discriminates a drop in gains in a signal reproduction part, and transmits the control signal to an antenna switching circuit 2 and the switching means 7. Due to the control signal the antenna switching circuit 2 is immediately switched to the side of an antenna 1B, and connects an output terminal from the antenna 1B to the signal reproduction part. On the other hand, when the switching means 7 inputs the control signal, it is switched to the side of the delay circuit 9 after a delay time tau3 elapses, blocks a signal input from the A/D converting circuit 6, and simultaneously transmits delay information from the delay circuit 9 to a D/A converting circuit 8. The switching means 7 maintains such a state for a time taub, then is restored and switched to the side of the A/D converting circuit 6. Thus a drop in gains, which arises at the time of switching the antenna, can be prevented.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は複数のアンテナ素子からの高周波信号を選択的
に切換受信して、フェージングによる影響を減少させ、
信頼性の高い通信を確保するダイバーシチ受信装置に関
する。
Detailed Description of the Invention (Industrial Application Field) The present invention selectively switches and receives high frequency signals from a plurality of antenna elements to reduce the effects of fading.
The present invention relates to a diversity receiving device that ensures highly reliable communication.

(従来の技術) 無線通信では、フェージングによって良質な通信が妨げ
られることから種々のダイバーシチ受信装置が開発され
ている。中でも2以上のアンテナを設置し、これを選択
的に切換受信する所謂スペースダイバーシチ受信方式は
回路構成が簡単なことからよく利用されている。このよ
うなスペースダイバーシチ受信方式を採用するダイバー
シチ受信装置としては第4図に示すようなものが知られ
ている。第4図において、IA及びIBは同一電波を受
信するアンテナであり、所定間隔、例えば到来電波のハ
波長の間隔をおいて設置される。また、アンテナIAs
LBはアンテナ切換回路2に接続されている。ここで第
4図に示すようにアンテナ切換回路2はアンテナ切換側
に切換えられており、アンテナIAからの受信信号のみ
がRF・IF回路3及び検波回路4で成る信号再生部に
与えられ、低周波信号に再生される。フェージングが発
生しアンテナIAの電界強度が低下すると、制御回路5
はRF・IF回路3からの出力低下を判別し、制御信号
をアンテナ切換回路2に送出してアンテナ切換回路2を
アンテナ切換側に切換え、アンテナLBによる受信信号
を信号再生部に与えることでフェージングによる影響を
低減するようにしている。
(Prior Art) In wireless communications, various diversity receiving devices have been developed because fading impedes good quality communications. Among these, the so-called space diversity reception method, in which two or more antennas are installed and selectively switched for reception, is often used because of its simple circuit configuration. As a diversity receiving apparatus that employs such a space diversity receiving method, the one shown in FIG. 4 is known. In FIG. 4, IA and IB are antennas that receive the same radio wave, and are installed at a predetermined interval, for example, at a wavelength of the incoming radio wave. Also, antenna IAs
LB is connected to the antenna switching circuit 2. Here, as shown in FIG. 4, the antenna switching circuit 2 is switched to the antenna switching side, and only the received signal from the antenna IA is given to the signal regeneration section consisting of the RF/IF circuit 3 and the detection circuit 4, and the low Regenerated into a frequency signal. When fading occurs and the electric field strength of the antenna IA decreases, the control circuit 5
detects a decrease in the output from the RF/IF circuit 3, sends a control signal to the antenna switching circuit 2, switches the antenna switching circuit 2 to the antenna switching side, and supplies the signal received by the antenna LB to the signal regeneration unit to prevent fading. We are trying to reduce the impact of

(発明が解決しようとする問題点) しかしながら、高周波信号を受信するアンテナの電界強
度は極めて低く、このような低レベルのアンテナ出力自
体を直接切換えることから、このアンテナ切換の際に受
信信号が瞬断され、復調出力に雑音を生じる。また、ア
ンテナの切換頻度が高くなる程アンテナ切換に伴う切換
雑音の影響が大きくなる。
(Problem to be solved by the invention) However, the electric field strength of the antenna that receives high-frequency signals is extremely low, and since the antenna output itself at such a low level is directly switched, the received signal may be instantaneous when switching the antenna. This causes noise in the demodulated output. Furthermore, the higher the frequency of antenna switching, the greater the influence of switching noise associated with antenna switching.

更には、ダイバーシチブランチとしての全てのアンテナ
IAflBの受信電界強度が設定値以下に低下すると、
アンテナ切換回路2が連続的に切換動作する、所謂ハン
ティング現象が発生し、良質な通信状態を確保すること
ができないという問題があった。
Furthermore, if the received field strength of all antennas IAflB as a diversity branch decreases below the set value,
There is a problem in that a so-called hunting phenomenon occurs in which the antenna switching circuit 2 continuously switches, making it impossible to ensure a high-quality communication state.

(発明の目的) 本発明は上記問題点に鑑みてなされたもので、アンテナ
切換時に発生する雑音による受信感度の低下を防止し、
信頼性の高い通信を確保することのできるダイバーシチ
受信装置を提供することを目的とする。
(Object of the Invention) The present invention has been made in view of the above-mentioned problems, and is intended to prevent a decrease in receiving sensitivity due to noise generated when switching antennas,
It is an object of the present invention to provide a diversity receiving device that can ensure highly reliable communication.

(問題点を解決するための手段) 前述した問題点を解決し上記目的を達成するため本発明
は、複数のアンテナ素子からの高周波信号をアンテナ切
換回路により選択的に受信し、この高周波信号を信号再
生部で低周波信号に再生するダイバーシテ受信装置にお
いて、信号再生部からの出力に基づいてアンテナ受M状
態を判別し該判別結果に応じて制御信号を出力する制御
回路と、信号再生部からの再生信号をディジタル信号に
変換するA / D変換回路と、とのA/D変換回路か
らの信号をスイッチング手段を介して入力し該信号をア
ナログ信号変換するD/A変換回路と、そのアナログ信
号を所定の遅延時間1dだけ遅延する遅延回路とを備え
、制御回路からの制御信号に基づいてスイッチング手段
を作動させ、時間Tdより短かい時間7bの間だけA/
D変換回路からの信号を遮断しつつ遅延回路からの遅延
出力をD/入変換回路に送出するようにしたものである
(Means for Solving the Problems) In order to solve the above-mentioned problems and achieve the above objects, the present invention selectively receives high-frequency signals from a plurality of antenna elements using an antenna switching circuit, and converts the high-frequency signals into A diversity receiving device that regenerates a low frequency signal in a signal regenerator includes a control circuit that determines an antenna reception M state based on an output from the signal regenerator and outputs a control signal according to the determination result, and a signal regenerator. an A/D conversion circuit that converts a reproduced signal from the A/D conversion circuit into a digital signal; and a delay circuit that delays the analog signal by a predetermined delay time 1d, and operates the switching means based on the control signal from the control circuit, so that the A/
The delay output from the delay circuit is sent to the D/input conversion circuit while blocking the signal from the D conversion circuit.

(実施例) 本発明の実施例を図面に基づいて説明する。(Example) Embodiments of the present invention will be described based on the drawings.

第1図は本発明の一実施例をFM受信用の受信装置を例
にとって示したブロック図である。まず構成を説明する
と、IA及びIBはアンテナであり、アンテナIA及び
IBは所定間隔、例えば到来電波のハ波長の間隔をおい
て設置される。各アンテナLA、IBの出力端はアンテ
ナ切換回路2に接続され、アンテナlA*IBにより受
信した高周波信号を後で説明する制御回路からの指令に
基づくアンテナ切換回路2の切換動作で選択される。こ
のように選択された高周波信号は信号再生部、叩ちRF
−IP’回路3及び検波回路4に与えられ、低周波信号
に再生される。信号再生部の構成を具体的に説明すると
、まずRF・工F回路3にはアンテナからの高周波信号
を増幅する高周波増幅回路と、所定周波数で発振する局
部発振器とを内蔵しており、高周波増幅回路で高周波増
幅された増幅信号と局部発振器よりの局部発振信号とを
ヘテロダイン検波し、その差の周波数をビートとして中
間周波数信号を形成している。また、検波回路4はRF
・IF回路3からの中間周波信号の振幅を一定の振幅に
そろえる振幅制限器と、弁別器とを内蔵しており、予め
設定した中心周波数からの周波数偏移に比例した信号を
出力することで中間周波信号から低周波信号を取り出す
ようkしている。5はアンテナ受信状態を判別する制御
回路であり、予め所定の閾値が設定され、RF・IF回
路3からの出力、例えばリミッタ−電流の値が閾値を下
回った場合には制御信号をアンテナ切換回路2及びスイ
ッチング手段7に送出する。
FIG. 1 is a block diagram illustrating an embodiment of the present invention using a receiving apparatus for FM reception as an example. First, the configuration will be described. IA and IB are antennas, and the antennas IA and IB are installed at a predetermined interval, for example, at an interval of the wavelength of the incoming radio wave. The output end of each antenna LA, IB is connected to an antenna switching circuit 2, and the high frequency signal received by the antenna IA*IB is selected by a switching operation of the antenna switching circuit 2 based on a command from a control circuit, which will be explained later. The high frequency signal selected in this way is sent to the signal reproducing section, the RF
- It is given to the IP' circuit 3 and the detection circuit 4, and is regenerated into a low frequency signal. To explain the configuration of the signal reproducing section in detail, first, the RF/engineering circuit 3 has a built-in high frequency amplification circuit that amplifies the high frequency signal from the antenna and a local oscillator that oscillates at a predetermined frequency. The amplified signal high-frequency amplified by the circuit and the local oscillation signal from the local oscillator are heterodyne detected, and the difference frequency is used as a beat to form an intermediate frequency signal. In addition, the detection circuit 4
- Contains an amplitude limiter and a discriminator that adjust the amplitude of the intermediate frequency signal from the IF circuit 3 to a constant amplitude, and outputs a signal proportional to the frequency deviation from a preset center frequency. The low frequency signal is extracted from the intermediate frequency signal. Reference numeral 5 denotes a control circuit for determining the antenna reception state, in which a predetermined threshold value is set in advance, and when the output from the RF/IF circuit 3, for example, the limiter current value, falls below the threshold value, a control signal is transmitted to the antenna switching circuit. 2 and switching means 7.

6は信号再生部、即ち検波回路4からの再生信号をディ
ジタル信号に変換するA / D変換回路であり、A/
D変換回路6からの信号はスイッチング手段7を介して
D/A変換回路8及び遅延回路9に与えられる。ここで
スイッチング手段7は第1図に示すように通常時はA 
/ D変換回路6側に接続されており、制御回路5から
の制御信号を入力すると、第2図に示すようにRF・I
F回路3、検波回路4及びA / D変換回路6による
信号遅延時間τユ経過後遅延回路9側に切換わり、更に
所定時間τb経過後復旧する。この遅延回路9側に保持
する時間τbの値はアンテナ切換回路201回の切換動
作に伴なって発生する雑音の最大持続時間rn以上に設
定される。また、遅延回路9による遅延時間τdの値は
時間τb以上に設定される。D/A変換回路8からのD
 / A変換されたアナログ情報は他の装置、例えば音
響器等に送出される。
6 is a signal reproducing unit, that is, an A/D conversion circuit that converts the reproduced signal from the detection circuit 4 into a digital signal;
A signal from the D conversion circuit 6 is applied to a D/A conversion circuit 8 and a delay circuit 9 via a switching means 7. Here, the switching means 7 is normally set to A as shown in FIG.
/ It is connected to the D conversion circuit 6 side, and when the control signal from the control circuit 5 is input, the RF/I
After the signal delay time τ due to the F circuit 3, the detection circuit 4, and the A/D conversion circuit 6 has elapsed, the signal is switched to the delay circuit 9 side, and after a predetermined time τb has elapsed, it is restored. The value of the time τb held on the side of the delay circuit 9 is set to be greater than or equal to the maximum duration rn of the noise generated due to the switching operation of the antenna switching circuit 201 times. Further, the value of the delay time τd by the delay circuit 9 is set to be greater than the time τb. D from D/A conversion circuit 8
/A converted analog information is sent to another device, such as a sounder.

次に第2図を参照して第1図に示した実施例の動作を説
明する。第2図に示すように時刻t、においてフェージ
ングが発生したとすると、制御回路5が信号再生部にお
ける利得低下を判別し、制御信号をアンテナ切換回路2
及びスイッチング手段7に送出する。アンテナ切換回路
2は制御回路5からの制御信号により直ちに作動してア
ンテナ素子側に切換わり、アンテナIBからの出力端を
信号再生部に接続する。一方、スイッチング手段7は制
御回路5からの制御信号を入力すると、遅延時間τ、経
過後に遅延回路9側に切換わり、A / D変換回路6
からの信号入力を遮断すると同時に遅延回路9からの遅
延情報、即ちアンテナIAからの過去の情報をD / 
A変換回路8に送出する。スイッチング手段7はこの状
態を時間τbのあいだ保持しており、時間τ5経過後復
旧して再びA / D変換回路6側に切換わる。従って
第2図に示すように時刻t2から時刻t、までのあいだ
はアンテナIAからの過去の情報を、また時刻t、以後
はアンテナIBからの現在情報をD / A変換回路8
に送出する。
Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. Assuming that fading occurs at time t as shown in FIG.
and sends it to the switching means 7. The antenna switching circuit 2 is immediately activated by a control signal from the control circuit 5, switches to the antenna element side, and connects the output end from the antenna IB to the signal reproducing section. On the other hand, when the switching means 7 receives the control signal from the control circuit 5, it switches to the delay circuit 9 side after the delay time τ has elapsed, and the A/D conversion circuit 6 switches to the delay circuit 9 side.
At the same time, the delay information from the delay circuit 9, that is, the past information from the antenna IA, is cut off from the signal input from the antenna IA.
The signal is sent to the A conversion circuit 8. The switching means 7 maintains this state for a time τb, and after a time τ5 has elapsed, it recovers and switches to the A/D conversion circuit 6 side again. Therefore, as shown in FIG. 2, the D/A conversion circuit 8 receives past information from the antenna IA from time t2 to time t, and receives current information from the antenna IB after time t.
Send to.

尚、第1図に示した実施例では制御回路5はRF−IF
回路3からの信号出力に基づ−いてアンテナ受信状態を
判別するように構成したが、適宜の信号再生部、例えば
検波回路4かもの信号出力に基づいて受信状態を判別す
るように構成してもよい。
In the embodiment shown in FIG. 1, the control circuit 5 is an RF-IF
Although the antenna reception state is determined based on the signal output from the circuit 3, the reception state may be determined based on the signal output from an appropriate signal reproducing section, for example, the detection circuit 4. Good too.

第3図は本発明の他の実施例をAM受信用の受信装置を
例にとって示したブロック図である。第3図に示した実
施例では検波回路4に組み込まれる自動利得調整回路、
所謂AGC回路からのAGC電圧を制御回路5に与えて
おき、検波回路4からのAGC電圧に基づいてアンテナ
受信状態を判別するようにしたことを特徴とする。
FIG. 3 is a block diagram showing another embodiment of the present invention using a receiving apparatus for AM reception as an example. In the embodiment shown in FIG. 3, an automatic gain adjustment circuit incorporated in the detection circuit 4,
The present invention is characterized in that an AGC voltage from a so-called AGC circuit is applied to the control circuit 5, and the antenna reception state is determined based on the AGC voltage from the detection circuit 4.

尚、第1図及び第3図に示した実施例では、ダイバーシ
テブランチとして2個のアンテナ素子を用いた場合を例
にとって説明したが、本発明はこれを限定されることな
く、3以上の適宜の数のアンテナ素子を用いた場合にも
適用される。
In the embodiments shown in FIGS. 1 and 3, two antenna elements are used as the diversity branch. However, the present invention is not limited to this, and the present invention is not limited to this. This also applies when using an appropriate number of antenna elements.

(発明の効果) 以上説明してきたように本発明によれば複数のアンテナ
素子からの高周波信号をアンテナ切換回路により選択的
に受信し、この高周波信号を信号再生部で低周波信号に
再生するダイバーシチ受信装置において、信号再生部か
らの出力に基づいてアンテナ受信状態を判別し該判別結
果に応じて制御信号を出力する制御回路と、信号再生部
からの再生信号をA/D変換するA/D変換回路と、こ
のA/D変換回路からの信号をスイッチング手段を介し
て入力し該信号をそれぞれD/A変換するD / A変
換回路及び所定の遅延時間τd遅延する遅延回路とを備
え、制御回路からの制御信号に基づいてスイッチング手
段を作動させ、時間7dより短かい時間r1:lのあい
だA / D変換回路からの信号を遮断しつつ、遅延回
路からの遅延出力をD / A変換回路に送出するよう
にしたことで、アンテナ切換時に発生する雑音による受
信利得の低下を防止し、品質の高い通信を確保すること
ができ、ダイバーシチ受信装置の信頼性が大幅に向上す
るという効果が得られる。
(Effects of the Invention) As explained above, according to the present invention, high frequency signals from a plurality of antenna elements are selectively received by an antenna switching circuit, and this high frequency signal is regenerated into a low frequency signal by a signal reproducing section. The receiving device includes a control circuit that determines the antenna reception state based on the output from the signal reproducing section and outputs a control signal according to the determination result, and an A/D that performs A/D conversion of the reproduced signal from the signal reproducing section. A conversion circuit, a D/A conversion circuit that inputs a signal from this A/D conversion circuit via a switching means and converts the signal into D/A, and a delay circuit that delays a predetermined delay time τd, and controls The switching means is activated based on a control signal from the circuit, and the delayed output from the delay circuit is transferred to the D/A converter circuit while blocking the signal from the A/D converter circuit for a time r1:l shorter than the time 7d. This has the effect of preventing the reception gain from decreasing due to noise generated when switching antennas, ensuring high quality communication, and greatly improving the reliability of the diversity receiver. It will be done.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示したブロック図、第2図
は第1図の動作を示したタイミングチャート、第3図は
本発明の他の実施例を示したブロック図、第4図は従来
例を示したブロック図である。 LAslB・・・アンテナ、2・・・アンテナ切換回路
、3・・・RF・IF回路、4・・・検波回路、5・・
・制御回路、6・・・A / D変換回路、7・・・ス
イッチング手段、8・・・D/A変換回路、9・・・遅
延回路。 特許出願人 東洋通信機株式会社 代理人 弁理士 本 庄 伸 介 第1図 :*款の情祇; 1、      13 第2図 第3図 第4図
FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a timing chart showing the operation of FIG. 1, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. The figure is a block diagram showing a conventional example. LAslB...Antenna, 2...Antenna switching circuit, 3...RF/IF circuit, 4...Detection circuit, 5...
- Control circuit, 6... A/D conversion circuit, 7... Switching means, 8... D/A conversion circuit, 9... Delay circuit. Patent Applicant Toyo Tsushinki Co., Ltd. Agent Patent Attorney Shinsuke Honjo Figure 1: *Information about the clause; 1, 13 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】 複数のアンテナ素子からの高周波信号をアンテナ切換回
路により選択的に受信し、該高周波信号を信号再生部で
低周波信号に再生するダイバーシチ受信装置において、 前記信号再生部からの出力に基づいてアンテナ受信状態
を判別し該判別結果に応じて前記切換回路の切換制御信
号を出力する制御回路と、該信号再生部からの再生信号
をディジタル信号に変換するA/D変換回路と、該A/
D変換回路からの信号をスイッチング手段を介して入力
し該信号をアナログ信号に変換するD/A変換回路と、
前記ディジタル信号を所定の遅延時間^τdだけ遅延す
る遅延回路とを備え、 前記スイッチング手段は、前記制御回路からの前記制御
信号に基づいて作動し、時間^τdより短かい時間^τ
bの間だけ前記A/D変換回路からの信号を遮断して前
記遅延回路からの遅延出力を前記D/A変換回路に送出
するようにしたことを特徴とするダイバーシチ受信装置
[Scope of Claims] A diversity receiving device in which high frequency signals from a plurality of antenna elements are selectively received by an antenna switching circuit, and the high frequency signals are regenerated into low frequency signals by a signal reproducing section, comprising the steps of: a control circuit that determines the antenna reception state based on the output and outputs a switching control signal for the switching circuit according to the determination result; and an A/D conversion circuit that converts the reproduced signal from the signal reproducing section into a digital signal. , said A/
a D/A conversion circuit that inputs a signal from the D conversion circuit via a switching means and converts the signal into an analog signal;
a delay circuit that delays the digital signal by a predetermined delay time ^τd, the switching means operates based on the control signal from the control circuit, and the switching means is operated based on the control signal from the control circuit to delay the digital signal by a predetermined delay time ^τd.
1. A diversity receiving device characterized in that the signal from the A/D conversion circuit is cut off only during the period b, and a delayed output from the delay circuit is sent to the D/A conversion circuit.
JP61095167A 1986-04-24 1986-04-24 Diversity receiver Pending JPS62250729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61095167A JPS62250729A (en) 1986-04-24 1986-04-24 Diversity receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61095167A JPS62250729A (en) 1986-04-24 1986-04-24 Diversity receiver

Publications (1)

Publication Number Publication Date
JPS62250729A true JPS62250729A (en) 1987-10-31

Family

ID=14130204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61095167A Pending JPS62250729A (en) 1986-04-24 1986-04-24 Diversity receiver

Country Status (1)

Country Link
JP (1) JPS62250729A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63129728A (en) * 1986-11-20 1988-06-02 Matsushita Electric Works Ltd Diversity receiver
US6226505B1 (en) 1996-11-20 2001-05-01 Nec Corporation Automatic frequency correction apparatus and method for radio calling system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5549042A (en) * 1978-10-04 1980-04-08 Nippon Telegr & Teleph Corp <Ntt> Sound momentary break interpolating receiver
JPS60253333A (en) * 1984-05-30 1985-12-14 Pioneer Electronic Corp Diversity receiver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5549042A (en) * 1978-10-04 1980-04-08 Nippon Telegr & Teleph Corp <Ntt> Sound momentary break interpolating receiver
JPS60253333A (en) * 1984-05-30 1985-12-14 Pioneer Electronic Corp Diversity receiver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63129728A (en) * 1986-11-20 1988-06-02 Matsushita Electric Works Ltd Diversity receiver
US6226505B1 (en) 1996-11-20 2001-05-01 Nec Corporation Automatic frequency correction apparatus and method for radio calling system

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