JPS62248041A - Data processor and memory access controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the field of computer graphics. More particularly, the present invention provides that computer memory stores data for each individual pixel or pixels of a display.
It pertains to the field of computer graphics where bitmaps are stored in memory locations that correspond to the locations of their pixels in a display. Bitmap computer graphics have significant advantages due to the low cost per bit of dynamic random access memory (DRAM). Due to the lower cost per bit of memory, larger and more complex displays can be created in bitmap mode.

The cost per bit of conventional technology memory is reduced and thus
As the capacity of bitmap computer graphics increases, there is a need for a processing device that can effectively utilize bitmap memory in the computer graphics field. In particular, devices have been developed that are capable of drawing simple figures such as lines and circles under the control of a computer's main processor. Additionally, some devices of this type have a limited capability for bit block transfers (known as BIT-BLT or raster operations), which involve transferring data from one memory location to another. It involves transferring image data to a location and logically or computationally combining that data with data at a specified location in memory.

PROBLEM SOLVED BY THE INVENTION These bitmap controllers, with fixed wiring functions for drawing dotted lines and performing other basic graphical operations, represent one solution that meets the performance requirements of bitmap displays. It is something to do. Built-in algorithms that perform some of the most commonly used graphics operations provide one way to improve overall system performance. However, it is a useful graphics system.

Many functions are often required in addition to the few functions performed by such hard-wired controllers. These additional required functions must be implemented in software by the computer's main processor, typically with these hard-wired bitmap controllers.
The processor has only limited access to bitmap memory, thus limiting the extent to which software can augment the functional capacity of a fixed set of hard-wired controllers. Ru. We have therefore developed a flexible solution to the problem of controlling the contents of bitmapped memory, either by providing more powerful graphics controls and/or by allowing better access to this memory by the system processor. It would be very useful if you could provide a high-quality solution.

Means for Solving the Problems The present invention relates to a combination of a data processing device and a memory for storing data for operating the data processing device. A memory access controller connected between the data processing device and the memory controls the exchange of data so that memory read and write operations produce desired results.

According to one feature of the invention, the data processing device operates on data having a selectively variable field size, and the memory uses fixed length words.

The field size used by the data processing device is set by the status register of a given subset. The data in this portion of the status register indicates the length of the field. The data processing device specifies memory addresses in two parts, according to a preferred embodiment. The most significant part of the address is called the word address and points to the entire word in memory. The lowest part of the address is
Specifies the exact bit within the memory word where the specified field begins, and is called the bit address.

A memory access controller allows desired data to be transferred between the data processing device and the memory. The memory access controller uses the field size data, word address, and bit address to determine the memory word within the memory that contains the desired field. In a read operation, each memory word containing a portion of the desired field is accessed. This data is determined to be used correctly by a data processing device using a barrel shifter. This barrel shifter serves to eliminate called data that is not within the desired field by a sign or zero that extends the field to the maximum data length of the data processing device.

In a write operation, this barrel shifter is used to bit-align the field to be written to the bit boundaries specified by the bit address. Write operations are performed as a read/modify/write sequence. Each memory word in memory containing a portion of the field to be written is then accessed. The recalled data is modified to replace the portion of this memory word that corresponds to the field to be written. This modified data is then written to the same location in memory, and thus only in the bits contained within the designated field.

The memory access controller includes control of the number of memory cycles. Because a specified field does not have to match a word boundary, a read or write operation of a field involves multiple memory cycles for the specified field to cross one or more word boundaries. Control of the number of memory cycles is based on the sum of the bit address and field size. Furthermore, this technique can be easily used when the maximum word length of the data processing device is not equal to the word length of the memory.

This memory access controller thus serves to match devices operating at different word lengths.

Another feature of the invention is a memory access priority controller that operates on a variable priority basis. In bitmap graphics systems, multiple devices often compete for access to bitmap memory.

Primarily, the memory must be read periodically to retrieve the data to be displayed from the bitmap.

If the bitmap memory is formed by dynamic random access memory, this memory must be updated periodically. Furthermore, the bitmap memory must be accessed by a graphics data processor that manipulates the data in the bitmap to control the display. Additionally, the host processor, which performs the primary data processing functions of the system, also has access to the bitmap memory.

Determining the priority order for accessing bitmap memory is relatively easy. The first priority must be to update the display, otherwise the display will become unstable. The next priority generally causes memory to be refreshed. This is because this feature ensures that data within the bitmap is not lost. In most systems, the host processor has higher priority than the graphics data processor. That is, the host processor.

This is because it has superior monitoring capabilities to graphic data processors. The implementation of such a priority hierarchy is not continuous.

The above hierarchy gives rise to the following problem.

According to this hierarchy, the graphics data processor has the lowest priority. This is the device that controls the contents of the bitmap, so the display contents have the lowest priority. This makes the ability to change the display relatively slow.

According to an embodiment of the invention, the speed of change of the display is:
Increased by using variable priorities. When the bitmap memory access request is bending, the priority hierarchy is as described above. However, if there are no other bending access requests, the graphics data processor will have first priority. Thus, the speed of display changes is increased when display refreshes, memory refreshes, and host processor accesses are relatively infrequent.

In advantageous embodiments of the invention, one memory access of the graphics data processor requires a large number of memory cycles. In such a case, the graphics data processor's subsequent access requests will have a higher priority than the graphics data processor's initial memory access request. This effectively prevents the overlap of memory graphic accesses of two or more multiple memory cycles. These subsequent memory access cycles have lower priority than display refreshes, memory refreshes, and host processor accesses. Therefore, multiple cycle memory accesses of the graphics data processor result in one or more high priority memory accesses placed between memory cycles. This system works to provide a good trade-off between competing access requests to bitmap memory.

BRIEF DESCRIPTION OF THE DRAWINGS These and other objects of the invention will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram of a graphics computer system 100 constructed in accordance with the principles of the present invention. This graphics computer system 100 includes a host processing system 110, a graphics processor 120,
．． Memory 130, shift register 140. A video palette 150, a digital-to-video converter 160, and a video display 170 are included.

Host processing system 110 provides large computational capacity for GraphInk computer system 100. Preferably, host processing system 110 includes at least one microprocessor, read-only memory, random access memory, and peripherals to form a complete computer system. host processing system 110
It is also desirable to include some type of power device, such as a keyboard or mouse, and some type of long-term storage, such as a disk drive. Host processing system 1
Since the structure of No. 10 is generally known, it will not be described in further detail here. host processing system 11
The essential feature of 0, as far as the present invention is concerned, is that this host processing system 110 determines the content of the visual display shown to the user.

Graphics processor 120 is provided with greater data manipulation in accordance with the present invention in order to provide a particular video display to the user. Graphics processor 120 is bidirectionally connected to host processing system 110 via host bus 115. In accordance with the present invention, graphics processor 120 operates as an independent data processor from host processing system 110. However, it is anticipated that graphics processor 120 will also respond to requests from host processing system 110 over host bus 115. Graphics processor 120 further communicates with memory 130 and with video palette 150 via video memory bus 122. Graphics processor 120 connects video memory bus 12
2 to control data stored in video RAM 132. Graphics processor 120 is further controlled by programs stored either in video RAM 132 or in read-only memory 134. Read-only memory 134 may further include various graphic image data, such as one or more font-type alphanumeric characters and frequently used images.

Graphics processor 120 also controls data stored within video palette 150. This feature will be explained in detail below. Graphics processor 120 also controls digital-to-video converter 160 through video control bus 124 . Graphics processor 120, under control of digital-to-video converter 160 via video control bus 124,
The number of scan lines per frame of the video image presented to the user and the length of the scan lines can be controlled.

Video memory 130 includes video RAM 132 bidirectionally connected to graphics processor 120 via video bus 122 and also includes read-only memory 134.

Video RAM 132, as previously described, contains bitmapped graphics data that controls the video images presented to the user. This video data is manipulated by graphics processor 120 over video bus 122 . Additionally, video data corresponding to the current display screen is output from video RAM 132 via video output bus 136. Data from video output bus 136 corresponds to the pixels shown to the user. Video RAM 132, in the preferred embodiment, is manufactured by Chixas Instruments Corporation (Te), the assignee of this invention.
xas Instruments Corporation
on) multiple 1MS4161 64. formed by a dynamic random access integrated circuit. This 1MS
The integrated circuit at 416164 includes dual ports that allow display playback and display updating without interference.

Shift register 140 receives video data from video RAM 130 and organizes the data into a display bit stream. This memory is video random access memory 1
It is constructed by a number of separate random access memory integrated circuits based on a typical configuration of 32. The output of each of these integrated circuits is typically only one bit wide. Therefore, in order to obtain a sufficiently high data output rate to specify the image to be presented to the user, it is necessary to collect data from multiple circuits.

Shift register 140 is loaded in parallel from video output bus 136. This data is output in series with line 140. In this way, shift register 140
constitutes a display bitstream that provides video data at a rate high enough to specify each dot in the rask scan video display.

Video palette 150 receives and receives high speed video data from shift register 140 via bus 145. Video palette 150 also receives data from graphics processor 120 via memory bus 122.

Video palette 150 converts the data received on bus 145 to a video level output on bus 155. This conversion is performed by a look up table. This look up table is specified by graphics processor 120 via video memory bus 122. The output of video palette 150 may include hue and saturation for each pixel, and may include the red, green, and blue primary color levels for each pixel. Conversion tables from code stored in video memory 132 and digital level output over bus 155 are controlled by graphics processor 120 through video memory bus 122.

Digital-to-video converter 160 receives digital video information from video palette 150 over bus 155. Digital-to-video converter 160 connects graphics processor 120 through video control bus 124.
controlled by Digital-video converter 16
0 serves to convert the digital output of video palette 150 to the desired analog level for feeding to video display 170 via video output 165. Digital-to-video converter 160 is controlled by graphics processor 120 via video control bus 124, for example, to specify the number of pixels per horizontal scan line and the number of scan lines per frame. Data within graphics processor 120 controls the generation of synchronization, blanking, and retrace signals through digital-to-video converter 160. These portions of the video signal are not specified by data stored in video memory 132 and form the control signals necessary to specify the desired video output.

Additionally, video display 170 receives video output from digital-to-video converter 160 through video output line 165. Video display 170 produces designated video images for viewing by an operator of the graphics computer system. video palette 150,
Note that digital-to-video converter 160 and video display 170 operate based on two primary video technologies. In the first technique, video data is specified for each pixel in terms of hue and saturation. In the other technique, the primary color levels of red, green and blue are specified for each pixel. It is possible to select one of these major technologies. Video palette 150, digital-video converter 160
and video display 170 must be configured to be compatible with this technology. However, the principles of the present invention remain the same regardless of the video technology selected with respect to the operation of graphics processor 120.

FIG. 2 shows graphics processor 120 in more detail. Graphics processor 120 includes central processing unit 200. Special graphics hardware 210. Instruction cache 230, host interface 240. Includes memory interface 250, input/output registers 260 and video display controller 270.

The heart of graphics processor 120 is central processing unit 200 . Central processing unit 200 has the capacity to perform general data processing, including many arithmetic and logical operations typically included in a general purpose central processing unit. Additionally, central processing unit 200, alone or in conjunction with specialized graphics hardware 200, controls many specialized graphics instructions.

The graph ink processor 120 includes a main bus 2o5, which is connected to the central processing unit 200.
is connected to most of the graphics processor 120, including the Central processing unit 200 is bidirectionally connected via bidirectional register bus 202 to a set of register files containing a number of data registers. Register file 220 acts as a repository for data available for use by central processing unit 200. As discussed in more detail below, register file 220 includes general purpose registers used by central processing unit 200, as well as a number of data registers used to store implicit operands for graphics instructions. Contains.

The central processing unit 200 has an instruction cache bus 204.
The instruction cache 230 is connected to the instruction cache 230 through the instruction cache 230. Instruction cache 230 is further connected to general purpose bus 205 and can also be loaded with instruction words from video memory 130 through video memory bus 122 and memory interface 250. instruction cache 230
The purpose of the CPU 200 is to speed up the execution of certain functions of the central processing unit 200. Zero-iteration functions or functions that are frequently used within a particular part of a program executed by the central processing unit 200 are stored in the instruction cache 2.
It can also be stored within 30. Instruction cache bus 2
Accessing instruction cache 230 through 04 is even faster than accessing video memory 130. Accordingly, programs executed by central processing unit 200 can be sped up by preloading repetitive instructions or frequently used sequences of instructions into instruction cache 230. Doing this allows these instructions to execute faster because they can be fetched faster. instruction cache 23
0 need not always contain the same set of instructions, but
A particular set of instructions that are frequently used within a particular portion of a program executed by central processing unit 200 may be loaded.

Host interface 240 is connected to central processing unit 200 through host interface bus 206. Host interface 240 further includes:
It is also connected to host processing system 110 through host system bus 115 . host interface 2
40 acts to control communications between host processing system 110 and host system bus 115. Host interface 240 connects host processing system 11
0 and the graphics processor 120. In this regard, host interface 240 may allow host processing system 110 to interrupt graphics processor 120 or, conversely,
to interrupt host processing system 110. Host interface 240 further includes main bus 2
05, thereby allowing host processing system 110 to directly control the data stored within memory 130. Typically, host interface 240 communicates graphics requests from host processing system 110 to graphics processor 120 so that the host system can display video display 17.
0 allows specifying the type of display to be generated and causes the graphics processor 120 to perform the desired graphics function.

Central processing unit 200 connects special graphics hardware 2 via graphics hardware bus 208.
10. Special graphics hardware 210 is also connected to main bus 205.

Special graphics hardware 210 cooperates with central processing unit 20 to perform special graphics processing operations. In addition to its general-purpose data processing capabilities, central processing unit 200 controls the use of special graphics hardware 210 to execute various special graphics instructions. These special graphics instructions involve manipulating bitmapped data in video RAM 132. Special graphics hardware 210 operates under the control of central processing unit 200.

This allows particularly advantageous data manipulation of data within video RAM 132.

Memory interface 250 is connected to main bus 205 and also to video memory bus 122. Memory interface 250 serves to control communication of data and instructions between graphics processor 120 and memory 130. Memory 130 contains bitmapped data to be displayed through video display 170 as well as instructions and data necessary to control the operation of graphics processor 120. These functions include controlling the timing of memory accesses and controlling data and memory multiplexing operations. In the preferred embodiment, video memory bus 122 includes multiplexed address and data information. Memory interface 250 provides access to video memory 1 at a time appropriate for graphics processor 120 to access memory 130.
22 bus can be supplied with an appropriate output.

Graphics processor 120 finally includes input/output registers 260 and video output controller 270. Input/output registers 260 include:
It is bidirectionally connected to the main bus 205. Input/output registers 260 are preferably within the normal memory space of central processing unit 200. Input/output register 260 contains data specifying control parameters for video output controller 270. Video output control 270
issues signals to video control bus 124 to enable desired control of digital-to-video converter 160 according to data stored in input/output registers 260. Data in input/output register 260 includes data for specifying the number of pixels per horizontal scan line, the number of horizontal scan lines per frame, and the vertical sync blanking signal. Input/output registers 260 specify the type of frame skipping and may also include data to specify other types of video control functions. Finally, input/output registers 260 are storage locations for other specific types of input and output parameters. These input parameters and output parameters will be described in detail later.

Graphics processor 120 operates on address memory 130 in two different address modes. These 2
The two address modes are an XY address mode and a linear address mode.

Because graphics processor 120 operates on both bitmapped graphics data and regular data and instructions, different portions of address memory 130 can most advantageously be addressed by different addressing modes. Regardless of the particular address mode selected, memory interface 250 generates the appropriate physical address for the appropriate data to be accessed.

In linear address mode, the starting address of the field is formed by m- multi-bit linear addresses. The size of the field is determined by data in the status register of central processing unit 200. In XY address mode.

The starting address is a pair of X and Y coordinate values.

The size of the field is equal to the size of the pixel, ie, the number of bits required to specify specific data for a specific pixel.

FIG. 3 shows the structure of pixel data based on seven xY addresses. Similarly, FIG. 4 shows a similar data structure in linear address mode. FIG. 3 shows an origin 310 that serves as the reference point for the XY matrix of pixels. The origin 310 is designated as the XY starting address, but need not be the first address location in memory. A location of data corresponding to an array of pixels, eg, a specifically defined image element, is specified in conjunction with an origin address 310. This includes an X start address 340 and a Y start address 330. X start address 340 and Y start address 330
indicates, along with the origin, the starting address of the first pixel data 371 of the desired specific image. The width of the image in pixels is indicated by the quantity delta X350. The image height of a pixel is indicated by the quantity delta Y360.

In the example shown in FIG. 3, the images are numbered 371 to 37.
It contains nine pixels, denoted by 9. The last parameter needed to specify the physical address of each of these pixels is the screen pitch 320, which indicates the width of the memory in number of bits.

These parameters, in particular, X starting address 340, Y
Start address 330, amount delta X350, amount delta Y3
The designation of 60 and screen pitch 320 allows memory interface 250 to be provided with a designated physical address based on a designated XY addressing technique.

FIG. 4 similarly shows a linear memory configuration. One set of fields 441 to 446 is the fourth
As shown in the figure. This set of fields 441-446 may be identical to pixels 371-376 shown in FIG. The following parameters are necessary to specify a particular element according to the linear addressing technique.

The first parameter is the starting address 410, which is the first linear starting address of the first field 441 of the desired array. The second parameter is a quantity delta x indicating the length of a particular segment 1- of a field of many bits
It is 420. The third parameter is the quantity delta Y (not shown in FIG. 4), which indicates the number of a particular segment of a particular array.

The final parameter is linear pitch 430, which indicates the difference in linear starting addresses between neighboring array segments. As with the XY address mode, the specification of these linear address parameters allows memory interface 250 to generate the appropriate specific physical address to be specified.

The two addressing modes are useful for different purposes.

The XY address mode is called screen memory.
It is most useful for the portion of video RAM 132 that contains bitmap data. This screen memory is the portion of memory that controls the display. Linear address mode is
Most useful for off-screen memory such as instructions or image data not currently displayed. This latter category includes various standard symbols used by computer systems, such as alphanumeric fonts and images. Sometimes it is desirable to be able to convert an XY address to a linear address. This conversion is performed according to the following formula.

LA = OFF + (YXSP) + (XXPS) where LA is the linear address, OFF is the screen offset which is the linear address of the origin of the XY coordinate system, SP is the screen pitch in bits, and
is the X address and PS is the pixel size in bits. Regardless of which addressing mode is used, memory 250 issues a physical address suitable for accessing memory 130.

FIG. 5 illustrates how pixels are stored within data words of memory 130. According to a preferred embodiment of the present invention, memory 130 is organized into data words of every 16 bits.

These 16 bits are shown schematically in FIG. 5 as 16 digits 0 through F. According to a preferred embodiment of the invention, the number of bits per pixel in memory 130 is a power of two, but not more than 16 bits, so that each pixel in memory 130 is
A 6-bit word can contain an integer number of such pixels. FIG. 5 shows five available pixels, corresponding to pixel lengths of 1 bit, 2 bits, 4 bits, 8 bits, and 16 bits, respectively. Data word 510 consists of 16 1-bit pixels 511
to 526, thereby allowing 16 1-bit I-pixels to be placed into each 16-bit 1 within a data word. The data word 530 is
Eight 2-bit pixels 531-538 are shown arranged within a 16-bit data word. Data word 540 shows four 4-bit pixels 541-544 arranged within a 16-bit data word. Data word 550 shows two 8-bit pixels 551-552 arranged within a 16-bit data word.

Finally, data word 560 shows one 16-bit pixel 561 located within the 16-bit data word. Providing each pixel in this manner, and particularly each pixel aligned on a physical word boundary with an integer number of bits that is a power of two, enhances pixel operability through graphics processor 120. This is because processing each physical word involves operating on an integer number of pixels. It will be appreciated that in the portion of video RAM 132 that specifies video display, each horizontal scan line of pixels is assigned by a series of consecutive words as shown in FIG.

FIG. 6 illustrates the contents of a portion of register file 220 that stores implicit operands for various graphics instructions. Each of registers 601-611 shown in FIG. 6 resides in the register address space of central processing unit 200 of graphics processor 120. Note that the register files shown in FIG. 6 are not intended to include all possible registers within register file 220. In contrast, typical systems include a large number of general purpose unspecified registers that can be employed by central processing unit 200 for various program specified functions.

Register 601 stores the source address. This address is the address of the lower left corner of the source array. Is this source address a combination of X address 340 and Y address 330 in XY address mode?
Alternatively, it is the linear start address 410 in linear address mode.

Register 602 stores the source pitch, ie, the difference in linear starting addresses between adjacent columns of the source array. This source pitch becomes the source pitch 340 shown in FIG. 3 or the linear pitch 430 shown in FIG. 4 depending on whether the XY address format or the linear address format is adopted.

Register 603 and register 604 are similar to register 601 and register 602, respectively, except that these registers contain a destination start address and a destination pitch. The destination start address stored in register 603 is the address of the lower left corner of the destination array in XY address mode or linear address mode. Similarly, the destination pitch stored in register 604 is
The difference in linear starting addresses between adjacent columns.

In other words, the destination pitch can be 1 screen pitch 320 or linear pitch 34 depending on the selected address mode.
It will be either 0.

Register 605 stores the offset.

The offset is a linear bit address corresponding to the origin of the XY address coordinate system. As mentioned above, the origin 310 of the XY addressing mechanism need not be the physical starting address of memory. The offset stored in register 605 is the linear starting address of the origin 310 of this XY coordinate system. This offset is used to convert between linear addresses and XY addresses.

Register 606 and register 607 store addresses corresponding to windows in screen memory. The window start address stored in register 606 is the address of the lower left corner of the display window.

Similarly, register 607 stores the window end, which is the XY address of the upper right corner of this display window. Each address within these two registers is used to delimit a specified display window. The image within the window within the graphic display can be different from the background image according to known graphics techniques. The window start address and window end address contained within these registers are used to specify the range of the window so that graphics processor 120 can determine whether a particular XY address is inside or outside the window. used.

Register 608 stores delta Y/delta X data. This register 608 is divided into two independent halves, with the top half (high bits) specifying the height of the source array (Delta Y) and the bottom half (low bits) specifying the width of the source array (Delta X). Specify. The delta Y/delta X data stored in register 60g can be provided in either an XY address format or a linear address format depending on how the source array is specified.

For the meaning of the two quantities delta X and delta Y, see Part 3.
As previously discussed in conjunction with FIGS.

Register 609 and register 610 each contain pixel data. Color 0 data stored in register 609 includes pixel values that are copied across the register corresponding to the first designated color O. Similarly, the color 1 data stored in register 610 is
Contains pixel values to be copied across registers corresponding to color value designation color 1. Certain graphics instructions of graphics processor 120 may include, for its data operations,
Either or both of the above color values are used. The use of these registers will be discussed in detail later.

Additionally, register file 220 includes a register 611 that stores a stack pointer address. The stack pointer address stored in register 611 points to the top of the data stack, video RAM 132.
Specify the bit address within. This value is adjusted so that data is pushed into or out of the data stack. In this way, this stack pointer address serves to indicate the address of the last data entered on the data stack.

FIG. 7 illustrates in schematic form the process by which an array is moved from off-screen memory to screen memory. FIG. 7 shows video RAM 132 including screen memory 705 and off-screen memory 715. In FIG. 7, an array of pixels 780 (more precisely, data corresponding to an array of pixels) is transferred from off-screen memory 715 to screen memory 705 to become an array of pixels 790.

Before performing an array move operation, certain data must be stored in designated registers of register file 220. Register 601 must be loaded with the starting address 710 of the pixel's source array. In the example shown in FIG. 7, this load is specified in linear address mode. The source pitch 720 is the register 60
2 is stored. Register 603 is loaded with the destination address. In the example shown in Figure 7, this load is
It is specified in an XY address mode including address 730 and Y address 770. Register 604 is destination pitch 6
45 and the pitch 645 is five rows ahead of the register 60.
It is stored inside 4. The linear address of the origin of the XY coordinate system and offset 1-address 770 are stored in register 605. Finally, delta Y 750 and delta X 760 are stored in separate halves of register 608.

The array move operations shown schematically in FIG. 7 are performed in conjunction with data stored in each register of register file 220. According to a preferred embodiment, the number of bits per pixel is selected such that an integral number of pixels are stored in a single physical data word. This selection also allows the graphics processor to transfer an array of pixels 780 to an array of pixels 790, primarily by transferring all data words. Even with this selection of the number of bits per pixel in relation to the number of bits of the physical data word, in some cases it is necessary to handle partial words at the array boundaries. However, this design choice serves to minimize the need to access and transfer partial data words.

According to a preferred embodiment of the invention, the data transfer shown schematically in FIG. 7 is a special case in which a large number of different data are transformed. Pixel data from each corresponding address location in the source and destination images are combined in a manner specified by the instructions. The combination of data may be a logical operation (eg, AND or OR) or an arithmetic operation (eg, addition or subtraction). The new data stored in the array of pixels 790 in this manner is a function of both the data in the array of pixels 780 and the current data in pixels 790. The data transfer shown in Figure 7 is a special case of a more general variant, in which the data ultimately stored in the destination array does not depend on the data previously stored there. .

This process is illustrated in flow chart form in FIG. According to a preferred embodiment, the transfer is performed sequentially by physical data. Once the process begins (start block 801), the data stored in register 601 is read to obtain the source address (processing block 802). Next, graphics processor 12
0 retrieves the display data word corresponding to the display source address from memory 130 (processing block 8.3).

If the source address is specified in XY format, recalling this data includes converting the XY address to a corresponding physical address. register 60
3 to recall the destination address (processing block 804).
), then derive the display physical data word (processing block 8o5) A similar process is performed for the data contained in the destination location.

The combined data is then returned to its previously defined destination location (processing block 806). The source and destination pixel data are then combined according to the combination mode performed.

This combination is performed pixel by pixel even if the physical data word contains data corresponding to more than one pixel. This combined data is
It is then written to the specified destination location (processing block 807).

Graphics processor 120 determines whether the last data has been transferred with respect to the delta Y/delta X information stored in register 608.
A determination is made whether the entire data has been transferred (decision block 808).

If the entire data transfer has not been performed, the source address is updated. The source address stored in register 601 is used to refer to the next data word to be transferred in relation to the source address previously stored in register 601 and the source pitch data stored in register 602. Updated (processing block 809)
, as well.

The destination address stored in register 603 is:

The destination pitch data stored in register 604 is updated to reference the next data word of the destination (processing block 81o). This process creates a new source stored in register 601 and register 6
The process is repeated using the new destination data stored in 03.

As mentioned above, the delta Y/delta X data stored in register 608 is used to define the limits of the image to be transferred. The entire image is in register 6 as described above.
When the data is transferred while referring to the delta Y/delta It continues to work by running As mentioned above.

In the preferred embodiment, the process shown in FIG. 8 is implemented in instruction microcode. The entire data transformation process, referred to as array movement, is performed in response to a single instruction to graphics processor 120.

FIG. 9 illustrates some of the input/output registers 260 for the present invention. Input/output registers 260 include registers 901-910, which are registers dedicated to storing information regarding input/output control. Register 901 stores a display start address. register 9
02 stores the 5 display refresh address. Register 903 stores the display address increment. Together, these three registers control the portion of video RAM 132 that specifies video display. The display start address stored in register 901 is the start address in video RAM 132, and the memory
At 32, the start of video display is specified. At the beginning of each new display frame, register 9 is
The data in 01 is loaded into register 902 to define the display refresh address. The display refresh address stores the next portion of video RAMP 32 to be read, necessary to define the video display. This address is typically the starting address of the scan line of the video scan. During each horizontal retrace interval, data corresponding to the display address increment stored in register 903 is added to the data stored in register 902, thereby forming the display refresh address. This process continues until the end of this particular video frame when register 902 is again loaded with the display start address from register 901. The hardware for issuing the horizontal and vertical reset signals is shown in FIG.

Register 904 of input/output registers 260 stores the video RAM refresh address. In a typical system, such as the system shown in FIG. 1, video RAM 132 is comprised of dynamic random access memory. This memory is, for the most part, refreshed periodically to retain stored information.

The video RAM refresh address stored in register 904 is the column address to be primarily refreshed. This column address is applied to video RAM 132 along with a refresh signal to refresh all selected rows, based on known principles.

Once this operation is done, the data in register 904 is then changed to .

Incremented to the next column. In this way, the video RAM refresh address corresponds to the next address to be refreshed. Hardware for issuing dynamic random access memory refresh requests is shown in FIG.

Registers 905.906, 907.908 and 909 allow host processing system 110 to directly access memory 130. This is accomplished by providing register 905 with host data, register 906 with host least significant data, and register 907 with host most significant data. These three registers operate to allow host processing system 110 to write to or read from memory 130 through memory interface 250 . This is accomplished by control signals from host processing system 110 and data stored in registers 908 and 909. These registers 908 and 909 store the host's least significant control bit and host's most significant control bit, respectively. In the preferred embodiment, these two registers are 8 bits wide, while the other register 260 is 16 bits wide. Having these two 8-bit wide registers allows host processing system 110, operating as an 8-bit external bus, to directly read or write to each of these registers in a single memory cycle. On the other hand, since graphics processor 120 has a 16-bit wide external bus, these two registers can be read or written in a single memory cycle.

FIG. 10 shows the contents of host control register 1000 corresponding to the combination of host most significant control bit 909 and host least significant control bit 908. Host control register 1000 includes a number of sub-portions that enable communication between host processing system 110 and graphics processor 120. Message input part 1o
01 allows host processing system 110 to send messages to graphics processor 120. This message input part 1001 has 1 interrupt input bit 1
Used with 002. This interrupt input bit 100
2, the host processing system 110 activates the graphics processor 1 in response to a certain request of the host processing system 110.
20 operations can be interrupted. Similarly, the message output part 1003 is the graphic processor 1
2o to send messages to host processing system 110. Coupled with this message output portion 1003 is an interrupt output bit 1004. This interrupt output bit 1004 allows graphics processor 120 to interrupt the operation of host processing system 110 in response to requests for certain priority operations. part 1
005 and 10o6 are used while host processing system 110 performs read and write operations with respect to memory 130. If the incremental write bit 1005 is set, the address formed by the host's lowest control word address 906 and the host's most significant word address 907 is written to the host processing system 11.
It is incremented by 0 each time a read operation is performed. If incremental write bit 1005 is not set, then
These address registers are not incremented during write operations. Similarly, if the incremental write bit 1006 is set, the host's lowest control word address 9
06 and the host's most significant word address 907 is incremented each time a read operation is performed by the host processing system 110. If, on the other hand, the increment write bit 1006 is not set, then such an increment will not occur during a read operation. The ability to perform such automatic incremental read and write operations allows host processing system 110 to read from or write to memory blocks within memory 130 without having to continuously supply primary addresses. be able to.

Cache flush bit 1007 and stop bit 10
08 allows for additional control of graphics processor 120 through host processing system 110. If cache flush bit 1007 is set, graphics processor 120 immediately erases all data stored in instruction cache 230. This feature is most useful when host processing system 110 is loading blocks of instructions for graphics processor 120 into memory 130.

Flushing the instruction cache in this manner ensures that graphics processor 12'O does not perform old instructions previously stored in instruction cache 230, but instead reads updated instructions from memory 130. .

If stop bit 1008 is set, graphics processor 120 is stopped until this bit is reset. This operation is performed by host processing system 110
defines a new set of operations for the graphics processor 120 while the graph ink processor 120
This is useful for stopping all operations. Thus, for example, host processing system 110 may redefine the instructions and data used by graphics processor 120, and during this operation graphics processor 120 is halted to avoid spurious responses.

In accordance with a preferred embodiment of the present invention, the video update and memory refresh operations described above are continued even when graphics processor 120 is stopped. This saves the current display and memory data during the stop interval.

The last register shown in FIG. 9 is control register 91.
It is 0. Control register 910 stores data used to control internal operations of graphics processor 120. The refresh rate section 911 is most relevant to the present invention. Refresh rate section 911 is two bits that determine the refresh rate of the dynamic random access memory forming video RAM 132. Table 1 shows this refresh rate section 91
1 shows a preferred embodiment.

Note that the dynamic random access memory can be updated every 32 or 64 instruction cycles of graphics processor 120, or refresh can be deferred depending on the state of this bit. The particular refresh rate is selected depending on the application for graphics processor 120. However, to ensure the integrity of the data stored in memory 130, the refresh rate should not be set above a certain short period of time).

RR Bit Refresh Rate 00 32 Clock Cycles 01 64 Clock Cycles 10 Unused 1 1 DRAM No Refresh Red FIG. 11 shows the various fields of status register 1100. Status register 1100 stores various instructions regarding the operation of graphics processor 120. Bits 1101.1102.1103 and 1104 are set or reset based on the results of operations by central processing unit 200. If the output of the operation of the central processing unit 200 is negative, the negative bit 110
Set to 1, otherwise this bit is reset. If the operation of central processing unit 200 generates a carry output, carry bit 1102 is set;
Otherwise, this bit is reset. Similarly, a zero output indication is formed via zero bit 1103 and an overflow output indication is formed via overflow bit 110.
Formed by 4. These bits of status register 1100 are automatically set based on the operation of central processing unit 200.

Other portions of status register 1100 shown in FIG. 11 are more relevant to the operation of the present invention. These portions can be set by central processing unit 200 to define two separate sets of field size and field expansion options. field size 0 portion 11
05 is 5 bits that indicates the length of the field acted upon by central processing unit 200. According to a preferred environment of the invention, the central processing unit 2°O comprises 3
Acts on two bits simultaneously.

The graphics processor 120 has a field size of 0.
Based on the field size set in portion 1105, an effect can be applied to a field size of 1 to 32 bits. A similar field size 1 portion 1107 of 5 bits indicates the second field size. The instructions of the central processing unit 200, which is capable of operating with variable field sizes, 5.
Contains one bit to indicate field size 0 portion 1105 or field size 1 portion 1107 of 0. Field extension O bit 11Q6 and field extension 1 bit 1108 indicate the sign extension option for each field size. If the field size operated on by central processing unit 200 is less than 32 bits, the remaining bits must be filled in the following manner. Each field extension O bit 110
These remaining portions of the 32-bit word of central processing unit 200 are filled with O's when the 6 or field extension 1 bit 1108 is ``0''. On the other hand, if this bit is "1", the sign of the number acted upon by the central processing unit 200 is expanded. In this regard, these additional field extension bits are set to 'o' if the number is positive. If this number is negative, these additional field extension bits are set to '1'.

This number corresponds to the use of two's complement arithmetic to represent negative numbers. The operation of selected field sizes and field extensions will be described in detail below with reference to the accompanying drawings.

FIG. 12 shows address register 1200.

In the preferred embodiment, address register 1200 has 32
bit length, which is the same as the length of the data word used by central processing unit 200. In the preferred embodiment, for variable field size selection, address register 1200 specifies a particular bit within memory 130 rather than a more general word specification. Therefore, address register 1200 includes a 4-bit focus address portion 1201 and a 28-bit word address portion 1202. Word address portion 12o2 specifies individual 16-bit words within memory 130 in the preferred embodiment. Bit address 1201 specifies a particular bit within the selected word.

The address sent from graphics processor 120 to memory 130 includes only word address 1202. Bit address 1201 is used within graphics processor 120 to select the desired bit.

FIG. 13 illustrates various cases of the relationship between specific word boundaries in memory 130 and selected field sizes. In accordance with a preferred embodiment of the present invention, graphics processor 120 can write to and read from memory 130 field sizes of selected widths from 1 bit to 32 bits. Furthermore,
In the preferred embodiment of the invention, memory 130 is organized into 16-bit words. FIG. 13 shows each possible case of the relationship between a 16-bit word of memory 130 and the selected field size and start of that field.

Figures 13A-13D illustrate the case where one word access is sufficient to access all specified fields. Figure 13A is the simplest case. In FIG. 13A, a 16-bit field is specified that exactly matches the 16-bit word N of memory 130. In the case shown in FIG. 13A, the operation of the read field requires reading a single data word N. The operation of the read field similarly involves writing a single memory word N.

The case shown in FIGS. 13B-13D occurs when the specified field is completely within a single data word N of memory 130, but does not match exactly this data word N. .

FIG. 13B illustrates the case where the least significant bit of the designated field does not coincide with the start of data word N, but the most significant bit of the designated field does coincide with the most significant bit of data word N. Similarly, FIG. 13C shows the case where the least significant bit of the data field is aligned with the least significant bit of memory word N, but the most significant bit is not. Furthermore, FIG. 13D shows the case where the field is completely contained within data word N without being aligned to either the least significant bit or the most significant bit.

In each case of FIGS. 13B-13D, when reading a designated field, it is possible to read only a single data word N from memory 130 and mask the bits that are not contained within this designated field. Needed. on the other hand.

A compounding operation is required to write fields such as those shown in FIGS. 13B-13D. First, data word N must be recalled from memory 130 and then the bits corresponding to the specified fields must be changed without changing the other bits of data word N.

Finally, this modified data word is stored in memory 130
is written to the same location as data word N in the data word N. This combination of operations is referred to as a read/modify/write operation.

Figures 13E-13H illustrate an example where two consecutive data words in memory 130 must be accessed when accessing a specified field.

Figure 13E shows the simplest example of these cases. In FIG. 13E, a pair of consecutive data words (data word N and data word N+) in memory 130 are shown.
A 32-bit field that corresponds exactly to 1) is specified. When reading a field such as that shown in Figure 13E, two consecutive read operations are required. Similarly, when writing a field such as that shown in FIG. 13E, two consecutive full word seeding operations are required.

Figures 13F-13H illustrate the case where a specified field intersects one data word boundary.

In FIG. 13F, the specified field begins at a position within data word N and ends at the end of data word N+1. When reading such a data field, two successive read operations must be performed with a corresponding mask applied to the first read operation to remove bits that are not contained within the designated field. When writing such a field, a read/modify/write operation must be performed on data word N and a simple write operation must be performed on data word N+1. FIG. 13G shows the case where the specified field starts at the least significant bit of data word N and ends somewhere in the next data word N+1. When reading such a data field, it is necessary to perform two consecutive read operations with corresponding masking. When writing such a data field, it is necessary to perform one write operation on data word N and a read/modify/write operation on data word N+1. FIG. 13H shows that the data field starts within data word N, crosses a word boundary, and crosses data word N.
This shows a case where the number ends with +1. To read such a data field, it is necessary to perform two consecutive read operations with corresponding masking. Writing such a data field requires two consecutive read/modify/write operations on data word N and data word N+1.

FIG. 13I shows the simplest case of fields associated with word boundaries according to a preferred embodiment of the invention. In FIG. 13I, a designated field begins at N data words N, crosses two consecutive data word boundaries, and ends somewhere within data words N+2.

When reading such a data field, it is necessary to perform three consecutive memory read operations with corresponding masking to remove bits of data word N and data word N+2 that are not present in the specified data field. It is. Writing such a data field requires performing a read/modify/write operation on data word N, a write to data word N+1, and a read/modify/write operation based on data word N+2. It is.

FIG. 14 illustrates hardware within memory interface 250 that provides access to memory 130 based on a set of priorities and provides access to memory 130 via central processing unit 200 with a specified field size. Another portion of graphics processor 120 is shown. FIG. 14 shows a plurality of registers 902, 904 that are part of input/output registers 260.
．． 906/907 and 905 are shown. Furthermore, the first
Figure 3 shows the address register 1200 of the central processing unit.
It shows. Each of these registers is connected to memory interface 250 for connection to bus 122. Also connected to the memory interface 250 are data latches, including a central processing unit top pit data latch 1440 and a central processing unit bottom pit data latch 1445.

Control of the operation of memory interface 250 is performed by sequencer 1400. sequencer 1400
receives and takes various input control and data signals. The control signals include a display refresh request appearing on input 1401, a DRAM refresh request appearing on line 1402, and a host access request appearing on line 1403.
Includes host read/write control cursed on line 1404, central processing unit access request appearing on line 1405, and central processing unit read/write control appearing on line 1406.

Sequencer 1400 receives data signals from multiple sources. First, the bit address 1201 from the address register 1200 of the central processing unit is zero detector 1.
420. The bit at bit address 1201 is provided to sequencer 1400 via line 1.407. A zero detection signal from zero detector 1420 is provided to sequencer 1400 via line 1408.

The bit address from bit address register 1201 is also sent to adder 1418. Adder 1418 is
The field size is received from bus 1417. As mentioned above, the field size is sent from status register 1100. Either field size 1105 or field size 1107 is determined by central processing unit 200.
selected by the specific instruction executed by. This selection results in a field size of 5 bits for bus 141.
7 and is sent to adder 1418. The output of adder 1418 is a 6-bit quantity stored in latch 1419. 4 least significant bits (denoted as bits 0 to 3)
is sent to zero detector 1421. These four least significant bits are sent to sequencer 1400 via bus 1411.

The zero indication signal is sent to the sequencer 14 via line 1412.
Sent to 00. The two most significant bits of latch 1419 (designated bits 5 and 4) are respectively.

It is sent to the sequencer via lines 1409 and 1410. The sequencer 1400 outputs 1413°, 1414.
1415 and 1416 are generated. The control configuration for these outputs will be explained below.

Multiplexer 143o controls specific data sent to memory bus 122. Multiplexer 1430 is connected to register 904 to receive and receive display refresh addresses via bus 1431. Similarly, multiplexer 1430 receives the composite host address from registers 906 and 907 via bus 1433. Register 905 containing host data is bidirectionally connected to multiplexer 1430 via bus 1434.

Word address portion 1202 of address register 1200 of central processing unit 1 is sent to multiplexer 1430 via bus 1435. Bus 1436 connects multiplexer 1430 to right mask 1437, left mask 14
38. It is bidirectionally connected to input/output latte 1439 and to central processing unit 200 via bus 205. Right mask 1437 is controlled via line 1413 from sequencer 1400. Similarly, left mask 1438
is controlled by sequencer 1400 via line 1414. The right mask 1437 is the multiplexer 143
0 to input/output latch 1439 via bus 1436. Similarly, left mask 1438 serves to mask the most significant bits of this data transfer.

The central processing unit includes a central processing unit most significant bit data latch 1440 and a central processing unit least significant bit data latch 1445, which are bidirectionally connected to input/output latch 1439 via bus 205. Line 1415 from sequencer 1400 is
Determine whether the data transfer occurs from the most significant bit 1440 or the least significant bit 1445. Central processing unit 200 further includes a barrel shifter 1450 bidirectionally connected to two portions of data latches 1440 and 1445 of the central processing unit. Barrel shifter 1450 shifts data received from the combination of central processing unit top pit data latch 144o and central processing unit bottom pit data latch 1445 as specified by central processing unit 200. Barrel shifter 1450 is controlled by field code/zero extension controller 1451.

As discussed with respect to FIG. 11, the Field Extension O bit 1106 or Field Extension 1 bit 1108 specifies whether the field is an extended sign or an extended zero. One of these two bits of status register 1100 is selected by the extended specific instruction. This control is sent to barrel shifter 1450 and used as described below. The barrel shifter 1450 is
It is connected to other parts of central processing unit 200 via bus 1455.

The general operation of memory controller 250 is described below with respect to FIG. Based on the particular control and data signals received by sequencer 1400, sequencer 1400 selects one source that is sent to multiplexer 143o for feeding to memory 130 via bus 122.

Thus, for example, sequencer 1400 enables multiplexer 1430 to connect a display refresh address stored in register 902 to memory in response to a display refresh request on line 1401. Similarly, a DRAM refresh request on line 1402 causes sequencer 1400 to control multiplexer 1430 to provide the video RAM refresh address stored in register 904 to memory 132 .

A host access request appearing on line 1403 and a host read/write control signal appearing on line 1404 cause sequencer 1400 to
30 to enable the host addresses stored in both registers 906 and 907 to be provided to memory 130 via bus 122 and to exchange data between the memory and register 905 based on the selected operation. It can be so. Additionally, the central processing unit access request appearing on line 1405 and the central processing unit read/write control signal appearing on line 1406 cause the sequencer 1400 to cause the central processing unit access request appearing on line 1405 to cause the sequencer 1400 to access the central The word address of the processing unit is sent to the multiplexer 14.
30 to memory 130 via 6. The bus is then connected between memory 130 and the central processing unit based on the read or write operation selected by the central processing unit read/write control signal appearing at input 1406. Data is exchanged via 1436. In this case, this data is transmitted to right mask 1437 and left mask 14 based on control signals sent from sequencer 1400 via control lines 1413 and 1414, respectively.
38. This data is then exchanged with data from the central processing unit bottom pit data latch 1445 and the central processing unit top pit data latch 1440, as described in more detail below.

FIG. 15 shows a structure for generating horizontal and vertical reset signals that allows the display 1 request signal to be generated on line 1401. The structure shown in FIG. 15 is part of a video display controller 270 that controls the formation of a video display by video display 170. Dot rate, ie.

A video clock at the pixel display rate on video display 170 is received at input 1501 . This video clock is sent to the count input of counter 1510. Comparator 1520 receives the count of counter 1510 and transfers it to register 153o corresponding to the total number of pixels or pixel equivalents in the horizontal line.
Compare with the count stored in . If these two counts are equal, comparator 1520 produces an output on line 1502 that corresponds to the horizontal reset signal.

This output is sent to the reset input of counter 1510 to reset the counter and start counting for the next line. A horizontal reset signal 1502 sends a display refresh request 1401 to the sequencer 14.
00.

Horizontal reset generated by comparator 1520) -15
02 is provided to the second counter 1540. Counter 1540 counts the horizontal reset signal and provides this count to comparator 1550. Also, comparator 155
0 also takes a count from register 1506 which stores the total number of lines or line equalizers per vertical frame.

Comparator 1550 produces an output signal on line 1503 corresponding to a vertical reset when these two counts are equal. This vertical reset signal is sent to the reset input of counter 1540 to reset the counter.

Due to the generation of the vertical reset signal 1503, the register 90
The starting point of the display address stored in 1 is the register 902.
to reset the display refresh address to the start of a new video frame.

FIG. 16 shows a structure that generates a DRAM refresh request signal that is sent to input 1402 of sequencer 1400. A central processing unit clock signal is received at input 1601.

This central processing unit clock signal is a clock signal that operates the central processing unit 200 and controls its operating speed. This signal is passed to programmable divider 16
Sent to 10. Programmable divider 1610 is also provided with a control signal via line 1602. This control signal is received from the fast/slow decoder 1620. The fast/slow decoder 1620 detects refresh rate bits 91 which are part of the control pit register 910.
1. As mentioned above, in accordance with the preferred embodiment, this bit indicates that the dynamic random access memory is refreshed once every 32 central processing cycles or once every 64 cycles. or whether a dynamic random access memory refresh signal is not generated. According to refresh rate bit 911 of control register 910, fast/slow decoder 1620 generates a signal to programmable divider 161o. A programmable divider 1610 receives and receives this control signal and outputs a dynamic random access memory refresh request signal 1610 at a selected rate.
Occurs on o3.

This is used at input 1 of sequencer 14oO to issue a dynamic random access memory refresh request.
402.

FIG. 17 is a detailed block diagram of sequencer 1400. The sequencer 1400 includes a set of latches 1700,
a logical array of programmable input addresses 1710;
Address register 1720, control read-only memory 1
730 and a micro sequencer 174o.

Various request signals are sent to individual latches within the set of latches 1700. The signals of these latches are sent to a programmable input address logic array 1710, which generates input addresses for supply to control read-only memory 1730. This derived input address is stored in address register 1720. Once this input address is generated, control read-only memory 1730 controls the operation of microsequencer 1740 to generate the various output signals of sequencer 1400.

Latch 1700 includes a set of latches for storing various request and control signals provided to sequencer 1400. Latch 1700 includes a display request latch 1701 that receives a display refresh signal. D.R.
AM refresh request launch 1702 is line 14
00(7) Receives a DRAM refresh request signal.

Host request latch 1703 receives and receives a host request signal on line 1403. Host read/write control latch 1704 receives and receives host read/write control signals on line 1404. The third request latch 1705 of the central processing unit is activated by the microsequencer 174o on the control line 1743, as described in detail below.
It is set after

Similarly, the second request latch 1706 of the central processing unit
is set by microsequencer 1740. The central processing unit first request latch 1707 receives and receives the central processing unit request signal appearing on line 1405. Additionally, a central processing unit read/write control latch 1708 receives and receives a central processing unit read/write control signal on line 1406.

Programmable input address logic array 1710 includes:
It receives and receives signals from each of the launches 1700. Additionally, programmable input address logic array 1710 receives and receives control signals 1742 from microsequencer 1740. This control signal primarily indicates whether microsequencer 1740 is concerned with servicing the current memory access request. Based on signals sent to programmable input address logic array 1710, addresses specifying input points within control read-only memory 1730 are generated. This address is address register 1
720 and stored here.

Address register 1720. Control read only memory 1
730 and microsequencer 1740 constitute a programmable controller. Read-only memory 1730 controlled by programmable input point logic array 1710
The input point selected within is the starting point of a subroutine for responding to the corresponding memory access request. The instructions for these subroutines stored in control read-only memory 1730 are sequentially supplied to a microsequencer 1740, which is connected to lines 1413.14.
14. Perform various output operations based on these instructions appearing at 1415 and 1416. in this regard,
An increment signal is provided from microsequencer 1740 via line 1741 to address register 172o each time a normal instruction is executed to enable the next instruction to be called. In addition to the outputs described above, microsequencer 174o generates a control output to latch 1700 via line 1743. This control output is related to setting and resetting various latches within latch 1700.

Furthermore, the microsequencer 174o
It receives host read/write control signals via line 1406 and central processing unit read/write control signals via line 1406. A general overview of certain control subroutines within control read-only memory 1730 is described in detail below with respect to FIGS. 18, 19, 20, and 21.

FIG. 18 is a diagram of a program 1800 detailing the operation of programmable input address logic array 1710. In particular, program 1800 illustrates the priority of operations in determining input point addresses by programmable input address logic array 1710. In a preferred embodiment.

Special hardware logic is used in programmable input address logic array 1710 to perform the functions shown in FIG. 18, but a program is provided in control read-only memory 1730 to perform the same functions. You can also do that.

Program 18 constitutes a continuous loop in which memory access requests are processed in priority order. If microsequencer 1740 was not idle during the previous cycle, program 1800 determines whether the received request is a display refresh request (decision block 1801). In such a case, a display refresh request is processed (processing block 180
2). This is accomplished by generating a starting address in control read-only memory 1730 that contains a subroutine to refresh the display. As mentioned above, for this display refresh, the data to be displayed next is called from the video RAM 132, and the data to be displayed next is read from the register 9.
The display address increment stored in register 90
This includes updating the display refresh address stored in 2. If a new frame starts.

It includes loading the start point of the display address stored in register 901 into register 902 and resetting the 1 display refresh address. This process is common and well known.

I will not explain it further here.

If the bending request is not a display refresh request, program 1800 performs a test to determine whether the bending request is a DRAM refresh request (decision block 180).
3). The request that is bending looks like this
If it is an AM refresh request, the DRAM refresh request is processed (processing block 1804).
.

This DRAM refresh request is processed as described above for the 1 display refresh request. progera 1
1 possible input address logic array 1710 is a DRAM
Generates the starting address of a subroutine in control read-only memory 1730 that contains the program that controls microsequencer 1740 to perform refresh requests. This process is generic and will not be described further. After this refresh request is processed.

The program 1800 returns to testing to determine if the display refresh request is the highest priority operation at processing block 18o1.

If the bending request is not a DRAM refresh request, program 1800 checks to determine whether the bending request is a host memory access request (decision block 1).
805). If the bending request is a host memory access request, the request is processed (processing block 1806). This host memory access request is processed as described above by inputting a subroutine in control read-only memory 1730.

Once this host memory access request has been processed, the program 1800 returns to testing at decision block 1801 to determine whether a display refresh is the highest priority access.

Program 1800 performs a test to determine whether the request being bent is the central processing unit's third access request (decision block 1807).

As shown in FIG. 13I, a field access request from central processing unit 200 may require the performance of three consecutive memory word accesses. When the second access request of the central processing unit is processed and a third access request of the central processing unit is required, the microsequencer 1740 generates a control signal on line 1743 to 3 request latch 1
Set 705. In such case, the central processing unit's third access request is processed (processing block 1808). This process is described in detail below in connection with program 2100 shown in FIG.

If the request being bent is not the third access request of the central processing unit, the program 1800
tests to determine if this is the central processing unit's second access request (decision block 1
809). again.

Referring to FIG. 13, it is apparent from FIGS. 13E-13 that a large number of field accesses by central processing unit 200 require two (or more) consecutive memory word accesses. There are cases where When the first access request of the central processing unit has been processed and it is determined that the second access request of the central processing unit is required, the microsequencer 1
740 generates a control signal on line 1743 to set the second request latch 1706 of the central processing unit. In this case, this second access request of the central processing unit is processed (processing block 1810), a process described in detail below with respect to program 2000 shown in FIG. As before, once this access request has been processed, program 1800 returns to decision block 1801 to determine whether a display refresh request has been issued.

In order to give the central processing unit's access request first priority when no other memory access request is bending, the program 1800 assigns a bending access request to a bending access request other than the central processing unit's first access request. Perform a test to determine whether there is (
decision block 1811). If another access request is bending, program flow returns to decision block 1801 to test whether there is a higher priority memory access request. However,
If no other access request is bending, program 1800 tests to determine if this is the central processing unit's first access request (decision block L 812). When central processing unit 200 wishes to access memory 130, it communicates with sequencer 140 via line 1405.
Issue this request to 0. The origination of such a request is the central processing unit's first access request. If no such central processing unit access request is issued, program 1800.

The process returns to testing whether other higher priority access requests are bending (decision block 1811). This sequence is maintained in this loop, but if a higher priority request is issued, decision block 1811 directs program flow to decision block 18o1 to test and process the request. Alternatively, if a central processing unit first access request is issued, it is processed (processing block 1813).

This priority technique works to control the order of memory accesses when two or more memory access requests are pending at the same time. If two or more memory access requests become bending at the same time, they are executed in priority order.

In this case, the display refresh request has the highest priority, followed by the DRAM refresh request, the host access request, the central processing unit third access request, the central processing unit second access request, and finally the central processing unit This is followed by the first access request. By giving progressively higher and different priorities to successive access requests of the central processing unit, two results are obtained.

First, the central processing unit's multiword access request is partially completed and then interrupted by a higher priority request. Furthermore, in such a multi-word access request of a central processing unit, successive word accesses are given progressively higher priority.
The central processing unit must wait for such multiword access to complete until it can process another individual central processing unit access. This prevents the two access requests of the central processing unit from interfering.

The loop including decision blocks 1811 and 1812 ensures that the central processing unit's first access request has the highest priority if the other access request is not bending, but if the other memory access request is bending. If so, it has the lowest priority.

As mentioned above, the process illustrated in FIG. 18 is preferably performed using programmable input address logic array 1710 rather than by a program executed by a processor. Programmable input address logic array 171o provides display request latch 170
Generates the starting address of a program sequence in control read-only memory 1730 to process a display refresh request when a 1 is entered. DRAM refresh request latch 1 when there is no display refresh request
If 702 is set.

Programmable input address logic array 1710 includes:
Generates a starting address in control read-only memory 173o to respond to a DRAM refresh request. Similarly, programmable input address logic array 1710
generates a starting address in control read-only memory 1730 to perform the operations based on the priority order described above with respect to FIG. 18 when any of the request latches 1700 are set.

FIG. 19 shows a program 1900 for processing the first access request of the central processing unit. This program 1900 includes processing block 1813 shown in FIG.
is one of a set of memory accesses for processing subroutines stored in control read-only memory 1730. Upon entering the program (start block 1901), the program first tests to determine whether the access request is a read access (decision block 1902). This determination is made based on the state of the central processing unit read/write signal sent to sequencer 1400 via line 1406. If the memory access request requests a read of memory, then the memory is read (processing block 1903). This is accomplished by sending the address stored in the central processing unit's address register 1202 along with the memory read signal to the memory 130 via multiplexer 1430. The data word stored in this memory location is 1 then 5 in the input/output latch 143.
9 is loaded. Right mask 1437 and left mask 14
38 has no effect on this data transfer.

This data is then loaded into the least significant bit data latch 1445 of the central processing unit (processing block 1904). Memory data that is not in the desired data field, as described below.

It is removed at barrel shifter 1450. The program then proceeds to decision block 1914, which tests whether a second central processing unit access request is needed.

If the central processing unit access request is a write request and not a read request, the program 1900
performs a test to determine whether the bit address is zero (decision block l 905). This test is simply performed by zero detection circuit 1420. This circuit receives the bit address and sends a signal on line 1408 indicating whether the bit address is zero.
occurs in If the bit address is zero, the desired data field begins on a memory word boundary. This is shown in Figures 13A, 13C, 13E and 13.
This corresponds to the case shown in Figure G. If the bit address is zero, program 190o tests to determine whether the sum of the bit address and field size is equal to or greater than 16 (decision block 1906). The sum of the bit address and field size formed by adder 1418 is added to line 1409.
and the sequencer 140 via 1410 and bus 1411.
Sent to 0. Additionally, zero detection circuit 1421 provides an indication of whether the four least significant bits (bits 0-3) of this sum are zero.

This sum is 16 if line 1412 indicates that bit 5 of line 1409 is a ``1'' or bit 4 of line 1410 is a ``1'' and bits 0-3 are non-zero. Become bigger. If this is the case and corresponds to the cases of FIGS. 13A, 13E, and 13G, the first access request of the central processing unit will be a simple write operation. The input/output latch is the lowest pit data latch 1445 of the central processing unit 1-
(processing block 1907).

The program then sets the data in the input/output latches to
Write to the memory indicated by the central processing unit word address stored in register 1202 (processing block 1913). As described above, program 1900 performs a test to determine whether a second central processing unit access is required (decision block 1914).
.

If the bit address is not zero, program 19
00 is the right mask 1427 corresponding to the pin 1 address
Set. The bit address is sent to sequencer 1400 via bus 1407. If the bit address is non-zero, or if the bit address is zero and the sum of the bit address and field size is either 16 or 32, program 1900 adds the bit address and field size. A test is performed to determine whether the sum of is greater than 16 (decision block 1909). If this sum is less than 16, then the left mask is set based on this sum (processing block 1910), regardless of whether the bit address is zero or non-zero, otherwise the field Since the left mask extends to or beyond the memory word boundary, the left mask is not needed. In any case, input/output latch 1
439 is loaded from the lowest pit data latch 1445 of the central processing unit (processing block 1911).
. The memory word pointed to by the word address of the central processing unit stored in register 1202 is read and this is used as right mask 14:37 and left mask 14.
38 to modify the data in input/output latch 1439 (processing block 1912). This process is.

The portion of the memory word that is not present within the selected data field is not changed, while the portion of the memory word that is within the selected data field is replaced with the data previously loaded from the data latches of the central processing unit. be able to do so. The data thus modified is corrupted to the same memory location (processing block 1913).

The program 1900 ends by testing whether a second access of the central processing unit is needed. This is determined by checking whether the bit address plus field size is greater than 16 (decision block 1914). If this sum is greater than 16, a second access is required.

This is the second access request latch 1 of the central processing unit.
706 (processing block 1915). This is a micro sequencer 1740
to request latch 1700 via line 1743. In any event, the central processing unit's first request latch is reset (processing block 1916), indicating that the request has been processed. Then program 190
0 is the end (end block 1917). As mentioned above, the program 1900 is equivalent to the processing block 1813 shown in FIG.

FIG. 20 shows a program 2000 for processing the second access request of the central processing unit. This program 2000 includes processing block 18 shown in FIG.
10, which corresponds to control read-only memory 173
This is one of a set of memory accesses that process the subroutine stored in o. The program started on the 19th
This is similar to the program 1900 shown in the figure. Note that the central processing unit word address stored in register 1202 must be incremented to refer to the correct memory data word on the central processing unit's second access.

Since the address stored in address register 1200 of the central processing unit includes bit address 1201, the number 16 must be added to address register 1200 to refer to the primary memory word.

When entering this program (start block 2001
), a test is first performed to determine whether the access request is a read access (decision block 20).
02). This determination is made based on the state of the central processing unit read/write signal provided to sequencer 1400 via line 1406. If the memory access request requires reading memory, as described above for processing block 1903.

Memory is read (processing block 2003).

The data retrieved from memory 130 in this manner is stored in the most significant pit data latch 144 of the central processing unit.
0 (processing block 2004). Data in memory that is not within the desired data field is removed at barrel shifter 1450, as described in detail below. The program then proceeds to decision block 20.
11, a test is made as to whether a third access request of the central processing unit is necessary.

If the second access request of the central processing unit is a write request and not a read request, program 2
000 performs a test to determine whether the sum of the bit address and field size is greater than or equal to 32 (decision block 2005). Bit 5 of the sum of line 14o9
is "1", the sum is 32 or more. If this sum is greater than or equal to 32, the write operation extends beyond the second word boundary. In such a case, the second access of the central processing unit is a simple write operation. Accordingly, the input/output latch is loaded from the most significant bit data latch 1440 of the central processing unit (processing block 2006), and the data in the input/output latch is written to memory (processing block 2010). As with the read operation, the program then proceeds to decision block 2011 where a test is made as to whether a third central processing unit access request is required.

If the bit address plus field size is less than 32, a left mask is required. This left mask is set based on the bit address plus field size (processing block 2007). The input/output latches are loaded with data from the central processing unit's top pit data latch 1440 (processing block 2008).6 The memory word pointed to by the central processing unit's word address is recalled from memory 130 and left input while being masked by mask 1438/
The output latch is loaded (processing block 2009).

This process is shown in processing block 19 in FIG.
The same as described above in connection with No. 12. Note that the right mask is not required since the central processing unit's second access will naturally involve the least significant bit of the memory word (Figures 13E, 13F, 13G, 13I). (see Figure and Figure 13I), now you can input /
The output latch will contain the data retrieved from memory 130 and modified as required by the field write operation for the bits within the selected field.

The program 2000 concludes by testing whether a third access of the central processing unit is required. This is determined by checking whether the bit address plus field size is greater than 32 (decision block 2011). If this sum is greater than 32, a third access is required.

This is the third access request latch 1 of the central processing unit.
705 (processing block 2012). This is a micro sequencer 1740
to request latch 1700 via line 1743. In any event, the first request latch of the central processing unit is reset (processing block 2013), indicating that the request has been processed. Now program 2000
is the end (end block 2014). As mentioned above, program 200o is equivalent to processing block 1810 shown in FIG.

FIG. 21 shows a program 210o that processes the third access request of the central processing unit. This program 2100 is best understood in conjunction with the word alignment diagram of FIG. Initially, the central processing unit's address register 1200 must be incremented by 16 to reference the next memory word after the second access.

In this respect, the process is similar to the central processing unit's processing of the second access request described above. The program 2100 shown in FIG. 21 corresponds to the process of processing block 18o8 shown in FIG.

When the program 210o starts (start block 21
01), a test is performed to determine whether the access request is a read access request (decision block 21).
02). If the request is a read request, the right mask 1437 is set by the bit address (
Processing block 2LO3). This process is best understood with reference to FIG. Field 2200 includes, at least in part, memory words 2201 .
2202 and 2203 are included. This is the 13th I
This is the case shown in the figure, ie the only case where a third process access request is necessary.

Field 2200 has three subfields:
It can be divided into a subfield 2211 contained entirely within memory word 2201, a subfield 2212 corresponding to memory word 2202, and a final subfield 2213 contained entirely within memory word 2203.

The first access of the central processing unit is to subfield 2.
211 in the upper bits of the least significant bit data latch 1445 of the central processing unit. The second access of the central processing unit is to access memory word 22.
The subfield 2212 corresponding to 02 is stored in the most significant bit data latch 144o of the central processing unit. The third access of the central processing unit must be a read, mask and modify operation similar to the read/modify/write operations described above. Data from the central processing unit's least significant bit data latch 1445, including the previously called subfield 2211, is loaded into the input/output latch (processing block 2104). Memory word 2203 is recalled from memory 130 and the portion determined by right mask 1437, including subfield 2212, is loaded into input/output latch 1439 (processing block 2105). The resulting input/output latch data is stored in the least significant bit data latch 1445 of the central processing unit (processing block 2106). The data obtained by this is the first subfield 2211 and the third subfield 221.
3. As with the read access described above, barrel shifter 1450 provides access to central processing unit 20.
0 to align the data for proper use. This is explained in detail below in connection with FIG. 23.

If the central processing unit's third access is a write access, a read/modify/write cycle is required. Left mask 1438 is bit address 1
201 and the field size (processing block 2107). The data stored in the central processing unit's least significant bit data latch 1445 is loaded into the input/output latch (processing block 2108); the memory word 2203 is read from memory 130 and input/output using the left mask 1438. Loaded into output latch 1439 (processing block 2109)
. At this time, input/output latch 1439 has the least significant bit corresponding to subfield 2213 and memory word 2.
203, and a most significant bit corresponding to the most significant bit of No. 203.

This data in input/output latch 1439 is then written to memory 130 at the same location as memory word 2203 (processing block 2110) to complete the read/modify/write operation. In any case, the third access of the central processing unit is completed by resetting the third request latch of the central processing unit (processing block 2).
111), progera t, 2 L OO is completed (end block 2112).

The technique of inputting the first subfield 2211 and the third subfield 2213 to the least significant bit data latch 1445 of the central processing unit 1- eliminates the need for a three word data latch in the central processing unit. Note that in the preferred embodiment, the field length does not exceed 32 bits. However, some combinations of bit addresses and field sizes require that the selected field occupy portions of three consecutive memory words. The two subfields are.

The reception is housed in a single 32-bit latch containing the two 16-bit halves shown. Therefore, providing a third 16-bit data latch is advantageous.

This results in wasted circuit area. By storing two subfields in one hand of the data latch, no additional circuitry is required. The above masking allows these subfields to be properly separated.

Central processing unit most significant bit data latch 1440
and the least significant bit data latch 14 of the central processing unit.
By circularly shifting the data within 45, the subfields can be properly aligned in bit order.

According to a preferred embodiment, all field operations within central processing unit 200 are performed while adjusting data to the right. When performing a field write operation,
Barrel shifter 145o circularly shifts the data to the left by an amount equal to the bit address before loading into data latches 1440 and 1445 of the central processing unit. This serves to properly align the data for field write operations. This circular shift to the left causes the second
As shown in FIG.
and a third subfield 2213 are automatically formed.

As discussed above, data read from memory 130 is aligned by barrel shifter 145o for use by central processing unit 200. This process is the second
This is shown in Figure 3. The data from central processing unit data latches 144o and 1445 is the most significant bit 2
301 and the least significant bit 2302. The selected field 2310 is shown crossing the word boundary between the most significant bit 23o1 and the least significant bit 2302. This alignment is provided for illustrative purposes only. I mean.

This technique applies equally to all other field alignments. First, the field is adjusted to the right by circularly shifting it to the right by the amount of bits indicated by the bit address.

This process is shown schematically at 2311).

The fields are 2211, 2212 and 221 in Figure 22.
This shift adjusts the entire field 2310 to the right in the proper order, even when divided into three subfields as shown at 3.

Other parts of the data word (not included within selected field 2310) are not important as they will be lost in the next process.

The field is then adjusted to the left by logically shifting it to the left by an amount 32 bits less than the field size. This process, illustrated schematically at 2312, operates to eliminate bits of higher order than the most significant bit of the selected field. field 23
Bits smaller than the 10 least significant bits should be removed in the first order stage and are therefore not important. Field 2310 is again finally logically shifted to the right by an amount 32 bits less than the field size. This removes bits of lower order than the least significant bit of field 2310. The upper bits are the effect field extension bit 11 from the status register 11oO.
Generated based on the status of o6 or 1108. The specific instructions executed by central processing unit 200 include field size 0 1105 and field extension 0 1
106 or field size 1107 and field extension 1108. If the selected field extension bit of status register 110o indicates a zero extension, upper bits 2320 of all "0"s are generated. On the other hand, if the field extension option instructs sign extension, all upper bits 233 equal to the most significant bit of field 2310
0 is generated.

The preferred embodiments of the present invention have been described in detail above. Although several design choices were made in this preferred embodiment, these are not necessary to practice the invention. For example, the central processing unit has been described as using data that is 32 bits long, while the memory has been described as using words that are 16 bits long. If you are a person skilled in the art.

It will be clear that these are merely convenient design choices and are not the essence of the invention. The scope of the present invention is
shall be defined by the claims.

In connection with the above description, the following items are disclosed.

A data processing system as claimed in the claims, further comprising: (1) a field size register connected to the central processing unit 1 to store a selected number of bits M.

(2) Each of the field memory access commands includes a field size selection portion for indicating a first field size having a first data length or a second field size having a second data length. , the memory access controller is responsive to the field memory access command to access the memory having an M-bit data field equal to the first data length if the field size selection portion indicates the first field size; and accessing said memory having an M-bit data field equal to said second data length if said field size selection portion indicates said second field size. .

(3) a memory interface for transmitting address, data, and read/write control signals; and operating on a data field having a selectable number of bits M to generate field read memory commands and field write memory commands. a central processing unit; and an address register connected to the central processing unit and having a plurality of bits for indicating individual bits in the memory at the beginning of an M-bit data field.

The above memory interface, the above central processing 221~
and a memory access controller connected to the address register and adapted to connect to a memory having N-bit data words stored in a plurality of memory locations.

Memory read signals and address signals corresponding to N-bit data words of memory are provided to said memory interface to access said N-bit data words, each such N-bit data word being responsive to a field read memory command. responsively includes a portion of the M-bit data field pointed to by the address register, and further provides a memory read signal and an address signal to the memory interface corresponding to the N-bit data word of the memory to modifying the retrieved N-bit data word by calling an N-bit data word and replacing the bits corresponding to the M-bit data field; and transmitting a memory write signal, the modified N-bit data word and the address signal. said memory interface to write said modified N-bit data words into memory, each such N-bit data word being written to said memory interface with said modified N-bit data words directed to said address register by said address register in response to a field write memory command; A data processing device comprising a portion of an M-bit data field.

(4) The data processing device of claim 3, further comprising a field size register connected to the central processing unit to store the selected number of bits M.

(5) Each of the field memory access commands includes a field size selection portion for indicating a first field size having a first data length or a second field size having a second data length. , the memory access controller is responsive to the field memory access command to access the memory having an M-bit data field equal to the first data length if the field size selection portion indicates the first field size; and accessing said memory having an M-bit data field equal to said second data length if said field size selection portion indicates said second field size. .

(6) The data processing system according to item 2 or 5, further comprising a field size register connected to the central processing unit to store the first data length and the second data length.

(7) The predetermined number of highest bits 1 to 1 of the above address register.
5. A data processing apparatus as claimed in claim 1 or 4, wherein the bits indicate address locations of individual N-bit I-data words, the least significant bits of which indicate bit addresses within said N-bit data words.

(8) the memory access controller includes an adder for adding the bit address and the field size; the memory access controller accesses a number of N-bit data words based on the relationship of the sum to N; The data processing device according to item 4 or 7 above.

(9) The memory access controller accesses a number of N-pi I-data foods equal to the sum of the bit address and field size divided by N, rounded to the nearest integer. The data processing device described in section.

(10) A memory having a plurality of address locations for storing and recalling data, and generating periodic display update access requests to recall display data corresponding to the visual display from successive address locations of the memory. and a video display device connected to the memory and generating a video display corresponding to the retrieved display data.

a local processing unit that performs operations based on the data, including local memory read operations to read data from the memory and local memory write operations to write data to the memory, the local processing unit comprising: generating a local processor memory access signal when a read operation or a memory write operation is requested, and generating a read/write control signal indicating whether a read or a write is requested; a local address register that specifies one of the address locations within the processor; and a local processor data register that receives data from the memory during memory read operations and provides data to the memory during memory write operations. and further connected to the memory, the display update timer, and the local processing unit to receive memory access requests and hold these memory access requests in a bending state until granted.

a memory priority controller for granting access to said memory in priority order by providing a corresponding address signal, a memory access request signal and a corresponding read/'8 write signal to said memory; The controller grants the display update access request at a higher priority than the local processor's access request if it previously had a bending memory access request, and the memory priority controller grants the bending memory access request. If the local processor access request has no previous memory access request, the local processor access request having a higher priority than the display update access request is permitted.

(11) The display update controller includes a display update address register for specifying one of the address locations in the memory where display data to be called next is stored, and periodically generates the display update request signal. a display update timer to
display update address register increasing means for increasing the address stored in the display update address register in order to refer to display data to be called primarily when each display update memory access is permitted; The memory access control system according to item 10 above.

(12) The memory is a dynamic memory that requires periodic refresh to retain data, and the memory access control system further includes a memory refresh controller that periodically generates a refresh memory access signal. The memory access controller includes:
a refresh address register storing an address to be refreshed next; and the memory priority controller further receives the refresh memory access signal and the memory priority controller is configured to bend a memory access request. If the memory priority controller previously had a bending memory access request, the memory priority controller grants the refresh memory access signal with a lower priority than the display update access request and higher priority than the local processor access request; is connected to the memory refresh controller to grant the refresh memory access request at a lower priority than the local processor access request and the display update access request if the refresh memory access request does not previously have a refresh memory access request. The memory access control system according to item 10.

(13) a memory interface for transmitting address, data, and read/write control signals and a display update for generating periodic display update access requests to recall memory display data corresponding to the visual display from successive address locations; a controller connected to the memory interface and configured to cause the memory interface to generate specified address and read control signals for reading data from memory; and a local memory read operation for causing the memory interface to read data from memory. a local processing unit for performing operations on the data, including a specified address for writing the data and a local write memory operation for generating a write control signal.

The local processing unit generates a local processor memory access signal when either a memory read or write operation is requested and a read/write control signal indicating whether a read or write operation is requested. the local processing unit has a local address register for specifying an address location, and a local processing unit that receives data from the memory interface during memory read operations and provides data to the memory interface during memory write operations. a processor data register, and further connected to the memory interface, the display update timer, and the local processing unit to receive memory access requests and hold these memory access requests in a bending state until granted. and the corresponding address signal.

a memory priority controller for granting access to the memory in priority order by providing a memory access request signal and a corresponding read/write signal to the memory interface; If the controller previously had a bending memory access request, it grants the display update access request with a higher priority than the local processor's access request, and the memory priority controller handles the bending memory access request. The memory access control system is characterized in that, if the local processor access request has not been previously held, the local processor access request having a higher priority than the display update access request is granted.

(14) The display update controller includes a display update address register that specifies one of the address locations in the memory in which display data to be called next is stored, and a display that periodically generates the display update request signal. an update timer; and a display update address register incrementing means for incrementing the address stored in the display update address register in order to refer to display data to be called next when each display update memory access is permitted. 14. The memory access control system according to item 13.

(15) A memory refresh controller connected to the memory interface and periodically generating a refresh memory access signal, the memory access controller having a refresh address register storing an address to be refreshed next. , the memory priority controller is further connected to the memory refresh controller to receive and receive the refresh memory access signal, and the memory priority controller is further connected to the memory refresh controller to receive and receive the refresh memory access signal and to determine whether the memory priority controller previously has a bending memory access request. the refresh memory access signal of lower priority than the display update access request and higher than the local processor access request if the memory priority controller previously had a bending memory access request; 14. The memory access control system according to item 13, wherein if there is no access request from the local processor, the refresh memory access request having a lower priority than the local processor access request and the display update access request is permitted.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a computer having a graphic function configured based on the principles of the present invention; FIG. 2 is a block diagram showing a preferred embodiment of the graphic processing circuit of the present invention; FIG. FIG. 4 is a diagram illustrating how individual pixel addresses in a bitmap memory are specified using addressing techniques; FIG. 4 is a diagram illustrating how field addresses are specified using linear addressing techniques; FIG. FIG. 6 is a diagram illustrating a preferred embodiment of storing pixel data of various lengths within one data word according to a preferred embodiment of the present invention. FIG. FIG. 7 is a diagram showing the characteristics of the array movement operation within the bitmap memory of the present invention; FIG. 8 is a flowchart of the bit block transfer, that is, the array movement operation according to the present invention; FIG. , a diagram illustrating some of the input/output registers used in the preferred embodiment of the invention. 10 is a detailed diagram of the host control register shown in FIG. 9; FIG. 11 is a detailed diagram of the status register according to a preferred embodiment of the present invention. FIG. 12 is a detailed illustration of an address register according to a preferred embodiment of the present invention, and FIGS. 13A-13I are diagrams showing various relationships between selected fields and memory words according to a preferred embodiment of the present invention. FIG. 14 is a diagram showing the structure of a memory access controller according to a preferred embodiment of the present invention. FIG. 15 is a diagram illustrating structures for generating horizontal and vertical reset 1 signals in accordance with a preferred embodiment of the present invention. FIG. 16 is a diagram illustrating a structure for generating a DRAM refresh signal according to a preferred embodiment of the present invention; FIG. 17 is a detailed diagram of the sequencer shown in FIG. 14; FIG. A flowchart illustrating the operation of the programmable input address logic array shown in FIG. 17 in accordance with a preferred embodiment; FIG. A flowchart explaining the operation. FIG. 20 is a flowchart illustrating the operation of the sequencer when performing the second memory access of the central processing unit in accordance with a preferred embodiment of the present invention. FIG. 21 is a flowchart illustrating the operation of the sequencer when performing the third memory access of the central processing unit according to a preferred embodiment of the present invention. FIG. 22 is a diagram illustrating how fields that intersect two memory word boundaries are stored and manipulated according to the present invention;
FIG. 23 is a diagram showing the operation of the barrel shifter shown in FIG. 14. 100...Graphic computer system 110
...Host processing system 115...Host bus 120...Graphic processor 122...Video memory bus 130...Memory 132...Video RAM 134
...Read-only memory 140...Shift register 150...Video palette 160...Digital-video converter 170...
Video display 200...Central processing unit 210...Graphics hardware 220...Register file 230...Instruction cache 240...Host interface 250...Memory interface 260...Input/output registers 270...・Video display controller
CI+,. Electric!
52, 4. 30 Showa year month day

Claims (1)

Claims: Based on a memory having a plurality of address locations and adapted to store an N-bit data word in each address location, and a data field having a selectable number of bits M. a central processing unit operatively connected to said central processing unit for generating at least one type of field memory access command; an address register having a plurality of bits; and each N-bit data word of said memory connected to said memory, said central processing unit and said address register and comprising a portion of an M-bit data field pointed to by said address register. and accessing at least one N-bit data word stored in said memory in response to a field memory access command by generating a memory address corresponding to and accessing each of said N-bit data words. A data processing system characterized by comprising a device.