JPH0762835B2 - Memory access control system - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to the field of computer graphics. More particularly, the present invention relates to the field of bit-mapped computer graphics in which a computer memory stores data for each individual pixel or pixel of the display at a memory location corresponding to that pixel location in the display. Pertain to.
Bitmapped computer graphics have significant advantages due to the low cost per bit of dynamic random access memory (DRAM). Due to the lower cost per bit of memory, larger and more complex displays can be created in bitmap mode.

[0002]

2. Description of the Related Art Bitmap memories can be effectively used in the field of computer graphics by reducing the cost per bit of memory and thus increasing the capacity of bitmap computer graphics. A processing device is needed. In particular,
Some form of device has been created that is capable of drawing simple figures such as lines and circles under the control of the computer's main processor. Furthermore, some devices of this type
It provides some limited functionality for bit block transfers (known as BIT-BLT or raster operation), which transfers image data from one location in memory to another. Logically or arithmetically combining that data with the data at the specified location in memory.

[0003]

These bitmap controllers, which have a fixed wiring function for drawing lines and performing other basic graphic operations, have been designed to meet the performance requirements of bitmap displays. It represents a solution. Built-in algorithms that perform some of the most frequently used graphics operations provide one way to improve overall system performance. However, useful graphics systems often require a large number of functions in addition to some functions performed by such fixed-wiring controllers. These additional required functions must be implemented in software by the main processor of the computer. Typically, these fixed-wired bitmap controllers only allow the processor to have limited access to the bitmap memory, and thus, a fixed set of fixed-wired controllers. Limits the extent to which the functional capacity of the can be increased by software. Thus, the flexibility to control the contents of the bitmapped memory by providing a more powerful graphics controller and / or allowing the system processor to have good access to this memory. It would be very useful if we could provide a high solution.

[0004]

A feature of the present invention is a memory (access) priority controller that operates on a variable priority basis. In bitmap graphics systems, many devices often compete for access to bitmap memory. Primarily, the memory must be read periodically to retrieve the data to be displayed from the bitmap. If the bitmap memory is a dynamic random access memory, this memory must be updated periodically. In addition, the bitmap memory must be accessed by the graphics data processor that manipulates the data in the bitmap to control the display. Further, the host processor, which exhibits the main data processing function of the system, can also access the bitmap memory.

Determining the priority of accessing the bitmap memory is relatively straightforward. The first priority is that the display must be updated or the display will be unstable. The next priority generally causes the memory to refresh. This feature ensures that the data in the bitmap is not lost. In most systems, the host processor has a higher priority than the graphics data processor. Because the host processor
This is because it has a monitoring capability superior to that of the graphic data processor. Implementation of such a priority hierarchy is not difficult.

The above hierarchy creates some problems. According to this hierarchy, the graphics data processor has the lowest priority. This is the device that controls the contents of the bitmap, so the contents of the display have the lowest priority. This makes the function of changing the display relatively slow. According to an embodiment of the invention, the changing speed of the display is increased by using a variable priority.
When the access request to the bitmap memory is pending, the priority hierarchy is as described above. However, if there are no other pending access requests, the graphics data processor will be the first priority. Therefore, the display change speed is
Increased when display refresh, memory refresh and host processor access are relatively infrequent.

In an advantageous embodiment of the invention, a memory access of the graphics data processor requires a large number of memory cycles. In such a case, subsequent access requests of the graphics data processor will have a higher priority than the initial memory access requests of the graphics data processor. This effectively prevents superposition of memory graphic accesses for multiple memory cycles of two or more. These subsequent memory access cycles are of lower priority than the display refresh, memory refresh and host processor access. Therefore, multiple cycles of memory accesses of the graphics data processor are one or more high priority memory accesses located between memory cycles. This system serves to make a good tradeoff between competing access requests to the bitmap memory.

[0008]

These and other objects of the invention will be readily understood by the following detailed description in conjunction with the accompanying drawings. FIG. 1 is a block diagram of a graphic computer system 100 constructed according to the principles of the present invention. The graphic computer system 100 includes a host processing system 110, a graphic processor 120, a memory 130, a shift register 140, and a video palette 1.
50, a digital-to-video converter 160 and a video display 170 are included.

The host processing system 110 has a large computing capacity for the graphic computer system 100. The host processing system 110 has at least one
It is desirable to configure a complete computer system with a microcomputer, read only memory, random access memory and peripherals. The host processing system 110 preferably also includes some form of input device such as a keyboard or mouse and some form of long term storage such as a disk drive. The structure of the host processing system 110 is generally known and will not be described in detail here. An essential feature of the host processing system 110, as far as the invention is concerned, is that the host processing system 110 determines the content of the visual display presented to the user.

The graphics processor 120 has superior data manipulability in accordance with the present invention to provide a particular video display to the user. The graphic processor 120 is bidirectionally connected to the host processing system 110 via the host bus 115. According to the invention,
The graphics processor 120 operates as an independent data processor from the host processing system 110. However, it is expected that the graphics processor 120 will also respond to requests from the host processing system 110 over the host bus 115. The graphics processor 120 further communicates with the memory 130 and also with the video palette 150 via the video memory bus 122. The graphics processor 120 controls the data stored in the video RAM 132 via the video memory bus 122. The graphics processor 120 is further controlled by a program stored either in the video RAM 132 or in the read only memory 134. Read only memory 134
May further include various graphic image data such as one or more font-type alphanumeric characters and frequently used images. Graphic processor 1
The 20 also controls the data stored in the video palette 150. This feature will be described in detail below. The graphics processor 120 also controls the digital-to-video converter 160 via the video control bus 124. The graphic processor 120 is
The control of the digital-to-video converter 160 through the video control bus 124 can control the number of scan lines and the length of the scan lines per frame of the video image presented to the user.

The video memory 130 has a video bus 122.
It includes a video RAM 132 which is bidirectionally connected to the graphics processor 120 through a read-only memory 134. Video RAM 13
2 contains bit-mapped graphic data, as described above, which control the video image presented to the user. This video data is operated by the graphic processor 120 via the video bus 122. In addition, the video data corresponding to the current display screen is displayed on the video output bus 13
6 is an output from the video RAM 132. The data from the video output bus 136 corresponds to the pixels shown to the user. Video RAM 132, in the preferred embodiment, is Texas Instruments Co., the assignee of the present invention.
RMS) TMS4161 64K dynamic random access integrated circuit. This TM
The S4161 64K integrated circuit includes a dual port, which allows playback of the display and updating of the display without interference.

The shift register 140 is a video RAM 1
Receives video data from 30 and organizes the data into a display bit stream. This memory is constructed by a number of separate random access memory integrated circuits based on the typical configuration of video random access memory 132. The output of each of these integrated circuits is typically only 1 bit wide. Therefore, it is necessary to collect data from multiple circuits in order to obtain a sufficiently high data output rate to specify the image presented to the user. The shift register 140 is loaded in parallel from the video output bus 136. This data is the output in series with line 140. In this way, the shift register 1
40 constitutes a display bit stream, and this display bit stream is
It provides video data at a rate high enough to specify each dot in a raster-scan video display.

Video palette 150 receives high speed video data from shift register 140 over bus 145. The video palette 150 has a memory bus 122.
Through, also receives data from the graphics processor 120. Video palette 150 converts the data received on bus 145 into a video level output on bus 155. This conversion is done by a look-up table. This look-up table is specified by the graphics processor 120 via the video memory bus 122. The output of video palette 150 may include hue and saturation for each pixel, and may include red, green and blue primary levels for each pixel. The conversion table from the code stored in the video memory 132 and the digital level output via the bus 155 are controlled by the graphics processor 120 via the video memory bus 122.

Digital-to-video converter 160 receives digital video information from video palette 150 via bus 155. Digital-video converter 16
0 is controlled by the graphics processor 120 through the video control bus 124. The digital-to-video converter 160 outputs the digital output of the video palette 150 to the video display 17 via the video output 165.
Works to convert to the desired analog level to feed zero. The digital-to-video converter 160 may, for example, specify the number of pixels per horizontal scan line and the number of scan lines per frame, for example, the video control bus 124.
Is controlled by the graphic processor 120. The data in the graphic processor 120 is generated by digitally generating the sync signal, the blanking signal and the blanking signal.
It is controlled through the video converter 160. These portions of the video signal are not specified by the data stored in the video memory 132 and form the control signals necessary to specify the desired video output.

In addition, video display 170 receives the video output from digital-to-video converter 160 on video output line 165. Video display 170 produces a designated video image for viewing by an operator of the graphic computer system. Note that video palette 150, digital-to-video converter 160 and video display 170 operate on the basis of two major video technologies. In the first technique, video data is specified for each pixel in terms of hue and saturation. In the other technique, red, green and blue three primary color levels are specified for each pixel. It is possible to choose which of these major technologies is selected. Video palette 150, digital-to-video converter 160 and video display 170 must be configured to be compatible with this technology. However, the principles of the present invention remain the same with respect to operating the graphics processor 120 regardless of which video technology is selected.

FIG. 2 illustrates the graphics processor 120 in more detail. Graphic processor 1
20 is a central processing unit 200, special graphics hardware 210, an instruction cache 230, a host interface 240, a memory interface 250,
Input / output register 260 and video display controller 270
Is included.

The heart of the graphics processor 120 is the central processing unit 200. The central processing unit 200 has the capacity to perform general data processing, including many arithmetic and logic operations typically included in general purpose central processing units. Further, the central processing unit 200
Stand alone or with special graphics hardware 20
Together with 0, it controls a number of special graphic instructions.

The graphics processor 120 includes a main bus 205, which is connected to most of the graphics processor 120 including the central processing unit 200. The central processing unit 200 includes a set of register files containing a number of data registers,
It is connected in both directions through a bidirectional register bus 202. Register file 220 acts as a repository for available data when used by central processing unit 200. As will be described in more detail below,
Register file 220 contains general purpose registers used by central processing unit 200, as well as a number of data registers used to store implicit operands for graphic instructions.

The central processing unit 200 is connected to the instruction cache 230 through the instruction cache bus 204. The instruction cache 230 further includes the general-purpose bus 20.
5 and is connected to the video memory 130 through the video memory bus 122 and the memory interface 250.
You can also load the instruction word from The purpose of instruction cache 230 is to speed up the performance of certain functions of central processing unit 200. Iterative functions or functions that are frequently used within a particular portion of a program executed by central processing unit 200 may also be stored in instruction cache 230. Accessing the instruction cache 230 through the instruction cache bus 204 is even faster than accessing the video memory 130. Thus, the program executed by central processing unit 200 can be sped up by preloading iterative instructions or a frequently used sequence of instructions into instruction cache 230. If you do this, these instructions can execute faster because they can be fetched faster. The instruction cache 230 need not always contain the same set of instructions, but may load a particular set of instructions that are frequently used within a particular portion of a program executed by the central processing unit 200. it can.

The host interface 240 is connected to the central processing unit 200 through the host interface bus 206. Host interface 24
0 is also connected to the host processing system 110 via the host system bus 115. The host interface 240 acts to control the communication between the host processing system 110 and the host system bus 115. The host interface 240 controls the timing of data transfer between the host processing system 110 and the graphic processor 120. In this regard, the host interface 240 allows the host processing system 110 to interrupt the graphics processor 120, or vice versa. The host interface 240 is also connected to the main bus 205, which allows the host processing system 110 to directly control the data stored in the memory 130. Typically, the host interface 240 communicates graphics requests from the host processing system 110 to the graphics processor 120 to allow the host system to specify the type of display to be emitted by the video display 170, and the graphics processor 120. Lets you perform the desired graphic function.

The central processing unit 200 is connected to special graphics hardware 210 via a graphics hardware bus 208. Special graphics hardware 210 is also connected to the main bus 205. Special graphics hardware 210
Cooperates with the central processing unit 200 to perform special graphics processing operations. Central processing unit 200
In addition to its general purpose data processing capability, it controls the use of special graphics hardware 210 to execute various special graphics instructions. These special graphic instructions relate to manipulating the bit mapped data in video RAM 132. Special graphics hardware 210 is provided for central processing unit 200.
Of the video RAM 132 and enables particularly advantageous data manipulation with respect to the data in the video RAM 132.

The memory interface 250 is connected to the main bus 205, and further, the video memory bus 12 is connected.
It is also connected to 2. Memory interface 250
Operate to control the communication of data and instructions between the graphics processor 120 and the memory 130. The memory 130 contains the bit-mapped data to be displayed through the video display 170, as well as the instructions and data necessary to control the operation of the graphics processor 120. These functions include controlling the timing of memory access and controlling the multiplexer operation of data and memory. In the preferred embodiment, the video memory bus 122 contains multiplexed address and data information. The memory interface 250 is the graphic processor 1
20 to provide the appropriate output to the video memory 122 bus at the appropriate time to access the memory 130.

The graphics processor 120 finally includes an input / output register 260 and a video output controller 2.
70 and. Input / output registers 260 are bidirectionally connected to main bus 205 to allow reading and writing within these registers.
The input / output register 260 is the central processing unit 200.
It is desirable to be within the normal memory space of. Input / output register 260 contains data that specifies control parameters for video output controller 270. The video output controller 270 controls the video control bus 1 to control the digital-to-video converter 160 as desired according to the data stored in the input / output register 260.
Signal to 24. The data in the input / output register 260 includes data for specifying the number of pixels per horizontal scanning line, the number of horizontal scanning lines per frame, and the vertical synchronization blanking signal. The input / output register 260 may also contain data for specifying the type of frame interlace as well as other types of video control functions. Finally, the input / output register 260 is a storage location for other particular types of input and output parameters. The input parameters and output parameters will be described later in detail.

The graphics processor 120 operates on the address memory 130 in two different address modes. These two address modes are the XY address mode and the linear address mode. Because the graphics processor 120 operates on both bitmapped graphics data and regular data and instructions, different parts of the address memory 130 can be addressed most conveniently by different address modes. Regardless of the particular address mode selected, the memory interface 250 will generate the appropriate physical address for the appropriate data to be accessed. In the linear address mode, the starting address of the field is formed by a single multi-bit linear address. The size of the field is defined by the data in the status register of central processing unit 200. In the XY address mode, the start address is a pair of X and Y coordinate values. The size of the field is equal to the size of the pixel, ie the number of bits needed to specify the particular data of a particular pixel.

FIG. 3 shows the structure of pixel data in the XY address mode. Similarly, in FIG.
It shows a structure of similar data in the linear address mode. FIG. 3 shows an origin 310 that serves as a reference point for the XY matrix of pixels. Origin 310 is X
Specified as the Y start address, but need not be the first address location in memory. The location of the data corresponding to the array of pixels, eg, the specifically defined image element, is designated in association with the origin address 310. This includes an X start address 340 and a Y start address 330.
And are included. The X start address 340 and the Y start address 330, together with the origin, indicate the start address of the first pixel data 371 of the particular image desired. The width of the image of a pixel is indicated by the quantity Delta X350. The image height of the pixel is indicated by the quantity delta Y360.
In the example shown in FIG. 3, the images are designated by reference numerals 371-379.
It contains 9 pixels shown by. The last parameter needed to specify the physical address of each of these pixels is the screen pitch 320, which indicates the width of the memory in bits. These parameters, in particular X start address 340, Y start address 330, quantity delta X3
The designation of 50, the amount delta Y 360 and the screen pitch 320 allows the memory interface 250 to have a designated physical address based on a designated XY addressing technique.

Similarly, FIG. 4 shows a linear format memory configuration. A set of fields 441-4
46 is shown in FIG. This set of fields 44
1 to 446 are pixels 371 to 3 shown in FIG.
It may be the same as 76. The following parameters are needed to specify a particular device according to the linear addressing technique. The first parameter is the start address 410, which is the first linear start address of the first field 441 of the desired array. The second parameter is the quantity delta X420 which indicates the length of a particular segment of a multi-bit field. The third parameter is the quantity delta Y (not shown in FIG. 4) that indicates the number of particular segments in a particular array. The final parameter is the linear pitch 430, which indicates the linear start address difference between neighboring array segments. As in the XY address mode, by specifying these linear address parameters,
Allows memory interface 250 to generate the appropriate specific physical address to be designated.

The two addressing modes serve different purposes. The XY address mode is most useful for the portion of the video RAM 132 that contains the bitmap data, called the screen memory. This screen memory is part of the memory that controls the display. The linear addressing mode is most useful for off-screen memory of instructions, image data not currently displayed, etc. This latter type includes various standard symbols used by computer systems such as alphanumeric fonts and images. At times, it is desirable to be able to translate XY addresses into linear addresses. This conversion is performed according to the following formula.

LA = OFF + (Y × SP) + (X × PS) Here, LA is a linear address, and OFF is XY.
The screen offset is a linear address of the origin of the coordinate system, SP is the screen pitch in bits, X is the X address, and PS is the pixel size in bits. Regardless of which address mode is used, the memory 250 issues a physical address suitable for accessing the memory 130.

FIG. 5 illustrates a method of storing pixels in a data word of memory 130. According to the preferred embodiment of the present invention, the memory 130 is organized by 16-bit data words. These 16 bits are schematically represented in FIG. 5 by the 16 digits O through F. In accordance with the preferred embodiment of the present invention, the number of bits per pixel in memory 130 is a power of 2 but does not exceed 16 bits. Because of this limitation, each 16-bit word in memory 130 is
An integer number of such pixels can be included. Figure 5
Is 1 bit, 2 bits, 4 bits, 8 bits and 16
Figure 5 shows five available pixels, each corresponding to a pixel length of bits. The data word 510 is
Sixteen 1-bit pixels 511-526 are shown, which allows 16 1-bit pixels to be placed in each 16-bit data word. Data word 530 includes eight 2-bit pixels 531 to 53 arranged in a 16-bit data word.
8 is shown. Data word 540 illustrates four 4-bit pixels 541-544 arranged in a 16-bit data word. Data word 5
50 shows two 8-bit pixels 551 to 552 arranged in a 16-bit data word. Finally, the data word 560 shows one 16-bit pixel 561 arranged in 16-bit data. Providing each pixel, particularly each pixel arranged on a physical word boundary with an integer number of powers of 2 bits, in this manner enhances pixel manipulability through the graphics processor 120. This is because processing a physical word involves manipulating an integer number of pixels. It will be appreciated that in the portion of the video RAM 132 that specifies the video display, the horizontal scan line for each pixel is assigned by a series of consecutive words as shown in FIG.

FIG. 6 shows the contents of a portion of the register file 220 that stores implicit operands for various graphic instructions. Register 60 shown in FIG.
Each of 1 to 611 is a graphics processor 12
0 in the central processing unit 200 register address space. Note that these register files shown in FIG. 6 are not meant to contain all possible registers in register file 220. In contrast, a typical system includes a number of general purpose unspecified registers that can be employed by central processing unit 200 for various programmed functions.

The register 601 stores the source address. This address is the address in the lower left corner of the source array. The source address is a combination of the XY address 340 and the Y address 330 in the XY address mode, or the linear start address 410 in the linear address mode. Register 602 is
The source pitch, i.e. the difference in linear starting address between adjacent columns of the source array, is stored. The source pitch is the source pitch 340 shown in FIG. 3 or the linear pitch 430 shown in FIG. 4 depending on which of the XY address format and the linear address format is adopted.

Registers 603 and 604 are similar to registers 601 and 602, respectively, except that they contain a leading start address and a leading pitch. The destination start address stored in the register 603 is the address at the lower left corner of the destination array in XY address mode or linear address mode. Similarly, the destination pitch stored in register 604 is the difference in the linear start address between adjacent columns. In other words, the destination pitch will be either the screen pitch 320 or the linear pitch 340 depending on the address mode selected.

The register 605 stores the offset. The offset is a linear bit address corresponding to the origin of the XY address coordinate system. As mentioned above, XY
The address mechanism origin 310 need not be the physical start address of the memory. The offset stored in the register 605 is the linear start address of the origin 310 of this XY coordinate system. This offset is the linear address and X
Used for conversion to and from the Y address.

Registers 606 and 607 store the addresses corresponding to the windows in screen memory. The window start address stored in the register 606 is the address in the lower left corner of the display window. Similarly, register 607 stores the window end, which is the XY address in the upper right corner of this display window. Each address in these two registers is used to demarcate a specified display window. The image in the window in the graphic display can be different from the background image according to known graphic techniques. The window start and window end addresses contained in these registers are used to specify a window range so that the graphics processor 120 can determine whether a particular XY address is inside or outside the window. Used.

Register 608 stores delta Y / delta X data. This register 608 is divided into two independent halves, the upper half (high order bit) specifying the height of the source array (delta Y) and the lower half (low order bit) width of the source array (delta X). Is specified. The Delta Y / Delta X data stored in register 608 can be provided in either XY addressing or linear addressing depending on how the source array is specified. The meaning of the two quantities Delta X and Delta Y has been previously described in both FIGS. 3 and 4.

Registers 609 and 610 each contain pixel data. The color 0 data stored in the register 609 includes the pixel value copied over the entire register corresponding to the first color designation color 0. Similarly, the color 1 data stored in the register 610 contains the pixel value copied over the entire register corresponding to the second color value designated color 1. Certain graphics instructions in the graphics processor 120 use either or both of the above color values to manipulate their data. The use of these registers will be described in detail later.

In addition, the register file 220 includes a register 611 that stores a stack pointer address. The stack pointer address stored in the register 611 is the video R which is the top of the data stack.
Designate the video address in AM132. This value is
The data is arranged to be pushed into or out of the data stack. In this way, the stack pointer address acts to indicate the address of the last input data on the data stack.

FIG. 7 illustrates, in schematic form, the process by which the array moves from off-screen memory to screen memory. FIG. 7 shows a screen memory 705.
Video RAM 1 including off-screen memory 715
32 is shown. In FIG. 7, an array with pixels 780 (more precisely, data corresponding to the array with pixels) is transferred from off-screen memory 715 to screen memory 705 into an array with pixels 790.

Prior to performing an array move operation, certain data must be stored in a designated register in register file 220. Register 601 must be loaded with the starting address 710 of the source array of pixels. In the example shown in FIG. 7, this load is designated in the linear address mode. The source pitch 720 is
It is stored in the register 602. The destination address is loaded into the register 603. In the example shown in FIG. 7, this load is specified in the XY address mode including the X address 730 and the Y address 770. The register 604 has a destination pitch 645, and the destination pitch 645 is stored inside the register 604. The linear address of the origin of the XY coordinate system and the offset address 770 are
It is stored in the register 605. Finally, Delta Y750
And Delta X 760 are stored in separate halves of register 608.

The array move operation illustrated schematically in FIG. 7 is performed with respect to the data stored in each register of register file 220. According to the preferred embodiment, the number of bits per pixel is chosen such that an integer number of pixels are stored in a single physical data word. This selection also allows the graphics processor to transfer an array of pixels 780 to an array of pixels 790, primarily by transferring the entire data word. Thus, even if the number of bits per pixel is selected in relation to the number of bits of the physical data word, in some cases it is necessary to handle partial words at the array boundaries. However, this design choice serves to minimize the need to access and transfer partial data words.

In accordance with the preferred embodiment of the present invention, the transfer of data shown schematically in FIG. 7 is a special case where a number of different data are transformed. Pixel data from each corresponding access location of the source and destination images are combined in the manner specified by the instruction. The combination of data may be a logical operation (eg AND or OR) or an arithmetic operation (eg addition or subtraction). The new data thus stored in the array of pixels 790 is the same as the data in the array of pixels 780
Both functions of the 90 current data. The data transfer shown in FIG. 7 is a special case of a more general variant,
In this case, the data finally stored in the destination array does not depend on the data previously stored there.

This process is shown in the flow chart of FIG. According to the preferred embodiment, the transfer is done sequentially by physical data. Once the process begins (start block 801), the data stored in register 601 is read to obtain the source address (processing block 802). Next, the graphics processor 120 retrieves the display data word corresponding to the display source address from the memory 130 (processing block 803). If the source address is specified in XY format, recalling this data includes converting the XY address to the corresponding physical address. A similar process is performed for the data contained in the destination location by recalling the destination address from register 603 (processing block 804) and then retrieving the displayed physical data word (processing block 805).

This combined data is then returned to its previously defined destination location (processing block 80).
6). The source and destination pixel data are then combined according to the combination mode performed. This bond is
It is done on a pixel by pixel basis even if the physical data word contains data corresponding to more than one pixel. This combined data is then written to the specified destination location (processing block 807).

The graphics processor 120 determines whether the entire data transfer has occurred by detecting whether the last data has been transferred with respect to the delta Y / delta X information stored in the register 608 ( Decision block 808). If the entire data transfer has not been performed, the source address is updated.
The source address stored in register 601 is associated with the source address previously stored in register 601 and the source pitch data stored in register 602 to reference the next data word to be transferred. It is updated (processing block 809). Similarly, register 6
The destination address stored in 03 is stored in the register 604.
Updated to reference the next data word of the destination in relation to the destination pitch data stored at (processing block 810). This process is repeated with the new source stored in register 601 and the new destination data stored in register 603.

As mentioned above, the delta Y / delta X data stored in register 608 is used to define the limit of the image to be transferred. The entire image is stored in register 608 as described above Delta Y / Delta X
Transferred while referring to data (decision block 8)
08), the execution of the instruction is complete (end block 8
11), the graphic processor 120 continues to operate by executing the instructions of the program. As mentioned above, in the preferred embodiment, the process shown in FIG. 8 is implemented in instruction microcode. The entire data transformation process, referred to as array move, is performed in response to a single instruction to graphics processor 120.

FIG. 9 shows some of the input / output registers 260 of the present invention. The input / output register 260 includes registers 901 to 910 dedicated to storing information regarding input / output control. The register 901 stores the display start address.
The register 902 stores the display refresh address. Register 903 stores the display address increment.
These three registers work together to make a video RAM 132.
Controls which part of the video display is specified. Register 90
The display start address stored in 1 is the video RAM.
This is the start address in 132, and the memory specifies the start of video display in this video RAM 132. At the beginning of each new display frame, the data in register 901 is loaded into register 902 to define the display refresh address. The display refresh address stores the portion of video RAM 132 to be read next that is needed to define the video display. This address is generally the start address of the scan line for video scanning. During each horizontal blanking period, the data corresponding to the increment of the display address stored in register 903 is added to the data stored in register 902, thereby forming the display refresh address. This process continues until register 902 is reloaded with the display start address from register 901 until the end of this particular video frame. The hardware for issuing the horizontal reset signal and the vertical reset signal is shown in FIG.

Register 90 of input / output register 260
4 stores the video RAM refresh address.
In a typical system, such as the system shown in FIG. 1, video RAM 132 is comprised of dynamic random access memory. This memory is mostly refreshed periodically to retain the stored information. Video R stored in register 904
The AM refresh address is a column address to be refreshed next. This column address is applied to the video RAM 132 along with the refresh signal according to a known principle, thereby refreshing all the selected rows. Once this work is done, register 90
The data in 4 is then incremented to the next column. In this way, the video RAM refresh address corresponds to the address to be refreshed next. The hardware for issuing a dynamic random access memory refresh request is shown in FIG.

Registers 905, 906, 907, 908
And 909, the host processing system 110 has a memory 13
Allows direct access to 0. This is accomplished by providing register 905 with host data, register 906 with the host's least significant data, and register 907 with the host's most significant data. These three registers serve to allow the host processing system 110 to write to or read from the memory 130 through the memory interface 250. This is accomplished by the control signals from the host processing system 110 and the data stored in registers 908 and 909. These registers 908 and 909 store the least significant control bit of the host and the most significant control bit of the host, respectively. In the preferred embodiment, these two registers are 8 bits wide, while the other register 260 is 16 bits wide. Having these two 8-bit wide registers allows the host processing system 110, which acts as an 8-bit external bus, to directly read or write to each of these registers in a single memory cycle. on the other hand,
Since the graphics processor 120 has a 16-bit wide external bus, these two registers can be read or written in a single memory cycle.

FIG. 10 shows the host's most significant control bit 90.
9 shows the contents of the host control register 1000 corresponding to the combination of 9 and the least significant control bit 908 of the host. The host control register 1000 includes a number of sub-portions that allow communication between the host processing system 110 and the graphics processor 120. Message input portion 1001 enables host processing system 110 to send a message to graphics processor 120. This message input portion 1001 is used with the interrupt input bit 1002. This interrupt input bit 1002 allows the host processing system 110 to interrupt the operation of the graphics processor 120 in response to certain requests from the host processing system 110.
Similarly, message output portion 1003 enables graphics processor 120 to send a message to host processing system 110. Combined with this message output portion 1003 is an interrupt output bit 1004.
Is. This interrupt output bit 1004 allows the graphics processor 120 to interrupt the operation of the host processing system 110 in response to a request for some priority operation. Portions 1005 and 1006 are used while host processing system 110 is performing read and write operations on memory 130. If the incremental write bit 1005 is set, the address formed by the host's lowest control word address 906 and the host's highest word address 907 is incremented each time a read operation is performed by the host processing system 110. It If the incremental write bit 1005 is not set, then these address registers are not incremented during a write operation. Similarly, incremental write bit 10
If 06 is set, the host's lowest control word address 906 and the host's highest word address 90
The address formed by 7 and 7 is incremented each time a read operation is performed by the host processing system 110. Conversely, if the incremental write bit 1006 is not set, then the above increments are not performed during a read operation. The ability to perform such automatic incremental read and write operations results in host processing system 11
A 0 can read from or write to a memory block in memory 130 without having to continuously supply the next address.

By the cache flush bit 1007 and the stop bit 1008, the host processing system 100
It is possible to additionally control the graphic processor 120 through. Cash flush bit 100
If 7 is set, the graphics processor 12
0 immediately erases all data stored in the instruction cache 230. This function is performed by the host processing system 110 in the memory 130 by the graphic processor 1.
Most useful when loading an instruction block for 20. Flushing the instruction cache in this manner ensures that the graphics processor 120 does not perform old instructions previously stored in the instruction cache 230, but reads updated instructions from the memory 130. If the stop bit 1008 is set, the graphics processor 120 will be stopped until this bit is reset. This operation is useful for halting all operations of graphics processor 120 while host processing system 110 is defining a set of new operations for graphics processor 120. Thus, for example, the host processing system 110 can redefine the instructions and data used by the graphics processor 120, and to avoid spurious responses during this operation, the graphics processor 1
20 is stopped. According to a preferred embodiment of the present invention,
The above video update operation and memory refresh operation are continued even when the graphic processor 120 is stopped. This saves the current display and memory data during the stop interval.

The last register shown in FIG. 9 is the control register 910. The control register 910 stores data used for controlling the internal operation of the graphic processor 120. Most relevant to the present invention is the refresh rate unit 911. Refresh speed section 911
Is 2 bits, and these 2 bits are the video RAM 13.
2 defines the refresh rate of the dynamic random access memory forming 2. Table 1 shows a preferred embodiment of the refresh speed unit 911. Note that the dynamic random access memory can be updated every 32 or 64 instruction cycles of the graphics processor 120, or the refresh can be deferred depending on the state of this bit. The particular refresh rate is selected depending on the application to which the graphic processor 120 will be applied. However, in order to ensure the integrity of the data stored in memory 130, the refresh rate should not be set above a certain short time.

Table 1 RR Bits Refresh Rate 0 0 32 Clock Cycles 0 1 64 Clock Cycles 1 0 Unused 1 1 No DRAM Refresh FIG. 11 shows the various fields of the status register 1100. The status register 1100 stores various instructions regarding the operation of the graphics processor 120.
Bits 1101, 1102, 1103 and 1104 are
It is set or reset based on the result of the operation by the central processing unit 200. If the output of the operation of the central processing unit 200 is negative, a negative bit 1101
Is set, otherwise this bit is reset. If the operation of central processing unit 200 produces a carry output, then carry bit 1102 is set, otherwise this bit is reset. Similarly, a zero output indication is formed via zero bit 1103, and an overflow output indication is overflow bit 1104.
Formed by. These bits of status register 1100 are automatically set based on the operation of central processing unit 200.

The other parts of the status register 1100 shown in FIG. 11 are more relevant to the operation of the present invention.
These parts can be set by the central processing unit 200 and define two sets of separate field sizes and field expansion options. The field size 0 portion 1105 is 5 bits which indicates the length of the field acted upon by the central processing unit 200. In accordance with the preferred environment of the present invention, central processing unit 200 operates on 32 bits simultaneously. The graphics processor 120 may operate on a field size of 1 to 32 bits based on the field size set in the field size 0 portion 1105. A similar field size 1 portion 1107 of 5 bits indicates a second field size. The instructions of central processing unit 200, which is capable of operating with variable field sizes, cause status register 1100 to indicate the length of the selected field size.
Field size 0 portion 1105 or field size 1 portion 1107. Field extension 0 bit 1106 and field extension 1 bit 1108 indicate the sign extension option for each field size. If the field size acted upon by the central processing unit 200 is smaller than 32 bits, the remaining bits must be filled in some way. Each field extension 0 bit 1106
Or, when the field extension 1 bit 1108 is "0", these remaining portions of the central processing unit 200 32-bit word are filled with 0s. On the other hand, if this bit is "1", the number of codes operated by the central processing unit 200 is expanded. In this regard, these additional field extension bits are set to "0" if the number is positive. If this number is negative, these additional field extension bits are set to "1". This corresponds to the use of 2's complement arithmetic to represent negative numbers. The operation of the selected field size and field expansion will be described in detail below with reference to the accompanying drawings.

FIG. 12 shows the address register 1200. In the preferred embodiment, the address register 12
00 is 32 bits long, which is the same as the length of the data word used by the central processing unit 200. In the preferred embodiment, for variable field size selection, the address register 1200 specifies a particular bit within the memory 130 rather than a more general word specification. Therefore, the address register 1200
Includes a 4-bit bit address portion 1201 and a 28-bit word address portion 1202. Word address portion 1202, in the preferred embodiment, points to an individual 16-bit word in memory 130. Bit address 1201 specifies a particular bit within the selected word. Graphic processor 120
The address sent from the to the memory 130 includes only the word address 1202. Bit address 1201
Are used within the graphics processor 120 to select the desired bits.

FIG. 13 illustrates various cases of the relationship between a particular word boundary in memory 130 and a selected field size. In accordance with the preferred embodiment of the present invention, the graphics processor 120 stores a field size of selected width from 1 bit to 32 bits in the memory 13.
You can write to 0 and read from here. Further, in the preferred embodiment of the present invention, the memory 130
Are organized into 16-bit words. FIG. 13 shows each possible case of the 16-bit word of the memory 130 and the relation between the selected field size and the start of that field.

FIGS. 13A-13D show the case where one word access is sufficient to access all designated fields. FIG. 13A is the simplest case. In FIG. 13A, a 16-bit field that exactly matches the 16-bit word N of memory 130 is designated. In the case shown in FIG. 13A, a read of a single data word N is required for read field operation. The operation of the write field likewise involves writing a single memory word N.

The case shown in FIGS. 13B-13D is when the specified field is entirely within a single data word N of memory 130 but does not exactly match this data word N. is there. FIG. 13B illustrates the case where the least significant bit of the designated field does not match the start of data word N, but the most significant bit of the designated field matches the most significant bit of data word N. Similarly, FIG. 13C shows that the least significant bit of the data field is aligned with the least significant bit of memory word N,
The most significant bit shows the case that it is not aligned. Further, FIG. 13D illustrates the case where the field is completely contained within the data word N without being aligned with the least significant bit or the most significant bit.

In each case of FIGS. 13B-13D, when reading a specified field, only a single data word N is read from memory 130 and bits not contained within this specified field are masked. Is needed. Meanwhile, FIGS. 13B to 13D
A compound operation is required to write a field as shown in. First of all, the data word N must be retrieved from the memory 130 and then the bit corresponding to the specified field must be changed without changing the other bits of the data word N. Finally, this modified data word is written into memory 130 at the same location as data word N. This combination of operations is called a read / modify / write operation.

FIGS. 13E through 13H show an example where two consecutive data words in memory 130 must be accessed when accessing a specified field. FIG. 13E shows the simplest example of these cases. In FIG. 13E, a 32-bit field is designated that corresponds exactly to a pair of consecutive data words (data word N and data word N + 1) in memory 130. When reading a field as shown in Figure 13E, two consecutive read operations are required. Similarly, when writing a field as shown in FIG. 13E, two consecutive full word write operations are required.

13F to 13H show the case where the designated field intersects one data word boundary. In FIG. 13F, the designated field begins at some position within data word N and ends at the end of data word N + 1. When reading such a data field, two consecutive read operations must be performed with a corresponding mask applied to the first read operation in order to remove bits not included in the designated field. When writing such a field, a read / modify / write operation must be performed on data word N and a simple write operation on data word N + 1. FIG. 13G illustrates the case where the designated field starts at the least significant bit of data word N and ends somewhere within the next data word N + 1. When reading such a data field, it is necessary to perform two consecutive read operations with corresponding masking. When writing such a data field, one write operation is performed on the data word N and the data word N + 1.
It is necessary to perform read / modify / write operations on the. FIG. 13H illustrates the case where the data field starts within data word N, crosses word boundaries, and ends at data word N + 1. Reading such a data field requires two successive read operations with corresponding masking. When writing such a data field, data word N and data word N +
It is necessary to perform two consecutive read / modify / write operations for one.

FIG. 13I shows the simplest case of a field associated with a word boundary according to the preferred embodiment of the present invention. In FIG. 13I, the designated field is
Starting with N data words N, crossing two consecutive data word boundaries and ending somewhere within data word N + 2. When reading such a data field, it is necessary to perform three consecutive memory read operations with corresponding masking to remove bits of data word N and data word N + 2 that do not exist in the designated data field. Is. When writing such a data field, a read / modify / write operation is performed on the data word N, a write is performed on the data word N + 1 and a data word N +
It is necessary to perform read / modify / write operations based on 2.

FIG. 14 shows a memory interface 250.
And the memory 130 through the central processing unit 200 with a specified field size to allow access to the memory 130 based on the hardware within and a set of priorities.
0 and another part of the graphics processor 120 which makes it possible to access 0. FIG. 14 shows a plurality of registers 90 that are part of the input / output register 260.
2, 904, 906/907 and 905 are shown.
Further, FIG. 13 shows the address register 1200 of the central processing unit. Each of these registers has a memory interface 250 for connection to the bus 122.
Connected to. Also connected to the memory interface 250 is a data latch, which includes a central processing unit most significant bit data latch 1440 and a central processing unit least significant bit data latch 1445.

The operation of memory interface 250 is controlled by sequencer 1400. Sequencer 1400 receives various input control and data signals. The control signals are the display refresh request appearing on input 1401, the DRAM refresh request appearing on line 1402, the host access request appearing on line 1403, the host read / write control appearing on line 1404, and the central processing unit appearing on line 1405. It includes access requests and read / write control of the central processing unit appearing on line 1406.

Sequencer 1400 receives data signals from multiple sources. First, the bit address 1201 from the address register 1200 of the central processing unit is supplied to the zero detector 1420. Bit address 12
The 01 bit is sent to the sequencer 14 via line 1407.
00 is supplied. The zero detect signal from zero detector 1420 is provided to sequencer 1400 via line 1408. The bit address from the bit address register 1201 is also sent to the adder 1418. Adder 1
418 receives the field size from bus 1417. The field size is sent from the status register 1100, as described above. Either field size 1105 or field size 1107 is selected by the particular instruction executed by central processing unit 200. With this selection, a 5-bit field size is sent to adder 1418 via bus 1417. The output of adder 1418 is a 6-bit quantity stored in latch 1419. The four least significant bits (designated bits 0 through 3) are sent to the zero detector 1421. These four least significant bits are sent to sequencer 1400 via bus 1411. The zero indication signal is on line 1412.
And is sent to the sequencer 1400. Latch 1419
The two most significant bits of (indicated as bits 5 and 4) are sent to the sequencer on lines 1409 and 1410, respectively. The sequencer 1400 outputs the outputs 1413 and 141.
4, 1415 and 1416 are generated. The control configuration of these outputs will be described below.

The multiplexer 1430 is connected to the memory bus 1
Controls the specific data sent to 22. Multiplexer 1430 is connected to register 904 to receive the display refresh address via bus 1431.
Similarly, multiplexer 1430 receives the composite host address from registers 906 and 907 via bus 1433. Register 905 containing host data is bidirectionally connected to multiplexer 1430 via bus 1434. The word address portion 1202 of central processing unit address register 1200 is provided to multiplexer 1430 via bus 1435. Bus 1436 bidirectionally connects multiplexer 1430 to right mask 1437, left mask 1438, input / output latch 1439,
Then, it is connected to the central processing unit 200 via the bus 205. The right mask 1437 is controlled from the sequencer 1400 via line 1413. Similarly, the left mask 14
38 is controlled by sequencer 1400 via line 1414. The right mask 1437 is the multiplexer 1
Input / output latch 143 from 430 via bus 1436
9 acts to mask the least significant bit portion of the data sent to 9. Similarly, the left mask 1438 acts to mask the most significant bits of this data transfer.

The central processing unit comprises a central processing unit most significant bit data latch 1440 and a central processing unit least significant bit data latch 1445.
These are input / output latches 1439 via bus 205.
Is connected in both directions. Line 1415 from sequencer 1400 determines whether the data transfer originates from most significant bit 1440 or least significant bit 1445. Central processing unit 200 further includes a barrel shifter 1450 bidirectionally connected to two portions of central processing unit data latches 1440 and 1445.
Barrel shifter 1450 shifts the data received from the combination of central processing unit most significant bit data latch 1440 and central processing unit least significant bit data latch 1445 as specified by central processing unit 200. Barrel shifter 1450 is controlled by field code / zero extend controller 1451.
As described with respect to FIG. 11, field extension 0 bit 1106 or field extension 1 bit 1108 specify whether the field is an extended code or an extended zero. One of these two bits of the status register 1100 is selected by the extended specific instruction. This control is sent to the barrel shifter 1450 and used as described below. Barrel shifter 1450
It is connected to other parts of the central processing unit 200 via the bus 1455.

The general operation of the memory controller 250 is described below with respect to FIG. Based on the particular control and data signals received by the sequencer 1400,
The sequencer 1400 has a memory 130 via the bus 122.
1 sent to multiplexer 1430 for feeding to
Choose one source. Therefore, for example, the sequencer 1
400 includes a multiplexer 1430 and a register 902.
The display refresh address stored in
Enables connection to memory in response to 01 display refresh request. Similarly, DRAM on line 1402
The refresh request causes the sequencer 1400 to control the multiplexer 1430 to provide the video RAM refresh address stored in the register 904 to the memory 132. With the host access request appearing on line 1403 and the host read / write control signal appearing on line 1404, sequencer 1400
The multiplexer 1430 is controlled to control both registers 906.
And 907 to provide the host address stored in the memory 130 via the bus 122 and to exchange data between the memory and the register 905 based on the selected operation. In addition, line 1405
In response to the central processing unit access request appearing on line 1406 and the central processing unit read / write control signal appearing on line 1406, sequencer 1400 causes central processing unit address register 1200 subpart 12
The word address of the central processing unit stored in 02 can be connected to the memory 130 via the multiplexer 1430. Then, based on the read or write operation selected by the read / write control signal of the central processing unit appearing at input 1406, the memory 1
Data is exchanged between 30 and the central processing unit via bus 1436. In this case, this data is sent from the sequencer 1400 to control lines 1413 and 1414.
The right mask 143 based on the control signals sent via
7 and the left mask 1438. This data is then exchanged with data from the least significant bit data latch 1445 of the central processing unit and the most significant bit data latch 1440 of the central processing unit, as described in detail below.

FIG. 15 shows the display request signal on line 1401.
2 shows a structure for generating horizontal and vertical reset signals that can be generated at the same time. The structure shown in FIG. 15 is part of a video display controller 270 that controls the formation of the video display by video display 170. A video clock at the dot rate, ie the pixel display rate at the video display 170, is received at the input 1501. This video clock uses the counter 151
Sent to count input of 0. Comparator 1520 receives the count of counter 1510 and compares it with the count stored in register 1530 corresponding to the total number of pixels or pixel equalizations in a horizontal line.
If these two counts are equal, the comparator 152
0 indicates the output corresponding to the horizontal reset signal on the line 1502.
Occurs in. This output is sent to the reset input of counter 1510 to reset it and start counting for the next line. Horizontal reset signal 1
502 is a signal that enables the display refresh request 1401 to be supplied to the sequencer 1400.

The horizontal reset 1502 generated by the comparator 1520 is supplied to the second counter 1540. The counter 1540 counts the horizontal reset signal and supplies this count to the comparator 1550. Comparator 1550 also receives a count from register 1506, which stores the total number of lines or line equalizations per vertical frame. Comparator 1550 produces an output signal on line 1503 corresponding to a vertical reset when these two counts are equal. This vertical reset signal is sent to the reset input of the counter 1540 to reset this counter. When the vertical reset signal 1503 is generated, the start point of the display address stored in the register 901 is stored in the register 902, and the display refresh address is reset to the start point of a new video frame.

FIG. 16 shows the input 14 of the sequencer 1400.
2 shows a structure for generating a DRAM refresh request signal sent to the H.02. The central processing unit clock signal is received at input 1601. The central processing unit clock signal is the clock signal that operates the central processing unit 200 to control its operating speed. This signal is sent to programmable divider 1610.
Programmable divider 1610 has line 1602
A control signal is also supplied via. This control signal is high speed /
Received from the slow decoder 1620. The fast / slow decoder 1620 is part of the control bit register 910 and operates on the refresh rate bits 911. As mentioned above, according to the preferred embodiment, this bit indicates whether the dynamic random access memory is refreshed once every 32 central processing unit cycles or once every 64 cycles. Alternatively, it indicates whether the refresh signal of the dynamic random access memory is not generated. According to the refresh rate bit 911 of the control register 910, the fast / slow decoder 1620 generates a signal to the programmable divider 1610. Programmable divider 1610 receives this control signal and generates a dynamic random access memory refresh request signal at output 1603 at a selected rate. It is fed to the input 1402 of the sequencer 1400 to issue a refresh request for the dynamic random access memory.

FIG. 17 is a detailed block diagram of the sequencer 1400. The sequencer 1400 comprises a set of latches 1700, a programmable input address logic array 1710, an address register 1720, a control read only memory 1730 and a microsequencer 1740. Various request signals are sent to individual latches within the set of latches 1700. The signals in these latches are sent to a programmable input address logic array 1710, which generates the input address for supply to the control read only memory 1730. The derived input address is stored in the address register 1720.
Once this input address is generated, the control read-only memory 1730 causes the microsequencer 1740 to generate the various output signals of the sequencer 1400.
Control the behavior of.

Latch 1700 is for storing various request and control signals provided to sequencer 1400.
It has a set of latches. The latch 1700 includes a display request latch 1701 that receives a display refresh signal. The DRAM refresh request latch 1702 is
Receive the DRAM refresh request signal on line 1400. Host request latch 1703 receives the host request signal on line 1403. Host read / write control latch 1704 receives the host read / write control signal on line 1404. The third request latch 1705 of the central processing unit is controlled by the microsequencer 1740 as described in detail below.
It is set after 743. Similarly, the second request latch 1706 of the central processing unit is the microsequencer 1
740. First of the central processing unit
The request latch 1707 of FIG. 1 receives the central processing unit request signal appearing on line 1405. In addition, the central processing unit read / write latch 1708 receives the central processing unit read / write control signal appearing on line 1406.

Programmable input address logic array 1710 receives signals from each of latches 1700. In addition, programmable input address logic array 1
710 is a control signal 1 from the microsequencer 1740.
Receive 742. This control signal primarily indicates whether the microsequencer 1740 is committed to serving the current memory access request. An address designating an input point in the control read only memory 1730 is generated based on the signal sent to the programmable input address logic array 1710. This address is sent to the address register 1720 and stored there.

Address register 1720, control read only memory 1730 and micro sequencer 1740
Constitute a programmable controller. The input point selected in the control read-only memory 1730 by the programmable input point logic array 1710 is the starting point of a subroutine for responding to the corresponding memory access request. The instructions of these subroutines stored in the control read-only memory 1730 are stored in the micro sequencer 174.
0 sequentially, the microsequencer performs various output operations based on these instructions appearing on lines 1413, 1414, 1415 and 1416. In this regard, the microsequencer 17 is executed each time a normal instruction is executed so that the next instruction can be called.
40 through line 1741 to address register 172
An increment signal is provided to zero. In addition to the outputs described above, the microsequencer 1740 produces a control output to the latch 1700 via line 1743. This control output is associated with setting and resetting the various latches within latch 1700. In addition, the microsequencer 1740
A host read / write control signal is received via line 1404 and a central processing unit read / write control signal is received via line 1406. A general overview of a specific control subroutine within the control read-only memory 1730 is shown in FIGS. 18, 19, 20 and 2.
1 will be described in detail below.

FIG. 18 illustrates Program 18 which details the operation of programmable input address logic array 1710.
It is a figure of 00. In particular, program 1800 illustrates the priority of operations in determining the input point address by programmable input address logic array 1710. In the preferred embodiment, an input address logic array 171 programmable to perform the functions shown in FIG.
Although a special hardware logic is used for 0, a program for performing this same function can be provided in the control read only memory 1730.

The program 18 constitutes a continuous loop in which memory access requests are processed in priority order.
If the microsequencer 1740 is not idle during the previous cycle, the program 1800
Determines whether the received request is a display refresh request (decision block 1801). In such a case, the display refresh request is processed (processing block 1802). This is accomplished by generating a starting address in control read-only memory 1730 that contains a subroutine for refreshing the display. As mentioned above, the display refresh is
This includes calling the data to be displayed next from the video RAM 132 and updating the display refresh address stored in the register 902 by the display address increment stored in the register 903. When a new frame starts, this includes loading the start point of the display address stored in the register 901 into the register 902 and resetting the display refresh address. This process is well known in the art and will not be discussed further here.

If the pending request is not a display refresh request, process 1800 tests to determine if the pending request is a DRAM refresh request (decision block 1803). If the pending request is such a DRAM refresh request, then the DRAM refresh request is processed (processing block 1804). This DRAM refresh request is processed as described above for the display refresh request. The programmable input address logic array 1710 is
A start address of a subroutine in the control read-only memory 1730 including a program for controlling the micro sequencer 1740 to execute the RAM refresh request is generated. This process is general
No further explanation will be given. After this refresh request has been processed, program 1800 proceeds to processing block 180.
Return to the test at 1 to determine if the display refresh request is the highest priority operation.

DRAM is pending request
If it is not a refresh request, the program 1800
Checks to determine if the pending request is a host memory access request (decision block 1805). If the pending request is a host memory access request, then the request is processed (processing block 1806). This host memory access request is processed as described above by the input of the subroutine in the control read only memory 1730. When this host memory access request is processed, program 1800 returns to the test at decision block 1801 to determine if display refresh is the highest priority access.

Program 1800 tests to determine if the pending request is a third access request of the central processing unit (decision block 1807). As shown in FIG. 13I, a field access request from central processing unit 200 can request execution of three consecutive memory word accesses. When the second access request of the central processing unit is processed and the third access request of the central processing unit is required, the microsequencer 1740 generates a control signal on line 1743 to cause the third access of the central processing unit to be completed.
The request latch 1705 is set. In such a case, the third access request of the central processing unit is processed (processing block 1808). This process is described in detail below in connection with program 2100 shown in FIG.

If the pending request is not the central processing unit's third access request, the program 1800 tests to determine if this is the central processing unit's second access request (decision). Block 1809). Referring again to FIG. 13, as is apparent from FIGS. 13E-13I, in many cases where a field access by central processing unit 200 requires two (or more) consecutive memory word accesses. There is. If it is determined that the first access request of the central processing unit is processed and the second access request of the central processing unit is needed, the microsequencer 1740 generates a control signal on line 1743, The second request latch 1706 of the processing unit is set. In this case, this second access request of the central processing unit is processed (processing block 1810). This process is described in detail below for the program 2000 shown in FIG. Once this access request has been processed, as before, program 1800 returns to decision block 1801 to determine if a display refresh request has been issued.

In order to give the central processing unit access request a first priority when another memory access request is not pending, the program 1800
Performs a test to determine if there is a pending access request other than the central processing unit first access request (decision block 1811). If another access request is pending, program flow returns to decision block 1801 to test for a higher priority memory access request. However, if there are no other pending access requests, then program 1800 tests to determine if this is the central processing unit's first access request (decision block 1812). When central processing unit 200 attempts to access memory 130, it issues this request to sequencer 1400 via line 1405. Issuing such a request is the first access request of the central processing unit.
If no such central processing unit access request is issued, the program 1800 returns to the test if another higher priority access request is pending (decision block 181).
1). This sequence is kept in this loop,
If a higher priority request is issued, then in decision block 1811 the program flow is directed to decision block 1801 to test and process the request, or alternatively to the first of the central processing units. If an access request was issued, it is processed (processing block 1813).

This priority technique serves to control the order of memory accesses when two or more memory access requests are pending at the same time. If two or more memory access requests are pending at the same time, they are executed in priority order. In this case, the display refresh request has the highest priority, and then the DRA
M refresh request, host access request, central processing unit third access request, central processing unit second
Access request, and finally, the first access request of the central processing unit. By giving progressively higher and different priorities to successive access requests of the central processing unit, two results are obtained. First of all, the multi-word access request of the central processing unit is partially completed and then interrupted by the higher priority request. Moreover, since the multi-word access requests of such a central processing unit will be given progressively higher priorities to successive word accesses, the central processing unit will not be able to process such individual multi-word access until another individual central processing unit access can be processed. You have to wait for access to complete. This prevents the two access requests of the central processing unit from interfering. Decision block 18
The loop including 11 and 1812 ensures that the first access request of the central processing unit has the highest priority if no other access request is pending, but other memory access requests are pending. If so, have the lowest priority.

As noted above, the process shown in FIG. 18 is preferably performed using programmable input address logic array 1710, rather than by a program being executed by a processor. Programmable input address logic array 1710 generates the start address of the program sequence in control read-only memory 1730 to process the display refresh request when display request latch 1701 is set. If the DRAM refresh request latch 1702 is set when there is no display refresh request, the programmable input address logic array 1710 will generate a starting address in the control read only memory 1730 to satisfy the ERAM refresh request. Similarly, programmable input address logic array 1710 is configured to control the start address in control read only memory 1730 to perform operations based on the priorities described above with respect to FIG. 18 when any of request latches 1700 are set. To occur.

FIG. 19 shows a program 1900 for processing the first access request of the central processing unit. This program 1900 corresponds to the processing block 1813 shown in FIG.
730 is one of a set of memory accesses to process the subroutine stored in 730. Upon entering the program (start block 1901), the program first tests (decision block 1902) to determine if the access request is a read access. This decision is made based on the state of the central processing unit read / write signal sent to the sequencer 1400 via line 1406. If the memory access request requires a read of memory, then the memory is read (processing block 1903). This is done by sending the address stored in the address register 1202 of the central processing unit to the memory 130 via the multiplexer 1430 along with the memory read signal. The data word stored in this memory location is then loaded into the input / output latch 1439. Right mask 1437 and left mask 1438 have no effect on this data transfer. This data is then loaded into the least significant bit data latch 1445 of the central processing unit (processing block 1904). Memory data that is not present in the desired data field is removed at barrel shifter 1450, as described below. The program then proceeds to decision block 1914 where it is tested whether a second access request of the central processing unit is needed.

If the central processing unit access request is a write request and not a read request, program 1900 tests to determine if the bit address is zero (decision block 1905). This test is simply done by the zero detect circuit 1420. This circuit receives the bit address and produces a signal on line 1408 indicating whether the bit address is zero. If the bit address is zero, the desired data field starts at a memory word boundary. This corresponds to the case shown in FIGS. 13A, 13C, 13E and 13G. If the bit address is zero, program 1900 tests to determine if the sum of the bit address and field size is greater than or equal to 16 (decision block 1906). The sum of the bit address and field size formed by the adder 1418 is the line 14
09 and 1410 and the bus 1411 and the sequencer 1
Sent to 400. Furthermore, the zero detection circuit 1421 gives an indication as to whether the least significant 4 bits (bits 0-3) of this sum are zero. This sum is either bit 5 of line 1409 is "1" or bit 4 of line 1410.
Is '1' and bits 0-3 are non-zero, as indicated by line 1412, then greater than 16. If this is the case and corresponds to the case of FIGS. 13A, 13E and 13G, the first central processing unit
Access request is a simple write operation. input/
The output latch is loaded from the least significant bit data latch 1445 of the central processing unit (processing block 190).
7). The program then writes the data in the input / output latch to the memory pointed to by the word address of the central processing unit stored in register 1202 (processing block 1913). As mentioned above, the program 19
00 performs a test to determine if a second access of the central processing unit is required (decision block 19).
14).

If the bit address is not zero, program 1900 sets right mask 1427 corresponding to the bit address. Bit address is bus 14
It is sent to the sequencer 1400 via 07. If the bit address is non-zero, or if the bit address is zero and the sum of the bit address and the field size is either 16 or 32, the program 1900 sets the bit address and field size A test is made to determine if the sum of the two is greater than 16 (decision block 1909). If the sum is less than 16, then the left mask is set based on the sum, regardless of whether the bit address is zero or nonzero (processing block 1910). If not, the left mask is not needed because the field extends to or beyond the memory word boundary. In any case, the input / output latch 1439 is loaded from the least significant bit data latch 1445 of the central processing unit (processing block 1911). The memory word pointed to by the central processing unit word address stored in register 1202 is read and used with right mask 1437 and left mask 1438 to input / output latch 1439.
Modify the data within (processing block 1912). This process ensures that the parts of the memory word that are not within the selected data field are unchanged, while
Allows a portion of the memory word within the selected data field to be replaced by the data previously loaded from the central processing unit data latch. The data thus modified is written to the same memory location (processing block 1913).

Program 1900 ends by testing whether a second access of the central processing unit is required. This is determined by checking if the sum of the bit address and field size is greater than 16. (Decision Block 191
4). If this sum is greater than 16, then a second access is required. This is indicated by setting the second access request latch 1706 of the central processing unit (processing block 1915). This is signaled from the microsequencer 1740 via line 1743 to the request latch 1700. In any case, the first request latch of the central processing unit is reset (processing block 1916) indicating that the request has been processed. The program 1900 then ends (end block 1917). As mentioned above, the program 1900
This is equivalent to the processing block 1813 shown in FIG.

FIG. 20 shows a program 2000 for processing the second access request of the central processing unit.
This program 2000 corresponds to the processing block 1810 shown in FIG. 18, which is one of a set of memory accesses for processing a subroutine stored in the control read only memory 1730. The start of this program is
It is the same as the program 1900 shown in FIG. Note that the central processing unit word address stored in register 1202 must be incremented to reference the correct memory data word on the second access of the central processing unit. Since the address stored in the address register 1200 of the central processing unit contains the bit address 1201, the number 16 must be added to the address register 1200 to reference the next memory word.

When entering this program (start block 2001), a test is first performed to determine if the access request is a read access (decision block 2002). This decision is made based on the state of the central processing unit read / write signal provided to sequencer 1400 via line 1406.
If the memory access request requires a memory read, then the memory is read as described above for processing block 1903 (processing block 200).
3). The data thus retrieved from memory 130 is loaded into the most significant bit data latch 1440 of the central processing unit (processing block 2004). The data in the memory that is not in the desired data field is stored in the barrel shifter 1450, as described in detail below.
Is removed at. The program then proceeds to decision block 2011 where a test is made as to whether a third access request of the central processing unit is required.

If the second access request of the central processing unit is a write request and not a read request,
Program 2000 performs a test to determine if the sum of the bit address and field size is greater than or equal to 32 (decision block 2005). If bit 5 of the sum of line 1409 is "1", the sum is 32 or greater. If this sum is greater than or equal to 32, the write operation extends beyond the second word boundary. In such a case, the second access of the central processing unit is a simple write operation. Accordingly, the input / output latches are loaded from the central processing unit most significant bit data latch 1440 (processing block 2006) and the data from the input / output latch is written to memory (processing block 201).
0). As with the read operation, the program then proceeds to decision block 2011 where a test is made as to whether a third access request of the central processing unit is required.

If the sum of the bit address and field size is less than 32, a left mask is needed.
This left mask is set based on the sum of the bit address and the field size (processing block 200).
7). The input / output latches are loaded with data from the central processing unit most significant bit data latch 1440 (processing block 2008). The memory word designated by the word address of the central processing unit is the memory 1
Called from 30 and loaded into the input / output latch while being masked by the left mask 1438 (processing block 2009). This process is similar to that described above in connection with processing block 1912 shown in FIG. Note that the right mask is not needed, since the second access of the central processing unit will of course involve the least significant bit of the memory word (FIGS. 13E, 13F,
13G, 13H and 13I). The input / output latches will now contain the modified data as required by the field write operation, which is called from memory 130 and for the bits in the selected field.

The program 2000 ends by testing whether a third access of the central processing unit is required. This is determined by checking if the sum of the bit address and field size is greater than 32 (decision block 201).
1). If this sum is greater than 32, then a third access is required. This is signaled by setting the third access request latch 1705 of the central processing unit (processing block 2012). This is signaled from the microsequencer 1740 via line 1743 to the request latch 1700. In any case, the first request latch of the central processing unit is reset (processing block 2
013), indicating that the request has been processed. with this,
The program 2000 ends (end block 201)
4). As described above, the program 2000 includes the program shown in FIG.
Is the same as the processing block 1810 shown in FIG.

FIG. 21 shows a program 2100 for processing the third access request of the central processing unit.
This program 2100 will be best understood in relation to the word alignment diagram of FIG. First, the central processing unit address register 1200 must be incremented by 16 to reference the next memory word after the second access. In this respect, the program is similar to the processing of the second access request of the central processing unit described above. The program 2100 shown in FIG.
This corresponds to the process of processing block 1808 shown in FIG.

When the program 2100 starts (start block 2101). A test is performed to determine if the access request is a read access request (decision block 2102). If the request is a read request, the right mask 1437 is set by the bit address (processing block 2103). This process can best be understood with reference to FIG. Field 2200 contains memory words 2201, 2202 and 2203 as at least a portion thereof. This is the case shown in FIG. 13I, that is, the only case where a third processing access request is required. Feed 2200
Are in three subfields, namely memory word 220.
1 contained in subfield 2211 and subfield 2212 corresponding to memory word 2202
, And the last subfield 2213 contained entirely within memory word 2203.

The first access of the central processing unit serves to store the subfield 2211 in the upper bit of the least significant bit data latch 1445 of the central processing unit. The second access of the central processing unit is the subfield 2212 corresponding to the memory word 2202.
The most significant bit data latch 14 of the central processing unit
Store in 40. The third access of the central processing unit should be a read, mask and modify operation similar to the read / modify / write operation described above. The data from the least significant bit data latch 1445 of the central processing unit containing the previously called subfield 2211 is loaded into the input / output latch (processing block 2104). Memory word 2203 is called from memory 130 and contains right sub-field 2212, right mask 1
The portion determined by 437 is the input / output latch 1
439 is loaded (processing block 2105). The resulting input / output latch data is stored in the least significant bit data latch 1445 of the central processing unit (processing block 2106). The data obtained by this includes a first subfield 2211 and a third subfield 2213. As with the read access described above, barrel shifter 1450 aligns the data for proper use by central processing unit 200. This will be described in detail below in connection with FIG.

If the third access of the central processing unit is a write access, a read / modify / write cycle is required. Left mask 1438 is set to correspond to the sum of bit address 1201 and field size (processing block 2107). The data stored in the least significant bit data latch 1445 of the central processing unit is loaded into the input / output latch (processing block 2108). Memory word 2203 is
It is read from memory 130 and loaded into input / output latch 1439 using left mask 1438 (processing block 2109). At this time, input / output latch 1439
Comprises the least significant bit corresponding to subfield 2213 and the most significant bit corresponding to the most significant bit of memory word 2203. This data in input / output latch 1439 is then written to memory 130 at the same location as memory word 2203 (processing block 211
0), complete read / modify / write operations. In any case, the third access of the central processing unit is completed by resetting the third request latch of the central processing unit (processing block 2111) and program 2
100 is complete (end block 2112).

The technique of inputting the first subfield 2211 and the third subfield 2213 to the least significant bit data latch 1445 of the central processing unit eliminates the need for a three word data latch of the central processing unit.
Note that in the preferred embodiment, the length of the field does not exceed 32 bits. However, some combinations of bit address and field size require that the selected field occupy a portion of three consecutive memory words. The two subfields are
It is accommodated in a single 32-bit latch containing the two 16-bit halves shown. Therefore, providing a third 16-bit data latch wastes circuit area. By storing two subfields in one half of the data latch, no additional circuitry is needed. With the above masking, these subfields can be properly separated. Circulating the data in the most significant bit data latch 1440 of the central processing unit and the least significant bit data latch 1445 of the central processing unit allows the subfields to be properly aligned in bit order.

According to the preferred embodiment, all field operations within central processing unit 200 are performed while adjusting the data to the right. When performing a field write operation, barrel shifter 1450 circularly shifts data left by an amount equal to the bit address before loading into central processing unit data latches 1440 and 1445. This serves to properly align the data for field write operations. This circular shift to the left automatically forms a first subfield 2211 and a third subfield 2213 in the least significant bit data latch 1445 of the central processing unit, as shown in FIG.

As mentioned above, the data read from memory 130 is aligned by barrel shifter 1450 for use by central processing unit 200. This process is shown in FIG. The data from the central processing unit data latches 1440 and 1445 include the most significant bit 2301 and the least significant bit 2302. Selected field 2310 has most significant bit 2
It is shown as crossing the word boundary between 301 and the least significant bit 2302. This alignment is given for illustration purposes only. This technique is equally applicable to all other field alignments. First, the field is aligned to the right by circularly shifting it to the right by the amount of bits indicated by the bit address. This process is shown schematically at 2311. The fields are 2211 and 2212 in FIG.
, And 2213, even when divided into three subfields, this shift causes all fields 2310 to be adjusted to the right in the proper order. The other parts of the data word that are not included in the selected field 2310 are not significant as they will be lost in the next process.

The field is then adjusted to the left by logically shifting it to the left by an amount 32 bits less than the field size. This process, shown generally at 2312, acts to eliminate bits of higher order than the most significant bits of the selected field. Bits that are less significant than the least significant bit of field 2310 should be removed in the next step and are therefore not significant. Field 2310 is again logically shifted right by an amount of 32 bits less than the field size. This removes bits that are less significant than the least significant bit of field 2310. The higher bits are generated based on the state of the action field extension bit 1106 or 1108 from the state revista 1100. The particular instruction executed by central processing unit 200 specifies whether field size 01105 and field extension 0 1106 work or field size 1107 and field extension 1108 work. If the selected field extension bit of the status register 1100 indicates a zero extension, then the high order bit 2320, which is all "0" s, is generated. On the other hand, when the field extension option indicates the extension of the code,
An upper bit 2330 is generated, which is all equal to the most significant bit of field 2310.

The preferred embodiments of the present invention have been described above in detail. In the preferred embodiment, some design choices have been made, but these are not necessary to practice the invention. For example, the central processing unit has been described as using 32-bit long data, while the memory has been described as using 16-bit long words. It will be apparent to those skilled in the art that these are merely design conveniences and not the subject matter of the present invention. The scope of the invention is defined by the claims.

The following items will be disclosed in relation to the above description. (1) The display update controller periodically generates a display update address register for defining one of the address positions in the memory in which display data to be called next is stored, and the display update request signal. Display update timer to
Display update address register increasing means for increasing the address stored in the display update address register for referring to display data to be called next when each display update memory access is permitted. The memory access control system according to claim 1. (2) The memory is a dynamic memory that requires periodic refreshing to retain data, and the memory access control system further includes a memory refresh controller that periodically generates a refresh memory access signal. The memory access controller further includes a refresh address register in which an address to be refreshed next is stored, and the memory priority controller further receives the refresh memory access signal and the memory priority controller. If the priority controller has had a pending memory access request, then grants the refresh memory access signal which is lower in priority than the display update access request and higher than the local processor access request, and the memory priority Rank control If the memory has no pending memory access request, the refresh memory access request having a lower priority than the local processor access request and the display update access request is permitted, and the memory refresh control is performed. The memory access control system according to claim 1, which is connected to a container. (3) The display update controller is a display update address register that specifies one of the address positions in the memory in which display data to be called next is stored, and a display that periodically generates the display update request signal. An update timer and display update address register increment means for incrementing the address stored in the display update address register for referencing the display data to be called next when each display update memory access is permitted. 3. The memory access control system according to the above 2nd item. (4) A memory refresh controller connected to the memory interface and periodically generating a refresh memory access signal is provided, and the memory access controller has a refresh address register in which an address to be refreshed next is stored. , The memory priority controller is further connected to the memory refresh controller to receive the refresh memory access signal and the memory priority controller has had a pending memory access request up to that point. In the case where the refresh memory access signal having a priority lower than the display update access request and higher than the local processor access request is permitted and the memory priority controller has not had a pending memory access request so far. 3. The memory access control system according to claim 2, wherein the refresh memory access request having a lower priority than the access request of the local processor and the display update access request is permitted.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer having a graphic function configured according to the principles of the present invention;

FIG. 2 is a block diagram showing a preferred embodiment of the graphic processing circuit of the present invention;

FIG. 3 is a diagram showing how to specify an individual pixel address in a bitmap memory by an XY address technique;

FIG. 4 is a diagram showing how to specify a field address by a linear address technique,

FIG. 5 is a diagram showing a preferred embodiment for storing pixel data of various lengths in one data word according to a preferred embodiment of the present invention;

FIG. 6 is a diagram showing the structure of the contents of operands stored in a register memory according to the preferred embodiment of the present invention;

FIG. 7 is a diagram showing characteristics of an array moving operation in the bitmap memory of the present invention,

FIG. 8 is a flowchart of a bit block transfer or array move operation according to the present invention;

FIG. 9 shows some of the input / output registers used in the preferred embodiment of the present invention,

10 is a detailed diagram of the host control register shown in FIG. 9;

FIG. 11 is a detailed diagram of a status register according to a preferred embodiment of the present invention;

FIG. 12 is a diagram showing in detail an address register according to a preferred embodiment of the present invention;

FIG. 13 is a diagram showing various cases of a relation between a selected field and a memory word according to a preferred embodiment of the present invention;

FIG. 14 is a diagram showing a structure of a memory access controller according to a preferred embodiment of the present invention;

FIG. 15 illustrates a structure for generating horizontal and vertical reset signals according to a preferred embodiment of the present invention,

FIG. 16 shows a structure for generating a DRAM refresh signal according to a preferred embodiment of the present invention,

FIG. 17 is a diagram showing in detail the sequencer shown in FIG.

FIG. 18 is a flowchart illustrating the operation of the programmable input address logic array shown in FIG. 17, according to a preferred embodiment of the present invention.

FIG. 19 is a flowchart illustrating the operation of the sequencer when performing the first memory access of the central processing unit according to the preferred embodiment of the present invention;

FIG. 20 is a flowchart illustrating the operation of the sequencer when performing the second memory access of the central processing unit according to the preferred embodiment of the present invention;

FIG. 21 is a flowchart illustrating the operation of the sequencer when performing the third memory access of the central processing unit according to the preferred embodiment of the present invention;

FIG. 22 is a diagram showing how a field intersecting two memory word boundaries is stored and manipulated in accordance with the present invention; and

23 is a diagram showing an operation of the barrel shifter shown in FIG. 14. FIG.

[Explanation of symbols]

 100 Graphic Computer System 110 Host Processing System 115 Host Bus 120 Graphic Processor 122 Video Memory Bus 130 Memory 132 Video RAM 134 Read Only Memory 140 Shift Register 150 Video Palette 160 Digital-Video Converter 170 Video Display 200 Central Processing Unit 210 Graphic Hardware 220 Register file 230 Instruction cache 240 Host interface 250 Memory interface 260 Input / output register 270 Video display controller

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Jerry Van Aken Kensington, Texas, United States 77478 Sugherland Fernhill 13563 (72) Inventor Neil Tebut France 6620 Golf Juan Simando Minoza Masre Pune (No address) (72) Invention Mark Ef Novak, Michigan, USA 48197 Ypsilanti Spinnaker Weissie 2-8845 (72) Inventor Thomas M. Preston England Bedfordshire Surrey Crossend Lane You Treehouse (No Address) (56) Reference JP 60-117338 (JP, A)

Claims (2)

[Claims] 1. A memory having a plurality of address locations for storing and recalling data, and a periodic display update access request for recalling display data corresponding to a visible display from successive address locations of the memory. And a local processing unit for performing data-based operations including a local memory read operation for reading data from the memory and a local memory write operation for writing data to the memory. However, the local processing unit generates a local processor memory access signal when a memory read operation or a memory write operation is requested, and a read / write control signal indicating whether a read or a write is requested. , The above local processing unit A local address register that designates one of the address locations in the memory and a local processor data register that receives data from the memory during a memory read operation and supplies data to the memory during a memory write operation. And further connected to the memory, the display update controller and the local processing unit to receive memory access requests, hold these memory access requests pending until granted, and address the corresponding address signal. , A memory priority controller that allows access to the memory in priority order by supplying a memory access request signal and corresponding read / write signals to the memory, which memory priority controller is Re Zeng memory access request or If if had the above a higher priority than access requests of local processors allow the display update access request and the memory priority controller does not have a memory access request pending until it memory access control system and permits the local processor access request at a higher priority than the display update access request. 2. A memory interface for transmitting address, data and read / write control signals, and a periodic display update access request for calling memory display data corresponding to a visible display from successive address locations. A display update controller, a local memory read operation connected to the memory interface and causing the memory interface to generate a specified address and a read control signal for reading data from the memory; A local processing unit for performing data-based operations including a specified address for writing a write control signal and a local write memory operation for generating a write control signal. Or a local processor memory access signal when either a write operation is requested, a read / write control signal indicating which co-input read or write operation is requested is generated, and the local processing unit comprises: A local address register for designating address locations, a local processor data register for receiving data from the memory interface during a memory read operation and providing data to the memory interface during a memory write operation, and further Connected to the memory interface, the display update controller and the local processing unit to receive memory access requests, hold these memory access requests pending until granted, and respond. The memory priority controller comprises a memory priority controller for permitting access to the memory in priority order by supplying an address signal, a memory access request signal and a corresponding read / write signal to the memory interface. , if the controller had a memory access request pending until it permits <br/> the display update access request at a higher priority than access requests of the local processor and this memory priority control vessel memory access control system and permits the local processor access request at a higher priority than the display update access request when the memory access request pending did not have before.