JPS6224546U - - Google Patents
Info
- Publication number
- JPS6224546U JPS6224546U JP11717785U JP11717785U JPS6224546U JP S6224546 U JPS6224546 U JP S6224546U JP 11717785 U JP11717785 U JP 11717785U JP 11717785 U JP11717785 U JP 11717785U JP S6224546 U JPS6224546 U JP S6224546U
- Authority
- JP
- Japan
- Prior art keywords
- stereo
- circuit
- trigger circuit
- display trigger
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stereo-Broadcasting Methods (AREA)
Description
第１図は本考案に係るステレオ受信機を示す図
、第２図は本考案に利用されるステレオ復調回路
を示す図である。
３は中間周波増幅回路、５はマルチプレツクス
回路、８は３８ＫＨＺスイツチング回路、９はス
テレオ復調回路、１０はステレオ表示トリガ回路
、１１はステレオ受信表示用素子、１２はセパレ
ーシヨン制御回路。
FIG. 1 is a diagram showing a stereo receiver according to the present invention, and FIG. 2 is a diagram showing a stereo demodulation circuit used in the present invention. 3 is an intermediate frequency amplifier circuit, 5 is a multiplex circuit, 8 is a 38 KHz switching circuit, 9 is a stereo demodulation circuit, 10 is a stereo display trigger circuit, 11 is a stereo reception display element, and 12 is a separation control circuit.
Claims (1)
状態となるステレオ表示トリガ回路と、このステ
レオ表示トリガ回路の動作電流に応じたスイツチ
ングレベルにてスイツチングされるスイツチング
回路と、このスイツチング回路より出力されるス
イツチング信号により駆動されるステレオ復調回
路と、前記ステレオ表示トリガ回路に接続された
ステレオ受信表示用素子と、中間周波信号レベル
に応じた動作電流を前記ステレオ表示トリガ回路
に印加するセパレーシヨン制御回路とよりなるス
テレオ受信機。 A stereo display trigger circuit that becomes driven when a stereo pilot signal is detected, a switching circuit that switches at a switching level according to the operating current of this stereo display trigger circuit, and a switching signal that is output from this switching circuit. a stereo demodulation circuit driven by a stereo display trigger circuit, a stereo reception display element connected to the stereo display trigger circuit, and a separation control circuit that applies an operating current to the stereo display trigger circuit according to the intermediate frequency signal level. stereo receiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11717785U JPS6224546U (en) | 1985-07-30 | 1985-07-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11717785U JPS6224546U (en) | 1985-07-30 | 1985-07-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6224546U true JPS6224546U (en) | 1987-02-14 |
Family
ID=31002452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11717785U Pending JPS6224546U (en) | 1985-07-30 | 1985-07-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6224546U (en) |
-
1985
- 1985-07-30 JP JP11717785U patent/JPS6224546U/ja active Pending