JPS62243419A - Priority timer circuit - Google Patents

Abstract

PURPOSE:To obtain an accurate timer by using a highly accurate frequency by using a trigger input signal arrived at a preceding time so as to count up a clock pulse, comparing its output with a prescribed number and leading a timer signal thereby eliminating the need for the adjustment of pulse width. CONSTITUTION:An output 105 of a holding circuit 12 on a line 5 keeps the state of the line 4 by the leading of a first-come signal 101 in trigger input signals 101,102 of lines 1,2. While the output 105 is at H, a clock signal 107 on the line 7 becomes a signal 108 on a line 8 as it is, the signal 106 on the line 6 entering a clear terminal of a counter circuit 16 is at L and the circuit 16 is counted up. When the setting value at a comaprator circuit 17 is coincident with the output of the circuit 16, a coincidence sigal 110 is outputted and the output 105 of the circuit 12 rises as an output 106 of the inverting circuit 14 and given to the clear terminal of the circuit 16. Thus, the signal 110 goes to an L level. Thus, the signal 105 is started by the first-come signal and utilized as a timer signal generating a pulse of a prescribed time width.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a priority timer circuit that is driven by first-arrival signals of a plurality of inputs and automatically resets after a certain period of time.

2. Description of the Related Art A conventional timer circuit has a configuration as shown in FIG. That is, 2o1 is a priority trigger circuit that is output based on the first arrival signal, and has input signal lines 203 and 204. 202 is a one-shot multivibrator activated by the output from the output signal line 206 of the priority trigger circuit 201. 206 is an output signal line of the one-shot multivibrator 202. In the above configuration, the trigger signal that first arrives at the input signal line 203 or 204 drives the priority trigger circuit 201 and is output to the output signal line 206, and the one-shot multivibrator 2
Start 02.

The one-shot multivibrator 202 outputs a pulse with a preset time width to the output signal line 206, which serves as a priority timer output.

Problems to be Solved by the Invention In such a conventional configuration, it is difficult to accurately set the pulse time width of the one-shot multivibrator 202 by adjusting the capacitance of the capacitor 207 and the value of the resistor 208. Another problem is that the pulse time width changes as the capacitance of the capacitor changes over time.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, it is an object of the present invention to provide a priority timer circuit that eliminates the need for pulse width adjustment, has good pulse width accuracy, and is resistant to aging. be.

Means for Solving the Problems In order to achieve the above object, the priority timer circuit of the present invention includes a priority trigger circuit that outputs according to the first-arrival signal, a holding circuit that inputs and outputs the output of the priority trigger circuit, and a clock. a clock generation circuit that generates a pulse; a product calculation circuit that inputs the output of the holding circuit and the output of the clock generation circuit; and outputs a clock pulse of the clock generation circuit when the holding circuit outputs; and an output of the holding circuit. an inverting circuit that inputs and inverts the output; a counter circuit that counts up the output of the product calculation circuit and resets the count by the output of the inverting circuit; When compared with the pattern and matches the reset terminal of the holding circuit,
It consists of a comparison circuit that outputs a match signal.

The output of the holding circuit is held high in response to the first-arrived trigger signal, and during this time the pulses output from the clock generating circuit are counted up by the counter circuit.

The output of the counter circuit is compared with a predetermined number by a comparison circuit, and if they match, the output of the holding circuit is dropped to low. When , the inverting circuit outputs a reset signal to the counter circuit to make the output of the counter circuit zero.

The output of the holding circuit can then be used as a timer signal that remains high for a period of time to count a given number of pulses from the clock generating circuit.

51.-/゛Embodiment FIG. 1 is a block diagram of a priority timer circuit according to an embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes a priority trigger circuit that is activated by the first-arrived trigger manual signal from input signal lines 1 and 2, and a priority trigger signal line 3 is connected to the output end of this priority trigger circuit 11.

Reference numeral 4 denotes a setting signal line kept high, and 12 a holding circuit composed of a D-type flip-flop which inputs the priority trigger signal line 3 to a clock terminal and inputs the setting signal line 4 to a D terminal.

15 is a clock generation circuit that generates clock pulses;
The output terminal of this clock generation circuit 16 is connected to the clock signal line 7.
is connected. 13 is a product operation circuit which connects the clock signal line 7 and the output signal line 6 from the holding circuit 12 to the input side, and connects the clock signal line 8 to the output side; 14 connects the output signal line 5 and the signal line 6; This is an inverting circuit that inverts the input signal and outputs it.

16 connects the clock signal line 8 to the clock input terminal, and 6.
−7 A counter circuit with signal line 6 connected to the clear input terminal,
A plurality of output signal lines 9 are connected to the output terminal of this counter circuit 16. A comparison circuit 17 inputs the signal from the output signal line 9, compares it with a predetermined pattern, and outputs a match signal to the match signal line 10 connected to the reset terminal of the holding circuit 12 if they match. It is a circuit.

Next, the operation of the above embodiment will be explained based on FIG. 2 showing signal waveforms of each part.

When the trigger manual signals 101 and 102 arrive at the input signal line 1.2, the output signal 105 of the holding circuit on the holding signal line 5 holds the state of the setting signal line 4 due to the rise of the first-arrival signal 101. Since the setting signal line 4 is set high, the output signal 105 of the holding circuit becomes high.

While the output signal 106 of the holding circuit is high, the signal 107 on the clock signal line 7 remains unchanged as the signal 108 on the signal line 8.
can be conveyed to.

During this time, the signal on the signal line 6 that enters the clear terminal of the counter circuit 16 is at low level 7, as shown by the signal 106, and is inactive, so the counter circuit 16 is counted up.

If the number 15 is set in advance in the comparator circuit 17, the moment the output of the counter circuit 16 reaches 15,
A match signal 110 is output on the match signal line 10, and since the holding circuit has been reset, the signal 105 falls, and the output signal 106 of the inverting circuit, which is an inverted signal of the output signal 105 of the holding circuit, rises. Since the output signal 106 of the inverting circuit is input to the clear terminal of the counter circuit 16, the rising edge of the output signal 106 of the inverting circuit clears the counter circuit 16.
is cleared and the output of the counter circuit 16 becomes zero.

When the output of the counter circuit 16 becomes zero, the comparator circuit 17
When the match signal 110 no longer matches the set value 16, the match signal 110 returns to low as shown in FIG.

The above operation returns this circuit to its initial state.

The signal 105 is activated by the first arrival signal and can be used as a timer signal that generates a pulse with a constant time width.

Effects of the Invention As described above, according to the present invention, the output of the holding circuit is set simultaneously with the arrival of the first trigger signal, the output clock signal of the clock generation circuit is counted up to a certain value, and then the output of the holding circuit is set. A timer can be created by resetting the output.

By adopting such a configuration, a highly accurate frequency of the clock signal can be obtained using a crystal oscillator or the like, making it possible to create a precise timer.

This can be expected to have a great effect when applied to time measurement in digital data communications.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a priority timer circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, and FIG.
The figure is a block diagram of a conventional priority timer circuit. 11...Priority trigger circuit, 12...
Holding circuit, 91゛-no13...Product calculation circuit, 14...Inversion circuit, 16...Clock generation circuit, 16...
... Counter circuit, 17... Comparison circuit. Agent's name: Patent attorney Toshi Nakao #Okaka1meToIUshito11Riki'-sg, j4--Ittancho8roI6--7IIIPukuseijokai2jimi1cm-Ittori> Rotating Muto 17-tc#75 'J':;,

Claims (1)

[Claims] A priority trigger circuit that outputs in response to a first-arrival trigger signal, a holding circuit that inputs and outputs the output of the priority trigger circuit, a clock pulse generation circuit that generates a clock pulse, an output of the holding circuit, and an output of the clock generation circuit. and a product calculation circuit that outputs the clock pulse of the clock generation circuit when the holding circuit outputs, an inversion circuit that inputs the output of the holding circuit and inverts the output, and counts up the output of the product calculation circuit. and a counter circuit that resets the count by the output of the inversion circuit, and inputs the output of the counter circuit, compares it with a predetermined pattern, and sends it to the reset terminal of the holding circuit.
A priority timer circuit consisting of a comparison circuit that outputs a match signal when a match occurs.