JPS62243342A - Semiconductor device - Google Patents

Abstract

PURPOSE:To stably connect wirings with a diffused layer in a semiconductor device by so forming a second insulating film formed by anisotropically etching on the side of a contact hole that the upper portion is thin and the lower portion is thick to form a taper in the hole, thereby eliminating the formation of an extremely thin portion or a disconnected portion at metal wiring depositing time. CONSTITUTION:An insulating film 1 is grown on a diffused layer 3 formed on a substrate 5, a contact hole is formed by anisotropically etching, a second insulating film 6 is grown by a CVD method on the hole, and removed by anisotropically etching. Then, a CVD film remains only on the sidewall of the contact. When wirings 2 are formed thereon, a contact corresponding to miniaturization is obtained. Thus, since a taper is formed at the CVD film without requiring an excess masking step from the edge to the bottom of the contact, the thickness of the deposited film necessary for wirings is obtained also on the sidewall of the hole to suppress the disconnection of the deposited film which feasibly occurs at the edge of the contact, thereby forming the contact without increasing the area of the hole. Accordingly, a miniaturization for raising the integration of a semiconductor device can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having fine contact holes.

BACKGROUND OF THE INVENTION As semiconductor devices become more highly integrated, the diffusion layers of the elements constituting the semiconductor devices, the metal films 21 that connect them, and the contact portions of the lines are also required to be processed with high accuracy and fineness. Conventionally, this type of contact was formed using the so-called RIB method, in which the insulating film was etched in only one direction.
Anisotropic etching methods were used. The circumstances surrounding this will be explained with reference to FIG. In order to obtain a fine contact on the diffusion layer 3 formed on the substrate 5,
A contact hole is formed on the insulating film 1 by the above-described anisotropic etching, and then a metal wiring layer 2 is deposited and connected to the diffusion layer 3. As shown in the figure, anisotropic etching allows the formation of almost vertical holes and does not spread into the vicinity, making it possible to form fine contacts.

Problems to be Solved by the Invention As shown in FIG. 2, fine contact holes formed by anisotropic etching have nearly vertical sides. Therefore, the surface parallel to the direction of the metal particles to be evaporated, that is, the side surface of the hole, is where the metal film is difficult to adhere.
For example, there is a part that looks like a person in the diagram. In such portions, there is a serious drawback in that during the operation of the half-conductor device, the current density to the metal wiring is extremely low, leading to wire breakage due to so-called electromigration. Furthermore, in extreme cases, there is a problem in that no metal is deposited on the person's part at all, and the connection between the diffusion layer 3 and the wiring 2 is not made.

One way to solve this problem is to perform anisotropic etching on the insulating film 1 and then perform wet etching to taper the sides of the contact hole, as shown in Figure 3. The purpose is to remove the part indicated by 4 in the middle. By doing this, the problem related to the thin part of the metal film as shown in Figure 2 can be solved, but since the opening of the contact hole is enlarged as shown in the figure, the contact hole is occupied. The area becomes larger. This makes it unsuitable for contact holes in semiconductor integrated circuits that require fineness, high density, and high integration.

Means for Solving the Problems In order to solve the above problems, the present invention has an impurity diffusion region in a predetermined region near the surface of a semiconductor substrate, and a first insulating film on the semiconductor substrate. , the first insulating film on the diffusion region has an opening whose sidewall is substantially perpendicular to the semiconductor substrate, and a second insulating film having a thickness gradually increasing in the depth direction on the sidewall of the opening. and a conductive layer on the diffusion region at the bottom of the opening, on the second insulating film on the side wall thereof, and on the first insulating film other than the opening part. Provide equipment.

The second insulating film formed on the side surface of the working contact hole by anisotropic etching is thin at the top of the contact hole.
It becomes thicker at the bottom and tapers into the contact hole. This prevents the formation of extremely thin portions or disconnected portions during vapor deposition of the metal wiring, making it possible not only to stably connect the wiring and the diffusion layer, but also to form fine contacts.

Example An example of the present invention will be shown below.

FIG. 1 shows the 5-meter disconnection at the contact portion in the present invention.
-/゛ plane structure is shown.

A diffusion layer 3 is formed on a substrate 5, and an insulating film 1 is grown thereon. After a contact hole is formed by anisotropic etching of the insulating film, a second insulating film 6 is grown over the contact hole by CVD. When the second insulating film formed by CVD on the diffusion layer is completely removed by anisotropic etching, the CVD film remains only on the sidewalls of the contacts. When wiring 2 is formed on this, a contact compatible with miniaturization can be obtained.

As described above, in this embodiment, a taper is formed with the CVD film from the edge of the contact part to the bottom, that is, the diffusion layer, without the need for an extra mask process. A thick film can be obtained, and it is possible to suppress disconnection of the deposited film, which tends to occur at the edge of the contact.

Furthermore, since contacts can be formed without increasing the contact hole area, miniaturization to increase the degree of integration of semiconductor devices becomes possible.

In addition, a shape simulation was performed to confirm the effect of the CVD film formed on the contact sidewall of this example in preventing disconnection of the deposited film. The ratio of the thickness of the deposited film on the contact sidewall to the thickness of the deposited film on the insulating film was defined as the deposition rate on the contact sidewall, and the dependence of this deposition rate on the taper angle of the contact sidewall was simulated. the result,
The evaporation rate is 10% with no taper at all, whereas the evaporation rate with a 60° taper is 4o%, and the taper has a large effect on the occurrence of wire breakage due to electromigration, etc. It was confirmed that

As described in detail, the present invention prevents disconnection at the edge of the contact and does not increase the contact area, thereby greatly contributing to higher integration of semiconductor integrated circuits.

[Brief explanation of drawings]

Fig. 1 is a sectional view of the contact part in the present invention, Fig. 2 is a sectional view of L+; 7
. , -7 is a cross-sectional view of a conventional example showing one method of doing so. 1... Insulating film, 2... Wiring, 3...
... Diffusion layer, 4 ... Part removed by additional etching, 6 ... Substrate, 6 ... Second insulating film formed by CVD method. Name of agent: Patent attorney Toshio Nakao and 1 other person f-
・IP, a Discipline 2-11 Flies Fig. 1 3-Busuke S-11 Motobayashi 6゛-・-cVDn Edit Fig. 2

Claims (1)

[Claims] an impurity diffusion region in a predetermined region near the surface of a semiconductor substrate, a first insulating film on the semiconductor substrate, and a sidewall of the first insulating film on the diffusion region substantially touching the semiconductor substrate; It has a vertical opening, and a second insulating film whose thickness gradually increases in the depth direction on the side wall of the opening, and a second insulating film on the diffusion region at the bottom of the opening and on the side wall of the opening. A semiconductor device comprising a conductive layer on an insulating film and on the first insulating film other than the opening.