JPS62243324A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPS62243324A
JPS62243324A JP8644186A JP8644186A JPS62243324A JP S62243324 A JPS62243324 A JP S62243324A JP 8644186 A JP8644186 A JP 8644186A JP 8644186 A JP8644186 A JP 8644186A JP S62243324 A JPS62243324 A JP S62243324A
Authority
JP
Japan
Prior art keywords
film
contact hole
metal
resist
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8644186A
Other languages
Japanese (ja)
Inventor
Tsutomu Fujita
勉 藤田
Hiroshi Yamamoto
浩 山本
Shoichi Tanimura
谷村 彰一
Takao Kakiuchi
垣内 孝夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8644186A priority Critical patent/JPS62243324A/en
Publication of JPS62243324A publication Critical patent/JPS62243324A/en
Priority to US07/532,170 priority patent/US5084413A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To avoid conductor discontinuity and improve reliability such as electromigration resistance by a method wherein, after a contact hole is formed, a semiconductor thin film or a thin film containing metal is formed on the side surface and the bottom surface of the contact hole only and then the con tact hole is selectively filled with metal. CONSTITUTION:After a high concentration diffused layer 2 is formed in a semiconductor Si substrate 1, an insulating film 3 is formed on the substrate 1 and a contact hole 4 is drilled in the insulating film 3 to expose the diffused layer 2. Then a thin polycrystalline Si film 5 is deposited over the whole surface. Resist 6 is applied to the whole surface to level the surface. Successively, the resist 6 is etched over the whole surface and left in the contact hole 4 only the polycrystalline Si film 5 is etched with the remaining resist 6 as a mask so as to be left on the side surface and the bottom surface of the contact hole 4 only. After the resist 6 is removed, gas composed of WF6 diluted by Ar is made to react with the polycrystalline Si film 5 to deposit a W film 7. Then WF6 is made to react with gas containing H2 and W 7 is made to grow by utilizing hydrogen reduction reaction.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は微細な電極コンタクトや多層配線を有する高密
度大集積な半導体集積回路の製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a high-density, large-scale integrated semiconductor integrated circuit having fine electrode contacts and multilayer wiring.

従来の技術 ]ンタクトに電極を形成する場合において、通常は人E
等の金属が用いられ、その堆積法としてはスパッタ法が
採用されている。しかしながらコンタクトの幅が1μm
以下の微細寸法になるとAIのスパッタ法ではコンタク
トの側面にほとんどムlが付着し力くなる。その結果、
人l配線が断線したりエレクトロマイグレーション耐性
等の信頼性に重要な問題が発生することになる。
[Prior art] When forming electrodes on contacts, usually a person
These metals are used, and the sputtering method is adopted as the deposition method. However, the contact width is 1 μm
When the micro-dimensions are smaller than the following, in the AI sputtering method, most of the mulch adheres to the side surfaces of the contact, which becomes difficult. the result,
Significant reliability problems such as wire breakage and electromigration resistance will occur.

これを防ぐためにコンタクトに選択的にメタルを埋込む
技術がある。この例を以下に示す。
To prevent this, there is a technique for selectively embedding metal in the contacts. An example of this is shown below.

第9図に従来の製造法を用いて、微細コンタクトに選択
的に金属を埋込んだ場合の断面図を示す。
FIG. 9 shows a cross-sectional view when metal is selectively embedded in fine contacts using a conventional manufacturing method.

同図において8は半導体基板、9は拡散層、10は絶縁
膜、11はコンタクトホール、12はコンタクトホール
11に埋込まれた高融点金属のタングステン、13は絶
縁膜上に堆積したタングステン、14は拡散層に侵入し
たタングステンである。
In the figure, 8 is a semiconductor substrate, 9 is a diffusion layer, 10 is an insulating film, 11 is a contact hole, 12 is tungsten, a high melting point metal, embedded in the contact hole 11, 13 is tungsten deposited on the insulating film, 14 is the tungsten that has entered the diffusion layer.

これは以下に述べる製法により形成された。即ち、絶縁
膜1oにコンタクトホール11を開孔した後、wF6(
6弗化タングステン)と基板シリコン8を反応させ、 2wF6+38工→2 w +38iF4タングステン
(ロ))12をコンタクトホール11に選択的に成長さ
せる。この時、コンタクトホール11の底面にはシリコ
ン基板が露出しているので生じる。即ち、長時間反応さ
せると、絶縁物1゜上に付着した反応副産物や絶縁膜1
oの表面にはじめから存在する核を中心としてW13が
堆積されることになる。このように絶縁膜1o上にW1
3が堆積すると選択性が失なわれ、コンタクトホール1
2のみにW12を埋込むことが不可能となる。
This was formed by the manufacturing method described below. That is, after opening the contact hole 11 in the insulating film 1o, wF6(
Tungsten hexafluoride) is reacted with the substrate silicon 8 to selectively grow 2wF6+38tungsten (2w+38iF4 tungsten (b)) 12 in the contact hole 11. At this time, this occurs because the silicon substrate is exposed at the bottom of the contact hole 11. In other words, if the reaction is allowed to occur for a long time, reaction by-products and insulating film 1 that adhere to the insulating material 1° will be removed.
W13 is deposited centering on the nucleus that is originally present on the surface of the wafer. In this way, W1 is placed on the insulating film 1o.
3 is deposited, selectivity is lost and contact hole 1
It becomes impossible to embed W12 only in 2.

この方法では約2000〜3000への厚みのWの選択
成長が限度であり、0.5〜1μmの深さを持つコンタ
クトを完全に埋込むことが出来ない。
This method has a limit of selective growth of W to a thickness of approximately 2000 to 3000 μm, and it is not possible to completely bury a contact having a depth of 0.5 to 1 μm.

さらにコンタクト11底面の周辺部では絶縁膜10のス
トレス等の原因により、W14が拡散層9まで侵入し、
拡散層9と半導体基板8との接合を破壊に至らしめる。
Furthermore, in the periphery of the bottom surface of the contact 11, W14 penetrates into the diffusion layer 9 due to stress in the insulating film 10, etc.
This leads to destruction of the bond between the diffusion layer 9 and the semiconductor substrate 8.

以上述べたごとく、従来の製造法では、厚くWを埋込む
ことが出来ないだめ、配線の断線が起こったり、まだ、
信頼性上の問題。
As mentioned above, with conventional manufacturing methods, it is not possible to embed W thickly, which may lead to disconnection of wiring or
Reliability issues.

接合破壊等の問題が発生する。Problems such as bond breakdown may occur.

+                   1\本発明
は従来の欠点を鑑みてなされたもので、簡単な方法で、
金属の侵入によるコンタクトの破壊を防ぐと共に選択的
にコンタクトホールを金属で埋込むことを目的としてい
る。
+ 1\The present invention was made in view of the drawbacks of the conventional technology, and is a simple method that
The purpose is to prevent contact destruction due to metal intrusion and to selectively fill contact holes with metal.

問題点を解決するだめの手段 6、、−7 本発明は上記問題点を解決するため、コンタクトホール
を形成した後、コンタクトホールの側面及び底面にのみ
薄く半導体薄膜あるいは金属を含む薄膜を形成する。そ
の後、金属を含んだガスを反応させ、選択的にコンタク
トホールを金属で埋込むものである。
Means for Solving Problems 6, -7 The present invention solves the above problems by forming a thin semiconductor film or a thin film containing metal only on the side and bottom surfaces of the contact hole after forming the contact hole. . Thereafter, a gas containing metal is reacted to selectively fill the contact hole with metal.

作用 本発明は上記の方法により、微細なコンタクトホールに
断線することなく電極配線を形成することが出来る上に
、コンタクトの破壊防止、配線の信頼性向上に効果があ
る。
Function The present invention is capable of forming electrode wiring in minute contact holes without disconnection by the above-described method, and is also effective in preventing damage to the contacts and improving reliability of the wiring.

実施例 第1図は本発明の実施例において、金属(タングステン
)を完全に埋込んだ微細なコンタクトの断面図である。
Embodiment FIG. 1 is a sectional view of a fine contact completely filled with metal (tungsten) in an embodiment of the present invention.

同図において1は半導体基板(シリコン層)、2は高濃
度の拡散層(シリコン層)、3は絶縁膜、4はコンタク
トホール、5はコンタクトホール4の側面及び底面に選
択的に形成された多結晶シリコン膜、7はコンタクトホ
ール4に選択的に埋込まれたタングステン(W)である
In the figure, 1 is a semiconductor substrate (silicon layer), 2 is a high-concentration diffusion layer (silicon layer), 3 is an insulating film, 4 is a contact hole, and 5 is selectively formed on the side and bottom of the contact hole 4. A polycrystalline silicon film 7 is tungsten (W) selectively buried in the contact hole 4 .

第2図〜第8図にて製造方法を説明する。第2図におい
て、1は半導体シリコン基板、2は高濃度の拡散層、3
は絶縁膜でコンタクトホール4が形成され、拡散層2が
露出している。第3図において全面にCVD法で多結晶
シリコン膜5を1oO〜10oO人と薄く堆積する。こ
の場合、多結晶シリコン膜のかわりに金属を含む膜を堆
積してもよい。例を上げると、w8i2 、w 、Mo
 、 MoSi2等がある。CVD法はステップカバレ
ジがよいのでコンタクトホール4の側面に充分に膜が付
着する。
The manufacturing method will be explained with reference to FIGS. 2 to 8. In FIG. 2, 1 is a semiconductor silicon substrate, 2 is a high concentration diffusion layer, and 3 is a semiconductor silicon substrate.
A contact hole 4 is formed in an insulating film, and the diffusion layer 2 is exposed. In FIG. 3, a polycrystalline silicon film 5 is deposited on the entire surface by CVD to a thickness of 100 to 1000 mm. In this case, a film containing metal may be deposited instead of the polycrystalline silicon film. For example, w8i2, w, Mo
, MoSi2, etc. Since the CVD method has good step coverage, a film is sufficiently deposited on the side surfaces of the contact hole 4.

第4図においてレジスト6を全面にコートし、表面の平
坦化を行なう0レジスト6は液状なのでコンタクトホー
ル4はレジスト6で完全に埋まる。
In FIG. 4, the entire surface is coated with a resist 6, and since the resist 6 used to planarize the surface is liquid, the contact hole 4 is completely filled with the resist 6.

引き続き第5図において、レジスト6をドライエツチン
グ法により全面エツチングし、コンタクトホール4のみ
レジスト6を残す。コンタクトホールのレジスト6の厚
みはエツチング時間によってコントロール出来る。コン
タクトホール4上にハ厚いレジスト5が残っているので
この工程が可トホール4が埋まる物質であり、かつ薄膜
5、及び絶縁3がエツチングされずに、上記物質が除去
出来るものであれば何でもよく例としてはポリイミドで
もよい。第6図においてレジスト5をマスクとして多結
晶シリコン膜5をエツチングし、コンタクトホール4の
側面及び底面にのみ多結晶シリコン膜6を残す。第7図
においてレジスト6を除去した後、wF6(e弗化タン
グステン)を人r(アルゴン)で希釈したガスを多結晶
シリコン膜5と反応させタングステン膜(W)を堆積さ
せる。即ち、 2 wF6−1−38i→2w−4−38iF4  の
シリコン還元反応を利用してコンタクトホール4の側面
及び底面のみにタングステン7を選択成長させる。
Subsequently, in FIG. 5, the entire surface of the resist 6 is etched by a dry etching method, leaving only the contact hole 4 as the resist 6. The thickness of the resist 6 in the contact hole can be controlled by the etching time. Since a thick resist 5 remains on the contact hole 4, this process can be performed using any material that can fill the hole 4 and remove the above material without etching the thin film 5 and the insulation 3. For example, polyimide may be used. In FIG. 6, polycrystalline silicon film 5 is etched using resist 5 as a mask, leaving polycrystalline silicon film 6 only on the side and bottom surfaces of contact hole 4. In FIG. 7, after the resist 6 is removed, a gas prepared by diluting wF6 (e-tungsten fluoride) with argon (argon) is reacted with the polycrystalline silicon film 5 to deposit a tungsten film (W). That is, tungsten 7 is selectively grown only on the side and bottom surfaces of contact hole 4 using the silicon reduction reaction of 2wF6-1-38i→2w-4-38iF4.

この反応ではwF6は主に多結晶シリコン5と反応する
ので、半導体基板1に存在する単結晶シリコンの拡散層
1とはほとんど反応しない。したがって、wF6が拡散
層2と反応し絶縁膜3の界面に沿ってタングステンが侵
入する現象、及びwFが拡散層2と反応し、タングステ
ンが垂直方向に進み接合が破壊される現象が阻止される
。この結果、タングステン7による接合破壊、コンタク
ト破壊が起こらない。次に第8図においてwF6とH2
(水素)を含んだガスを反応させる。即ち、WF6 +
 3 H2→w+eHF の水素還元反応を利用してタ
ングステン7を成長させる。この時、水素は金属表面の
みに吸着してイオン化する性質があるので、水素還元反
応はコンタクトホール4の側面及び底面からのみ成長し
、絶縁膜3上には成長しない。さらに、コンタクトホー
ル4において、側面からの反応による堆積も利用してい
るので、短時間でコンタクトホール4を埋込むことが出
来る。例えば、アスペクト比が1のコンタクトホールで
は時間が半分になる。さらにコンタクトが微細になるほ
どその効果が大きい。成長時間が短かいと、絶縁膜3上
に反応の副産物が付着しない上に、はじめから絶縁膜3
上に存在する核を中心としてタングステンが堆積されな
い。そのため選択性が保たれコンタクトホール4をタン
グステン7コンタクトホール4の側面に付着している多
結晶シリコン5の高さをコントロール出来るので、コン
タクトホール4に埋込まれたタングステン7の平坦性を
よくすることが出来る。この後は通常のスパッタ法で簡
単に電極や配線を形成することが可能となる。
In this reaction, wF6 mainly reacts with polycrystalline silicon 5, and therefore hardly reacts with single-crystal silicon diffusion layer 1 present in semiconductor substrate 1. Therefore, the phenomenon in which wF6 reacts with the diffusion layer 2 and tungsten invades along the interface of the insulating film 3, and the phenomenon in which wF reacts with the diffusion layer 2 and tungsten advances in the vertical direction and destroys the junction are prevented. . As a result, junction breakdown and contact breakdown due to tungsten 7 do not occur. Next, in Fig. 8, wF6 and H2
(hydrogen)-containing gas to react. That is, WF6 +
3 Tungsten 7 is grown using the hydrogen reduction reaction of H2→w+eHF. At this time, since hydrogen has the property of adsorbing and ionizing only on the metal surface, the hydrogen reduction reaction grows only from the side and bottom surfaces of the contact hole 4 and does not grow on the insulating film 3. Further, in the contact hole 4, since deposition by reaction from the side surface is also utilized, the contact hole 4 can be filled in a short time. For example, for a contact hole with an aspect ratio of 1, the time is halved. Furthermore, the finer the contact, the greater the effect. If the growth time is short, reaction by-products will not adhere to the insulating film 3, and the insulating film 3 will not adhere to the insulating film 3 from the beginning.
Tungsten is not deposited around the overlying core. Therefore, selectivity is maintained and the height of the polycrystalline silicon 5 attached to the side surface of the contact hole 4 can be controlled, improving the flatness of the tungsten 7 embedded in the contact hole 4. I can do it. After this, electrodes and wiring can be easily formed using a normal sputtering method.

本実施例では、第7図、第8図において、金属を含んだ
ガスとしてwF6を用いた例を示したが、他のガスとし
てMoF6 、Mo(GO)6 、W(CO)6を使っ
て同様にMoやWを堆積することができる。
In this example, in Figs. 7 and 8, an example was shown in which wF6 was used as the metal-containing gas, but other gases such as MoF6, Mo(GO)6, and W(CO)6 were used. Similarly, Mo or W can be deposited.

また第1図〜第8図に示しだ拡散層2はシリコン層であ
るが、この表面に、w Si2 、 Ti Si2 、
 Mo Si2 。
Further, the diffusion layer 2 shown in FIGS. 1 to 8 is a silicon layer, and on the surface thereof, w Si2 , Ti Si2 ,
MoSi2.

Mo、Ti等の膜があっても当然ながら本発明の方法を
用いることが出来るのは言うまでもない。
It goes without saying that the method of the present invention can be used even if there is a film of Mo, Ti, etc.

発明の効果 以上述べたように本発明によれば、簡単な方法で、コン
タクトを破壊することなく微細なコンタクトホールを選
択的に金属で埋込むことができるので、電極や配線を形
成しても断線が起こらない)書にエレクトロマイグレー
ション耐性等の信頼性向上に著しい効果がある。従って
高密度で大集積な半導体集積回路の実現が容易となる。
Effects of the Invention As described above, according to the present invention, fine contact holes can be selectively filled with metal using a simple method without destroying the contacts, so even if electrodes and wiring are formed, This has a significant effect on improving reliability, such as electromigration resistance, with no wire breakage. Therefore, it becomes easy to realize a high-density, large-scale semiconductor integrated circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における微細なコンタクトの
断面図、第2図〜第8図は上記微細なコンタクトの製造
プロセスを説明するだめの断面図、第9図は従来の製造
法による微細なコンタクトの断面図である。 1・・・・・・半導体基板、2・・・・・・拡散層、3
・・・・・・絶縁膜、4・・・・・・コンタクトホール
、5・・・・・・多結晶シリコン膜、7・・・・・・コ
ンタクトホールに埋込まれたタングステン(W)。
Fig. 1 is a cross-sectional view of a fine contact according to an embodiment of the present invention, Figs. 2 to 8 are cross-sectional views for explaining the manufacturing process of the above-mentioned fine contact, and Fig. 9 is a cross-sectional view of a conventional manufacturing method. FIG. 3 is a cross-sectional view of a fine contact. 1... Semiconductor substrate, 2... Diffusion layer, 3
...Insulating film, 4...Contact hole, 5...Polycrystalline silicon film, 7...Tungsten (W) embedded in the contact hole.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上の絶縁膜に電極又は配線用のコンタ
クトホールを形成する第1の工程、上記コンタクトホー
ルの側面及び底面にのみ薄く半導体膜又は第1の金属を
含んだ膜を形成する第2の工程、第2の金属を含んだガ
スを反応させて上記コンタクトホールに上記第2の金属
を選択的に成長させる第3の工程を含むことを特徴とす
る半導体集積回路の製造方法。
(1) A first step of forming a contact hole for an electrode or wiring in an insulating film on a semiconductor substrate, and a second step of forming a thin semiconductor film or a film containing a first metal only on the side and bottom surfaces of the contact hole. A method for manufacturing a semiconductor integrated circuit, comprising step 2 and a third step of reacting a gas containing a second metal to selectively grow the second metal in the contact hole.
(2)第2の工程が、コンタクトホールを含む全面に半
導体膜と第1の金属を含んだ膜と上記絶縁膜とはエッチ
ング特性の異なる塗布膜を表面が平坦化されるように形
成する工程、上記塗布膜をエッチングすることにより上
記コンタクトホールのみ上記塗布膜を残す工程、上記塗
布膜をマスクとして上記半導体膜又は上記第1の金属を
含んだ膜を除去し上記コンタクトホールの側面及び底面
にのみ薄く上記半導体膜又は上記第1の金属を含んだ膜
を形成する工程、上記塗布膜を除去する工程よりなるこ
とを特徴とする特許請求の範囲第1項記載の半導体集積
回路の製造方法。
(2) The second step is a step of forming a semiconductor film, a film containing the first metal, and a coating film having different etching characteristics from the insulating film on the entire surface including the contact hole so that the surface is flattened. , a step of etching the coating film to leave the coating film only in the contact hole; using the coating film as a mask, removing the semiconductor film or the film containing the first metal and etching the coating film on the side and bottom surfaces of the contact hole; 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, further comprising the steps of: forming the semiconductor film or the film containing the first metal only thinly; and removing the coating film.
JP8644186A 1986-04-15 1986-04-15 Manufacture of semiconductor integrated circuit Pending JPS62243324A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8644186A JPS62243324A (en) 1986-04-15 1986-04-15 Manufacture of semiconductor integrated circuit
US07/532,170 US5084413A (en) 1986-04-15 1990-05-29 Method for filling contact hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8644186A JPS62243324A (en) 1986-04-15 1986-04-15 Manufacture of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS62243324A true JPS62243324A (en) 1987-10-23

Family

ID=13887002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8644186A Pending JPS62243324A (en) 1986-04-15 1986-04-15 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS62243324A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0247830A (en) * 1988-08-10 1990-02-16 Toshiba Corp Manufacture of semiconductor device
JPH03230531A (en) * 1990-02-06 1991-10-14 Matsushita Electron Corp Manufacture of semiconductor device
USRE36663E (en) * 1987-12-28 2000-04-18 Texas Instruments Incorporated Planarized selective tungsten metallization system
JP2008227532A (en) * 1993-10-22 2008-09-25 At & T Corp Tungsten deposition process

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE36663E (en) * 1987-12-28 2000-04-18 Texas Instruments Incorporated Planarized selective tungsten metallization system
JPH0247830A (en) * 1988-08-10 1990-02-16 Toshiba Corp Manufacture of semiconductor device
JPH03230531A (en) * 1990-02-06 1991-10-14 Matsushita Electron Corp Manufacture of semiconductor device
JP2008227532A (en) * 1993-10-22 2008-09-25 At & T Corp Tungsten deposition process

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