JPS6223672A - Picture reader - Google Patents

Abstract

PURPOSE:To simplify the optical system by providing a reference color correcting member to a read position in a carrying means carrying an original so as to have only one optical path to use for the optical path from a light source to a photoelectric transducer. CONSTITUTION:An original read position 12 is set at the halfway of the carrying path 6, that is, between an aligning roller 8 and a carrying roller 9 and the reference color correcting plate 13 is provided to the original read position 12, and an original O is carried on the reference color correction plate 13. The light irradiated from a fluorescent light 16 is irradiated to the reference color correction plate 13 or the original O at the original read position 12, the reflected light is led to a lens 21 by a reflection mirror 35 and the image is formed on a line sensor 22. Thus, a white level correction data of the reference color correction plate 13 and the picture of the original O are read at the same read position 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image reading device that optically reads an image of a document.

[Technical background of the invention and its problems] Generally, in this type of image reading device, a document is irradiated with light from a light source, and the reflected light is photoelectrically converted by a photoelectric converter such as a CCO line sensor. It is output after being processed as an image signal. In this case, there are two types: the original moving method, which scans the original while moving it, and the original fixed method, which fixes the original and scans the original while moving the optical system including the light source and photoelectric converter. However, in the following explanation, the case of the original moving method will be described.

By the way, in this type of image reading device, a reference color correction plate is essential as a reference color correction member for reading white level correction data in order to correct the image signal including shading obtained from the photoelectric converter. It is. However, in the past, this reference color correction plate was placed at a position different from the original reading position, which resulted in two optical paths from the light source to the photoelectric converter, complicating the optical system. .

[Object of the Invention] The present invention has been made in view of the above circumstances, and its purpose is to simplify the optical system by eliminating the need to change the optical path from the light source to the photoelectric converter and requiring only one optical path. An object of the present invention is to provide an image reading device that can be used for various purposes.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention is capable of reading an image of a document and adjusting the reference color correction member by installing a reference color correction member at a reading position within a conveyance means for conveying a document. The configuration is such that correction data is read at the same reading position.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

1 and 2 show an image reading device according to the present invention. That is, reference numeral 1 denotes a housing of the image reading device, and a document insertion section 2 is formed at the lower part of the left side (front surface) of the case 1, and a document ejection section 3 is formed at the rear part of the upper surface. A manual feed guide 4 is detachably provided in the document insertion section 2, and the document 0 is inserted along the manual feed guide 4 with its image side (front side) facing upward. Further, the document discharge section 3 is removably provided with a paper discharge tray 5 inclined at a predetermined angle, and the document O to be discharged from the document discharge section 3 with its front and back reversed is placed on the paper discharge tray 5. It is designed to be stored face down. Then, the document insertion section 2 and the document ejection section 3 are provided.
A conveyance path 6 is formed between the original IIO and the original IIO inserted from the document insertion section 2 , which is turned over at the end of the conveyance and guided to the document discharge section 3 . This conveyance path 6 has a diagonal structure and a one-way clutch structure that have the function of moving the inserted document O toward the left reference side.

A pair of paper feed rollers 7 and a pair of aligners with a one-way clutch structure in which the upper roller is made of plastic and the lower roller is made of rubber in order to align the leading edge of the document 0 sent by the paper feed roller 7. A roller 8, a pair of transport rollers 9 having a one-way clutch structure that guides the original O sent by the aligning roller 8 to the original discharge section 3, and an arc-shaped guide that guides the original No. sent by the transport roller 9. A pair of paper discharge rollers 11 are provided in the document discharge section 3 and discharge the document O guided by the guide path 10 to the paper discharge tray 5.

The middle part of the conveyance path 6, that is, the aligning roller 8
A document reading position 12 is set between the transport roller 9 and the document reading position 12, and a reference color correction plate 13 is provided at this document reading position 12.
is provided, and the original O is conveyed over this reference color correction plate 13. This reference color correction plate 13 is for reading white level correction data in order to correct an image signal including shading from a line sensor 22, which will be described later. On the reference color correction plate 13, a glass plate 14 as a transparent member having excellent light transmittance is closely attached. This glass plate 14 is the reference color correction plate 1
Reference color correction plate 13 caused by rubbing between 3 and original O
This is to prevent dirt etc. A document fixing plate 15 is provided above the reference color correction plate 13 and just before the document reading position @12, and is a document fixing member that presses the conveyed document O. This document fixing plate 15 and a glass plate By lightly pressing the original O with 14, the original O is prevented from floating up in front of the original reading position 12. Note that the document fixing plate 15 is made of a thin material with a certain degree of elasticity, such as a polyester film, for example. Further, above the reference color correction plate 13, a green fluorescent lamp 16 as a light source is provided. As shown in detail in FIG. 6, a heat-retaining heater 17 is closely attached to a predetermined portion of the surface of the fluorescent lamp 16 in order to keep the tube wall temperature constant. Temperature-sensitive resistance element (
A thermistor (hereinafter referred to as a thermistor) 36 is attached. The light from the fluorescent lamp 16 is irradiated onto the reference color correction plate 13 or onto the document O conveyed above it, and the reflected light is reflected by the reflection mirrors 18, 19, 20 and the lens 21.
, and is imaged on a COD line sensor (for example, TCD105 manufactured by Toshiba Corporation) 22 serving as a charging converter, and this line sensor 22 converts the optical signal into an electrical signal. Note that the reflecting mirrors 18, 19
．． 20 are each covered with anti-corrosion mats to prevent vibrations. In addition, the fluorescent lamp 16 and the line sensor 22
are arranged in a direction perpendicular to the conveying direction of the document O.

Further, an operation panel 23 equipped with various operation buttons and various indicators is provided on the front surface of the housing 1, and a printed circuit board 24 in which a control circuit and the like are incorporated is provided near the top surface of the housing 1. is installed. In addition, 2
5 is a document detector that detects that the original IO is inserted; 2
Reference numeral 6 denotes a document detector in front of the aligning roller, which detects when the transported original fiO reaches the aligning roller 8;
27 is the document 0 conveyed by the aligning roller 8
28 is a document detector in front of the paper ejection roller that detects the ejection of the document O. Both of these use photointerrupters. Further, reference numeral 29 denotes a stepping motor for supplying power to each drive system, and by the action of a one-way clutch, the paper feed roller 7 is rotationally driven during normal rotation, and the alignment roller 8, conveyance roller 9, and paper ejecting motor are driven when rotating in reverse. The roller 11 is driven to rotate. Further, 30 is a power supply device that generates a DC voltage used for each control, and 31 is a connector for connecting to an external device. It is a connection.

By the way, as shown in FIG. 2, the casing 1 is divided into two parts, an upper casing 1a and a lower casing 1b, with the transport path 6 as a boundary, and both casings 1a and Ib are connected to one of the paper ejection rollers 11. The upper housing 1 is pivoted about a shaft 32 of the
a can be opened upward at a predetermined angle as shown in FIG. Here, the upper housing 1a includes a paper discharge tray 5, an upper roller of the paper feed roller 7, an upper roller of the aligning roller 8, an upper roller of the conveyance roller 9, an upper guide plate of the guide path 10, an original fixing plate 15, a fluorescent Light 16, reflective mirror 18
, 19, 20, a lens 21, a line sensor 22, an operation panel 23, a printed circuit board 24, etc. are respectively provided to constitute the upper unit (second unit) A, and the lower housing 1b includes a manual feed guide 4, a paper feed roller, etc. 7 lower roller, aligning roller 8 lower roller, transport roller 9 lower roller, lower guide plate of guide path 10, paper ejection roller 11, reference color correction plate 13, glass plate 14, document detector 2
5, 26, 27, 28, a stepping motor 29, a power supply device 30, a connector 31, and the like are provided, respectively, to constitute a lower unit (first unit) B. With such a structure, it is possible to easily process the document O that is jammed in the conveyance path 6. Furthermore, when the upper unit A is opened, the upper unit A is designed to have an appropriate opening/closing angle so that the original O stored in the paper ejection tray 5 does not fall. In addition, the upper unit A is a balancer (consisting of a hydraulic machine n, a spring, etc.) provided in the housing 1.
By releasing a locking mechanism (not shown), the upper unit A is automatically opened to a predetermined angle by the action of the balancer 33.
The open state is maintained.

Further, a handle 34 for lowering the device by hand is attached to the lower right side (rear surface) of the housing 1. That is, this handle 34 is used to reduce the burden on the opening/closing fulcrum (shaft 32) of the upper unit A when it is lowered.
It is provided on the side surface where the opening/closing fulcrum is provided.

FIG. 3 shows in detail the portion for reading the image of the original O by the fluorescent lamp 16. As shown in FIG. That is, when the original 0 is conveyed in the direction of the arrow shown in the figure, the original 0 is prevented from floating up in front of the original reading position 12 by the glass plate 14 and the original fixing plate 15.

Therefore, the light emitted from the fluorescent lamp 16 is transmitted to the document reading position 12.
The reference color correction plate 13 or the original 0 is irradiated with the reflected light, and the reflected light is guided to the lens 21 by the reflection mirror 35 and is imaged on the line sensor 22 . In this device, the reference color correction plate 1
The white level correction data of No. 3 and the image of original No. 0 are read at the same reading position 12. In FIG. 5, for convenience of explanation, only one reflecting mirror is used and the optical path length is changed.

FIG. 4 shows a control circuit of the image reading apparatus configured as described above. That is, 41 is a microprocessor that controls the entire device, 42 is an interrupt control circuit that controls interrupts to the microprocessor 41,
The interrupt request signal from the timer 43 is sent to the microprocessor 4.
I am telling 1. A general-purpose timer 43 generates the above-mentioned interrupt request signal and a basic timing signal during document conveyance. 44 is a microprocessor 41 and a timer 4
A crystal oscillator (O
20), 45 is an RO in which all control programs and data tables for operating this device are stored.
M (read-only memory), 46 is a working RAM (random access memory), and 47 is a driving circuit for the line sensor 22, which generates a basic clock pulse for driving the line sensor 22. There is.

48 is an amplifier circuit for amplifying the weak image signal from the line sensor 22, and 49 is a sample and hold circuit, which performs 8 dot/meal processing or 16 dot/hawk processing on the image signal according to the switching signal S1 from the microprocessor 41. It has functions that can be selected. 50 is line sensor 2
A shading correction circuit 51 is an input/output board for correcting the image signal including shading from 2. The shading correction circuit 51 is an input/output board which outputs display data to the operation panel 23 and reads operation buttons. 52 is an input port for reading data from various detectors 53 such as the document detectors 25 to 28 and thermistor 36; 54 is an output port; 55 is an inverter for supplying power to the heat-retaining heater 17, motor 29 and fluorescent lamp 16; A driving circuit 57 is an interface circuit for receiving command data from an external device, transmitting an image signal, etc., and is connected to the connector 31. 58 is a left margin count circuit for counting the left margin during document reading.

FIG. 5 is a detailed diagram of the input/output boat 51, input boat 52, and output boat 54 portions in FIG. 4. That is, 61 is a parallel input/output port, to which a transmission/reception control signal S2 from the microprocessor 41 is supplied. This transmission/reception control signal S2 is a signal for controlling transmission and reception of signals with various detectors, etc. 662 is an original density reading switch that can select the reading level from three levels: dark, normal, and light depending on the density of the original. It is provided on the operation panel 23. 63 is a temperature detection circuit connected to the thermistor 36 that detects the temperature of the tube wall of the fluorescent lamp 16; 64 is an external device power-on detection circuit that detects whether the external device is powered on; 65 is a line sensor A part of the image signal from 22 is extracted and the light from the fluorescent lamp 16 is
This fluorescent lamp light amount detection circuit 65 detects whether the light amount of the fluorescent lamp 16 is in a state where the document can be read, or whether the fluorescent lamp 16 is disconnected. The information is transmitted to the processor 41. Reference numeral 66 denotes a jam detection circuit, which detects the leading edge or the trailing edge of the document 0 based on the detection signals from the detectors 25 to 28, so that the document O passes through the four detectors 25 to 28 within a specified time. Then, it is monitored whether or not the document O is jammed. Reference numeral 67 denotes a ready status indicator that lights up when the device is in a state where it can read a document. Note that the document is in a readable state when the tube wall temperature of the fluorescent lamp 16 has reached a specified value, the light amount of the fluorescent lamp 16 has reached a specified value, and the fluorescent lamp 16 is not disconnected. , there is a document O in the transport path 6.
This is when all the conditions such as "no" are satisfied. 6
8 is a jam status indicator that lights up when the original No. is jammed in the conveyance path 6; 69 is a dark indicator that lights up when the original reading density is at a dark level; and 70 is a dark indicator that lights up when the original reading density is at a normal level. Normal indicator lights up,
71 is a light indicator that lights up when the original reading density is at the light level; 72 is a heater control circuit that controls on/off the heat-retaining heater 17; and 73 is an inverter (not shown) for supplying power to the fluorescent lamp 16. This is an inverter control circuit that performs on/off control. In addition, each of the above-mentioned indicators 67
71 are provided on the operation panel 23.

FIG. 6 shows a device for controlling the tube wall temperature of the fluorescent lamp 16 and its control section. In the figure, 17 is a heater for keeping warm, 3
6 is a thermistor, 37 is a control cord connected to the heat-retaining heater 17 and thermistor 36, 61 is a parallel input/output port that performs input/output processing with the microprocessor 41, 63 is a temperature detection circuit, and 72 is a heater control circuit. , 38 are connectors for connecting the control cord to the temperature detection circuit 63 and the heater control circuit 72.

An example of tube wall temperature control in such a configuration will be described with reference to FIG. 7. When the device is powered on,
After the control of the microprocessor 41, the heater control circuit 72 operates to turn on the heat-retaining heater 17, and the temperature TK detected by the thermistor 36 rises. This shows the state indicated by ■ in FIG. Detection temperature T of thermistor 36
K is monitored by the microprocessor 41 during liJ and compared with the specified tube wall temperature T stored in the data table of the ROM 45. As a result of this comparison, the detected temperature T
When K becomes larger than the specified tube wall temperature T, the heat-retaining heater 1
Control 7 off. This shows the state indicated by ■ in FIG. Moreover, when the detected temperature TK becomes smaller than the specified tube wall temperature T, the heat-retaining heater 17 is controlled to be turned on. This shows the state indicated by ■ in FIG. That is, as shown in FIG. 7, the temperature detection circuit 63, the heater control circuit 72, and the microprocessor 41 turn on and off the heat-retaining heater 17 to keep the tube wall humidity of the fluorescent lamp 16 near the specified value T. It is something to control.

Furthermore, in this device, as a measure to reduce the capacity of the power supply, control of the heat-retaining heater 17 is stopped while the stepping motor 29 is operating. This is because the document reading speed of this apparatus is approximately 3 seconds for an A4 size document, so even if the control of the heat-retaining heater 17 is stopped during this time, the light amount of the fluorescent lamp 16 will not change.

FIG. 8 shows the temperature detection circuit 63 in detail. In the figure, 81 is a variable resistance for current limiting of the thermistor 36;
82 is a current limiting resistor, 83 is a signal voltage stabilizing capacitor, 84 is an amplifier for increasing the gain of the output signal of the thermistor 36, and 85 is an A/D converter. To explain the operation in such a configuration, the thermistor 36 is installed on the tube wall of the fluorescent lamp 16, and detects the tube wall temperature.

The detection current of the thermistor 36 is converted into a voltage by resistors 81 and 82, stabilized by a capacitor 83, and then sent to an amplifier 8.
It is input to the non-inverting input terminal (+) of No. 4. The amplifier 84 increases the gain of the input voltage, converts the analog signal into a digital signal by inputting it to the A/D converter 85, and transmits it to the parallel input/output capotro 1. As described above, the microprocessor 41 detects the tube wall temperature based on the A/D conversion data from the parallel input/output capotrometer 1.

FIG. 9 shows the amplifier circuit 48 and sample hold circuit 49 in FIG. 4 in detail.

That is, O8 is the image signal from the line sensor 22, and D
O8 is an image compensation signal from the line sensor 22, and these signals os and oos are synchronized with the reset pulse R8 input to the line sensor 22. The signals os and oos are amplified by transistors 91 and 92, respectively, and output to their emitters. Resistors R10 and R11 are base current limiting resistors of transistors 91 and 92. The emitters of the transistors 91 and 92 are pulled up to a DC voltage of +12V via resistors R12 and R14, respectively, and the collectors thereof are grounded via resistors R13 and R15, respectively. Capacitors C10 and C11 are bridge capacitors excluding DC components, and resistors R16 and R17 are differential amplifier 9.
3 is the input current limiting resistor. The differential amplifier 93 removes offset bias and reset noise by receiving the emitter output signals of the transistors 91 and 92. SP is sample pulse,
It is output at every other timing of the reset pulse R8. This sample pulse SP is inverted by an inverter circuit 94 and then input to each input terminal of two 4-man NAND circuits 95. The above NAND circuit 95
Each output is connected to one end of a primary coil of a pulse transformer 96, and the other end of the primary coil of this pulse transformer 96 is grounded via a capacitor C,12.

One end of the secondary coil of the pulse transformer 96 has a resistor R
18 and a capacitor C13 in parallel to a terminal 97a of a bridge circuit 97 made up of four diodes. The other end of the secondary coil of the pulse transformer 96 is connected to the terminals 97b1. of the bridge circuit 97. : Directly connected.

On the other hand, the output of the differential amplifier 93 is connected to the base of a transistor 98 via a polar capacitor C14, and also to a resistor R23. A resistor R19 is a resistor for operating the transistor 98. The collector of the transistor 98 is pulled up to a DC voltage of +12V, and the emitter is connected to the terminal 97 of the bridge circuit 97.
c and is pulled down to a DC voltage of -12V via a resistor R20. A terminal 97d of the bridge circuit 97 is connected to a capacitor C14, and is charged and discharged by this capacitor C14. The charging voltage of the capacitor C14 is the uni-juction transistor 9.
It controls 9 gates. The drain of the unijuction transistor 99 is connected to the base of the transistor 100. A resistor R21 is a base-emitter resistor of the transistor 100, and is pulled up to a DC voltage of +12V. The source of the unijuction transistor 99 is connected to the collector of the transistor 100 and connected to a DC voltage of -12V via a resistor R22.
is pulled down.

The collector of the transistor 100 is connected to an analog switch (field effect transistor) 101 via a resistor R24.
connected to the drain of Analog switch 1 above
In case of 01, when a high level voltage is applied to the gate, the resistance between the drain and the source becomes low and the transistor turns on. Conversely, when a low-level voltage is applied, the resistance becomes high and the transistor turns off.

The switching signal @$1 is a signal for selecting the image signal between 8 dots/m processing and 16 dots/rtn processing, and is applied to the gate of the analog switch 101. Resistance R
23 and R24 constitute an adder circuit, which adds the output signal of the differential amplifier 93 and the output signal from the source of the analog switch 101, and sends the added signal S3 to the inverting input terminal of the operational amplifier 102. (−
) is entered. A resistor R25 and a capacitor C15 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier 102, forming a negative feedback circuit. The output of the operational amplifier 102 is connected to input terminals xo and yo of an analog switch (for example, Motorola 4053) 103 via a resistor R26.

Each is connected to ZO. S4 is a crumb pulse, which is connected to the enable terminal E of the analog switch 103.
It is input to NB. When a high-level voltage is applied to the enable terminal ENB, the analog switch 103 generates a low voltage between the input terminal XO and the output terminal X, between the input terminal YO and the output terminal Y, and between the input terminal ZO and the output terminal Z. It becomes a resistance and turns on. Conversely, when a low-level voltage is applied, the resistance becomes high and the transistor turns off. Each output terminal X, Y of the analog switch 103.

Z are connected in common, and this common connection point is connected to the inverting input terminal of the JET input operational amplifier 104 and grounded via the capacitor C17. A capacitor 016 is connected between the inverting input terminal and the output terminal of the operational amplifier 103, forming a negative feedback circuit. The non-inverting input terminal of the operational amplifier 103 is grounded.

The output of the operational amplifier 103 passes through a current-limiting resistor R27 and then through a resistor R28 for current-to-voltage conversion, and is positively fed back to the non-inverting input terminal of the operational amplifier 102. Ss is an image signal output from the operational amplifier 102.

Below, a sample hold circuit 4 having a function of selecting image signal between 8 dots/S processing and 16 dots/S processing is shown below.
The two operations will be explained with reference to the timing chart shown in FIG. In FIG. 10, R8 is the reset pulse input to the line sensor 22, O8 is the image signal from the line sensor 22, and the reset pulse R
8, and a pixel signal of the image signal O8 is output for each pulse of the reset pulse R8.

The sample pulse SP is synchronized with the reset pulse R8, but is output at every other timing of the reset pulse R8. Now, when the switching signal S1 is set to a low level, the analog switch 101 is turned off, and the signal S3 becomes only the output signal of the differential amplifier 93. The image signal O8 has reset noise removed by the differential amplifier 93, and is amplified by the operational amplifier 102. The image signal S5 output from the operational amplifier 102 is output in synchronization with the reset pulse R8. Since the line sensor 22 in this embodiment is capable of reading an A4 size original at a resolution of 16 dots/m, the image signal S5 is an image of an A4 size original at a resolution of 16 dots/m. It will output information.

In this way, by setting the switching signal S1 to a low level, the image signal is processed at a resolution of 16 dots/H.

Next, when processing the image signal at a resolution of 8 dots/a11, the switching signal S1 is set to a high level.

At this time, the analog switch 101 is turned on, and the signal @S3 becomes a sum signal of the output signal of the differential amplifier 93 and the output signal from the source of the analog switch 101. In FIG. 10, SH is a timing pulse for timing one line output time, and is input to the line sensor 22. When the above timing pulse SH is input,
Pixel signals for 3684 pixels are output as the image signal O8.

81, 82, S3, ..., S36*e in Fig. 10
corresponds to the pixel signal excluding the dummy component. For example, the 9th
In the figure, when the pixel signal S1 is output as the image signal O8, the reset noise is removed by the differential amplifier 93, the voltage is converted by the transistor 98, and the voltage is converted to the terminal 97G of the bridge circuit 97.
transmitted to. At this time, the pulse transformer 96 operates from the rise to the fall of the sample pulse SP.
In order to make the potential of the terminal 97d of the bridge circuit 97 equal to the potential of the terminal 97c, a charging/discharging current begins to flow in the circuit composed of the bridge circuit 97, the pulse transformer 96, the resistor R18, and the capacitor C13. Generally, a voltage of the same level as the terminal 97c is stored in the capacitor C14, and sample and hold is performed here. The charge 21IN voltage of the capacitor C14 is converted into voltage by transistors 99 and 100.

Then, in synchronization with the next reset pulse R8, the image signal O
When the pixel signal S2 is output to the pixel signal S2, the differential amplifier 93 removes the reset noise. At this time, since the sample pulse SP is not input, the charging/discharging operation 74N is not performed, and therefore the output signal of the differential amplifier 93 is output to the resistor R23. As a result, the pixel signal obtained by adding the pixel signals 1 and 82 is output as the signal 83 by the addition circuit including the resistor R23 and the resistor R24. This image signal is amplified by the operational amplifier 102, and the output image signal S5 becomes a pixel signal obtained by adding the pixel signals S1 and 82. In the same way, a sum pixel signal of pixel signals S3 and 84, a sum pixel signal of pixel signals Ss and Ss are output, and the process is repeated until a sum pixel signal of pixel signals 53547 and S364B is output. As described above, since the pixel signal is output at every other timing of the reset pulse R8, the image signal S5 is converted into image information with a resolution of 8 dots/sheet for an A4 size document and is output.

FIG. 11 shows the shading correction circuit 50 in FIG.
It shows in detail. Note that here the image signal is 8
An example of a circuit for processing at a resolution of dots/unit is shown below.

That is, 111 is an address counter of the RAM 112, and three 4-bit binary counters 111A, 11
It is composed of 1B and 111G. S6 is a basic clock pulse of the address counter 111, and the timing of the address counter 111 is synchronized with this basic clock pulse S6. 112 is static RA
M (for example, Toshiba Corporation TMM 2016P-2
) and is used to store white level correction data for shading correction of image signals. 11
3 is a 4-bit binary full adder, and by using two of them, an 8-bit binary full adder is constructed. Reference numeral 114 is a data selector multiplexer having a three-state output, and two of them are used to drive an 8-bit data line. S7 is a RAM write signal, which is input to the output control terminal OC of the data selector/multiplexer 114 and the write enable terminal WE of the RAMI 12. S8 is a select signal, and the data selector multiplexer 11
It is input to the select terminal S of No. 4. The data selector/multiplexer 114 outputs output terminals Y (IY, 2Y, 3Y) when the select signal S8 is at high level.

The state of input terminal B (18, 28, 38, 4B>) can be output to output terminal Y (1Y, 2Y, 3Y) when the select signal S8 is low level.

The status of input terminal A (IA, 2A, 3A, 4A) can be output to 4Y). Reference numeral 115 denotes a D-type flip-flop circuit, which can latch eight pieces of data in response to a trigger signal of the RAM enable signal S9.

The RAM enable signal S9 is also input to the 7 output enable terminal W of the RAMI 12.

Reference numeral 116 is a high-speed 8-bit D/A converter (for example, TD62901P manufactured by Toshiba Corporation), which converts a digital input signal into an analog DC current. This D/A
One output terminal of the converter 116 is connected to a four-channel demultiplexer (eg, Motorola 4052) 117 and a non-inverting input terminal of a differential amplifier 118 via a resistor R29. Resistance R30, R31, R32
The series circuit is a circuit that converts the output current of the D/A converter 116 into a voltage. The voltages divided by the resistors R30, R31, and R32 are input to input terminals XO, Xi, and X2°×3 of the demultiplexer 117, respectively. The selection input terminals A and B of the demultiplexer 117 are supplied with the original density switching signal S10. S11 is input,
By inputting a combination of high level and low level signals to the select input terminals A and B, the output terminal X becomes the input terminals XO, Xi, X2 . It turns on with one of X3. The output terminal X of the demultiplexer 117 is connected to the non-inverting input terminal of the differential amplifier 119. The inverting input terminals of the differential amplifiers 118 and 119 and the non-inverting input terminal of the differential amplifier 120 are commonly connected, and the image signal S5 is input to this common connection point.

The output of the differential amplifier 118 is the output of the binary full adder 11
3 is input to the carry input terminal CO. The differential amplifier 119 outputs an image signal that has undergone shading correction processing. This image signal is subjected to A/D conversion processing at the next stage and output to an external device. A divided voltage of DC voltage +5V is input to the inverting input terminal of the differential amplifier 120 through a variable resistor R33. Differential amplifier 1 above
The output of 20 is connected to the parallel input/output capotro 1 (see FIG. 5).

Next, in such a configuration, a process in which white level correction data for performing shading correction is accumulated in the RAM 112 will be described with reference to timing charts shown in FIGS. 12 and 13. In FIGS. 12 and 13, SH is a timing pulse for one line output time, which is input to the line sensor 22. In FIG. As shown in the twelfth factor, it is assumed that the select signal S8 is at a high level when the timing pulse SH is input. When the select signal S8 becomes high level, the select terminal S of the data selector/multiplexer 114 becomes high level, and the output terminal Y (1Y, 2Y.

3Y, 4Y), input terminal 8 <IB, 28.38°4
It becomes possible to output the state of B). Input terminal B (IB, 28
．． 3B, 4B) are all grounded, so the output terminal Y
All data (IY, 2Y, 3Y, 4Y) are at low level. When the RAM write signal S7 becomes low level, input terminal B (1B).

2B, 3B, 4B) state is output terminal Y (IY.

2Y, 3Y, 4Y). At this time, RAM1
12 write enable terminal WT also becomes low level,
Since the RAM enable signal S9 is at high level, the output terminals Y (1Y, 2Y.

3Y, 4Y) data is stored in the RAM 112.

RAM11 according to the timing of basic clock pulse S6.
Address 2 is counted by "+1", so
The data in RAMI 12 is cleared by repeating the above process until the next timing pulse SH arrives. As shown in FIG. 13, the select signal S8 becomes low level when the next timing pulse SH is input.

When the select signal S8 becomes low level, the select terminal S of the data selector/multiplexer 114 becomes low level, and the output terminals Y (IY, 2Y, 3Y, 4Y) are connected to the input terminals A (IA, 2A).

3A, 4A) can be output. Therefore, the output signal of the binary full adder 113 is input to the input terminals A (1A, 2A, 3A, 4A). RAM write signal S
7 is at a high level, the write enable terminal n of the RAM 112 is at a high level, and at this time, the RAM enable signal S9 is at a low level, so the RAM 112 enters a read state and data at the set address is output. This output data is latched by the flip-flop circuit 115 in response to the RAM enable signal S9. The latched contents of the flip-flop circuit 115 are the input terminal A (A1.A2) of the binary full adder 113.
．． A3. A4) and the D/A converter 11
6, and an output current having a value commensurate with the digital input signal is output from the output terminal 1OUT. D/A converter 1
The output current of 16 is converted into a voltage by resistors R30, R31, and R32, and the input image signal 85 (reference color correction plate 13
read signal) by a differential amplifier 118.

As a result of this comparison, when the output of the differential amplifier B118 becomes high level, it is carried to the binary full adder 113, and when the output of the differential amplifier 118 becomes low level, it is carried to the binary full adder 113.
is not carried forward. The binary full adder 113 performs an operation on the output signal of the flip-flop circuit 115 in consideration of the carry amount of the differential amplifier 118, and outputs the result of the operation. When the RAM write signal S7 changes from high level to low level, input terminals A (IA, 2A, 3A) of the data selector/multiplexer 114 are input.

4A) is the output terminal Y (1Y, 2Y, 3Y, 4Y)
It becomes possible to output to. At this time, the write enable terminal Wτ of the RAM 112 is also at a low level, so the data at the output terminals Y (1Y, 2Y, 3Y, 4Y) is transferred to the RAM 112.
112. Since the address of the RAM 112 is counted by "+1" according to the timing of the basic clock pulse S6, the data in the RAM 12 is rewritten to the shading correction data value by the time the next timing pulse SH arrives.

In this way, each time the timing pulse SH comes, R
By repeating the process of reading out the data in the AM 112, performing calculations on the shading correction data value by the reference color correction plate 13, and writing the calculation results back into the RAMI 12, the data in the RAM 112 is finally stored in the fluorescent lamp 16. A shading correction data value is written in consideration of the spectral characteristics of the line sensor 22 and variations in the photosensitive portion of the line sensor 22. The circuit configuration is such that rewriting of the shading correction data value in the RAM 112 starts after the original O passes the original detector 27 and ends before the original O reaches the original reading position 12. The shading correction data values in the RAM 112 are rewritten each time the original O is transported.

Next, a description will be given of the state in which reading the image of document 0 is started. When the select signal S8 becomes low level, the select terminal S of the data selector/multiplexer 114 becomes low level, and the output terminal Y (IY) becomes low level.

2Y, 3Y, 4Y) to input terminal A (1A: 2A.

3A, 4A) can be output. When the RAM write signal S7 becomes high level, the write enable terminal WE of the RAM 112 becomes high level, and at this time, the RAM
Since the enable signal S9 becomes low level, RAM1
12 is in a read state, and the shading correction data of the set address is output. This output data is latched by the flip-flop circuit 115 in response to the RAM enable signal S9. The latched contents of the flip-flop circuit 115 are as follows:
The signal is fed back to the input terminal A (A1.A2.A3°A4) of No. 3 and is also input to the D/A converter 116. D/A
The output current of converter 116 is controlled by resistors R30, R31, R32.
r'l voltage IC transforms fLl'' and is input to the non-inverting input terminal of the demultiplexer 117 and the differential amplifier 118.

The image signal S5 is input to the inverting input terminal of the differential amplifier 118, but at this time, since the potential of the inverting input terminal is higher than the potential of the non-inverting input terminal, the output of the differential amplifier 118 becomes low level, and the 2 A carry to the base full adder 113 does not occur. The demultiplexer 117 receives the original density switching signal 810. S11 causes output terminal X to become input terminal XO,
1. X2. Any of X3 turns on. The output signal of the demultiplexer 117 is input to the non-inverting input terminal of the differential amplifier 11'9, and compared with the image signal 85 (reading signal of original O) input to the inverting input terminal. At the output of 119, an image signal obtained by applying shading correction to the original 8 read image signal appears.

FIG. 14 shows a method of correcting an image signal by the shading correction circuit 50. The waveform in the figure is the line sensor 22
The image signal obtained by amplifying the image signal from the amplifier circuit 48 is shown. This signal has a waveform corresponding to one period of the timing pulse SH for one line output time. Reference numeral 121 indicates a waveform of an image signal obtained by reading a document, and reference numeral 122 indicates a shading waveform for correcting the image signal. A high level output is obtained where the image signal waveform is larger than the shading waveform, and a low level output is obtained where the image signal waveform is smaller than the shading waveform. By using the image signal correction method described above, an effect similar to that obtained by performing calculations using an integrating circuit can be obtained.

Next, a method of switching the reading density according to the density of the original will be explained. In FIG. 11, the original density switching signal S10
．． S11 is output from the microprocessor 41. The operation of the demultiplexer 117 is as follows: select input terminal A,
When B are both low level, output terminal X and input terminal xO are on, and when select input terminal A is high level, B
When is at low level, output terminal When both are at high level, the output terminal X and the input terminal x3 are in an on state. To read a low density original, set the original density reading switch 62 to the light state.

Then, the select input terminal A of the demultiplexer 117
, B outputs the value of the output terminal x (y input terminal x 2).As a result, the reference input of the differential amplifier 119 can be kept low, so the shading waveform 1 in FIG.
22 becomes low, and the output of the differential amplifier 119 becomes large. Further, in order to read a document with a high density, the document density reading switch 62 is set to the dark state. Then, by selecting the select input terminals A and B of the demultiplexer 117, the output terminal X outputs the value of the input terminal XO.

As a result, the reference input of the differential amplifier 119 becomes higher by 1.1, so the level of the shading waveform 122 in FIG. 14 becomes higher, and the output of the differential amplifier 119 becomes smaller.

Further, in order to read a document having a reference density, the document density reading switch 62 is set to the normal state. Then, by selecting the select input terminals A and B of the demultiplexer 117, the value of the output terminal X & input terminal x 1 is output. As a result, the reference input of the differential amplifier 119 becomes a value between the light state and the dark state, so the differential amplifier 119
The output is at a level between the above light state and dark state.

Next, the function of the differential amplifier 120 in FIG. 11 will be explained.
By setting the reference voltage level of 0 to a predetermined value, the image signal S5 is input to the non-inverting input terminal of the differential amplifier 120. Therefore, by inputting the output signal of the differential amplifier 120 to the microprocessor 41, , it is possible to detect the on/off state of the fluorescent lamp 16 and the state of the amount of light.

That is, this circuit constitutes the fluorescent lamp light amount detection circuit 65.

FIG. 15 shows the left margin count circuit 58 in FIG. 4 in detail. That is, 131 is a DIP switch for setting the initial setting value of the left margin count value, and 132 is a DIP switch for setting the data line to DC voltage +
This is a block resistance element for pulling up to 5.

The value of the dip switch 131 is determined by each data input terminal A, B, C, D of the 4-bit binary counter 133.134.
has been entered. The carrier terminal CO of the counter 133 is connected to the enable terminal ET of the counter 134, and carries up from the counter 133 to the counter 134. A timing pulse SH is input to each load terminal of the counters 133 and 134. The output terminal QD of the counter 134 is connected to the counter 13
3 and 134 enable terminals EP, and is also connected via an inverter circuit 135 to a clock terminal GK of a D-type flip-flop circuit 136. The counters 133 and 134 have clock terminals C
It operates by inputting a clock pulse CP to K. The data input terminal of the flip-flop circuit 136 is pulled up to a DC voltage of +5. The output terminal Q of the flip-flop circuit 136 is connected to the data input terminal of a D-type flip-flop circuit 137. Output terminal Q of the flip-flop circuit 136
A horizontal synchronizing signal NSC is outputted from. The flip-flop circuit 137 operates by inputting a clock pulse CP to its clock terminal CK. The output terminal Q of the flip-flop circuit 137 is connected to the clear terminal CLR of the flip-flop circuit 136, and the output terminal Q of the flip-flop circuit 137 is connected to the clear terminal CLR of the flip-flop circuit 136.
are connected to each load terminal. Above counter 13
8 data input terminals A, B, C, and D are each grounded. Data input terminals A and B of the counter 139 are pulled up to a DC voltage of +5V, and data input terminals C and B of the counter 139 are pulled up to a DC voltage of +5V.
D is grounded. Data input terminals A and D of the counter 140 are pulled up to a DC voltage of +5V, and data input terminals B and C are grounded. The above counter 138
．． 139.degree. and 140 perform carry by connecting the carrier terminal CO to the enable terminal ET. The counters 138, 139, and 140 operate by inputting a clock pulse CP to their clock terminals CK. Carrier terminal C of the counter 140
○ indicates that the counter 138 .
139 and 140 are connected to each enable terminal EP. A strobe pulse STB is output from the output terminal QC of the counter 138. This strobe pulse S
During the period when TB is being output, the image signal becomes valid data.

Next, in such a configuration, the left margin counting operation will be explained with reference to the timing chart shown in FIG. 16. The number of pixels output per line from the line sensor 22 is 3684 pixels as described above. The line sensor 22 is configured to first output dummy outputs for 32 pixels and image signals, and then output dummy outputs for 4 pixels, depending on the timing of the timing pulse SH. In this device, the image reading width is 219m5+, so the effective portion of the pixel signal is 216 bytes, or 3456 pixels. Counters 133 and 134 count time t1, and the left margin is adjusted by discarding 32 dummy pixels and invalid data from the pixel data. After counting time t1, horizontal synchronizing signal H8C is output. Strobe pulse S by counter 138゜139.140
After outputting TB and outputting the image reading width 219M, the counters 138, 139, and 140 stop operating from run 1, so during the time t2 until the next timing pulse SH comes, invalid data and 4 pixels are output. The dummy portion is rounded down. By doing this, it is no longer necessary to send pixel signals read from areas other than the image reading width to an external device, and there is no need for the external device to have a circuit configuration that newly selects only valid pixel data.

FIGS. 17 and 18 show details of commands and statuses used in this device.

SR1, SR2, and SR3 in FIG. 17 are status request commands corresponding to status 1, status 2, and status 3 in FIG. 18, and SST is a command for instructing this apparatus to start reading a document. In Figure 18,
The document reading density is a status that indicates the state of the document density reading switch 62. The document set is a status that indicates that it has detected that document 0 has been inserted into the document insertion section 2. During warm-up, this device is a status that indicates the state of the document density reading switch 62. The status indicates that the state is in the best condition for reading the document O, and the fluorescent lamp burnout indicates that the light intensity of the fluorescent lamp 16 has fallen below the limit for reading the document O, or that the fluorescent lamp 16 has burned out. The status document jam is a status indicating that document 0 has jammed in the conveyance path 6, and the 8/16 conversion is a status indicating whether the document reading resolution is 8 dots/m or 16 dots/m.

FIGS. 19 and 20 show a flowchart of a suburban program for operating this device, which will be explained with reference to FIG. 21. Note that FIG. 21 shows the position of each document detector with respect to the conveyance path 6 and the document conveyance time between these positions, Pl is the position of the document detector 25, and R2
indicates the position of the original detector 26, R3 the position of the original detector 27, and R4 the position of the original detector 28, respectively.

T1 is the time it takes for document 0 to reach from position P1 to R2, T2 is the time it takes for document 0 to reach from position P2 to the center position of aligning roller 8, and T3 is the time from the center position of aligning roller 8 to position P3. T4 is the time it takes to reach the document reading position 12 from the position P3, T5 is the time it takes to reach the document reading position 12 from the document reading position 12, and T6 is the time it takes to reach the document reading position 12 from the position P4. The time it takes to reach the center position is shown respectively.

First, the operation from turning on the power to entering the standby state will be explained. Now, when the power is turned on, the process proceeds to step A1. In step A1, it is determined whether or not the upper unit A is in the open state by checking the state of the upper unit open/close detection switch (not shown). If the upper unit A is in the open state, the upper unit is set to the oven state; If so, proceed to step A2. In step A2, it is determined whether each of the document detectors 25 to 28 is in the off state or not. If even one of the document detectors 25 to 28 is in the off state, it is assumed that a jam has occurred and the document is in a jam state. If all of the document detectors are in the off state, step A3
Proceed to. In step A3, the heat-retaining heater 17 of the fluorescent lamp 16 is turned on, and the process proceeds to step A4. In step A4, preheating of the fluorescent lamp 16 is turned on, and the process proceeds to step A5. In step A5, the fluorescent lamp 16 is turned on, and the process proceeds to step 86.

In step 86, time TX is set in the soft timer, the timer is started, and the process proceeds to step A7. In step A7, it is determined whether the fluorescent lamp 16 has reached a predetermined amount of light, and if it has not, the process proceeds to step 88. In step 88, it is determined whether or not the above-mentioned time TX has elapsed. If it has not elapsed, the process returns to step A7, and if it has elapsed, it is determined that there is an abnormality and a serviceman call state is established. In step A7, if the prescribed light amount has been reached, the process proceeds to step A9. In step 80, the fluorescent lamp 16 is turned off and placed in a standby state.

Next, the operation when the original fiO is inserted in the standby state will be described. In step A10, it is determined whether or not the document detector 25 at position P1 is turned on. If it is turned on, it is determined that the document O has been inserted, and the process proceeds to step A11. In step A11, the fluorescent lamp 16 is turned on, and the process proceeds to step AI2. In step A12, by rotating the stepping motor 29 in the normal direction, the paper feed roller 7 is operated to start conveying the inserted document O, and in step A
Proceed to step 13. In step A13, the time is delayed by T1,
Proceed to step A14. In step A14, position P2
It is determined whether or not the original document detector 26 is turned on. If it is not turned on, it is determined that a jam has occurred and a document jam state is set. If it is turned on, the process proceeds to step A15. Step A
In step A15, the process is delayed for a time T2 and proceeds to step A16.

In step A16, the document setting status is set and the stepping motor 29 is turned off, and the process proceeds to step A17. In step A17, it is determined whether or not a reading start command has been received, and if it has been received, step A18
Proceed to. In step A18, the stepping motor 29
By reversing the original O
After that, the process proceeds to step A19. Step A1
In step 9, the process is delayed for a time T3 and the process proceeds to step A20. In step A20, it is determined whether or not the document detector 27 of position 11P3 is turned on. If it is not turned on, it is determined that a jam has occurred and the document is jammed. If it is turned on, the process advances to step A21. In step A21, the process is delayed for a time T4, and the process proceeds to step A22. In step A22, the original O
, and the process proceeds to step A23. Step A
23, a predetermined period of time To after the document detector 27 is turned on.
It is determined whether the time required for the maximum length document to pass through the document detector 27 has elapsed, and if it has passed, it is determined that a jam has occurred and the document is in a jam state. If not, the process proceeds to step A24. In step A24, it is determined whether or not the document detector 27 at position P3 is turned off. If it is not turned off, the process returns to step A22 to continue reading; if it is turned off, step Proceed to A25.

In step A25, the time T4 is delayed, and step A2
Proceed to step 6. In step A26, reading of document 0 is finished, the fluorescent lamp 16 is turned off, and the document set status is canceled, and the process proceeds to step A27. Step A
In step A27, the process is delayed for a time T5 and proceeds to step A28.

In step A28, it is determined whether or not the document detector 28 of position 11P4 is turned off. If it is not turned off, it is determined that a jam has occurred and the document is jammed. If it is turned off, the process advances to step A29. In step A29, the process is delayed for a time T6 and the process proceeds to step A30. In step A30,
Turn off the stepping motor 29 and return to the standby state.

Note that FIGS. 20(a), 20(b), and 20(c) are flowcharts showing processing in the upper unit open state, document jam state, and serviceman call state.

In this way, by installing the reference color correction plate at the reading position in the conveyance path that conveys the original, it is configured to read the image of the original and read the correction data from the reference color correction plate at the same reading position. As a result, there is no need to change the optical path from the fluorescent lamp to the line sensor, and only one optical path is required, making it possible to simplify the optical system. Furthermore, by bringing the glass plate into close contact with the reference color correction plate, it is possible to prevent the reference color correction plate from becoming dirty due to misalignment between the original and the reference color correction plate, thereby eliminating the need for cleaning and replacement.

In the above embodiment, the reference color correction plate and the glass plate for preventing staining thereof were installed separately.
For example, they may be integrated as shown in FIG. That is, 151 is a glass plate as a light transmitting member having excellent light transmittance corresponding to the glass plate 14, and a material having a light reflectance comparable to that of the reference color correction plate 13 is coated on the back surface of this glass plate 151. By coating or vapor depositing,
A reference color correction plate 111152 is formed, and even in this case, the same function as the above embodiment can be achieved. Note that, as the above-mentioned substance, for example, aluminum oxide can be considered.

[Effects of the Invention] As detailed above, according to the present invention, there is no need to vary the optical path from the light source to the photoelectric converter, and only one optical path is required, thereby providing an image reading device in which the optical system can be simplified. can.

[Brief explanation of the drawing]

1 to 21 are for explaining one embodiment of the present invention, and FIG. 1 is a longitudinal sectional side view of an image reading device, and FIG.
The figure shows the upper unit in Fig. 1 opened, Fig. 3 shows the image reading part in detail, Fig. 4 is a block diagram showing the configuration of the control circuit, and Fig. 5 shows the input in Fig. 4. , a block diagram showing the output boat part in detail, FIG. 6 is a diagram showing a device for controlling the tube wall temperature of a fluorescent lamp and its control unit, and FIG. 7 is a timing chart for explaining an example of controlling the tube wall temperature. 8 is a configuration diagram of the temperature detection circuit, FIG. 9 is a configuration diagram showing details of the amplifier circuit and sample hold circuit in FIG. 4, and FIG. 10 is a timing chart for explaining the operation of the sample hold circuit. , FIG. 11 is a detailed configuration diagram of the shading correction circuit in FIG. 4, FIGS. 12 and 13 are timing charts for explaining the operation of the shading correction circuit, and FIG.
The figure is a diagram for explaining the method of correcting the image signal by the shading correction circuit, FIG. 15 is a block diagram showing the left margin count circuit in detail in FIG. 4, and FIG. 16 is a diagram explaining the operation of the left margin count circuit. Figures 17 and 18 are timing charts showing commands and status in detail, Figures 19 and 2 are timing charts for
Fig. 0 is a control program flowchart for explaining the overall operation, Fig. 21 is a diagram showing the position of each document detector with respect to the conveyance path and the document conveyance time between those positions, and Fig. 22 is a diagram showing the present invention. FIG. 7 is a perspective view of main parts for explaining another embodiment of the present invention. O...Original, 2...Original insertion section, 3.
...Document discharge section, 6...Transport path, 12.
...Original reading position, 13...Reference color correction plate (reference color correction member), 14...Glass plate (transparent member), 16...Fluorescence Light (light source), 22...
...Line sensor (photoelectric converter), 151...
...Glass plate (light-transmitting member), 152...Reference color correction thin film. Applicant's representative Patent attorney Takehiko Suzue Figure 5 Figure 8 Figure 7 (a) Figure 19 (b) Figure 19 (C) Figure 19 Figure 20

Claims (4)

[Claims] (1) a conveying means for conveying a document having an image to be read;
a light source that irradiates light onto the image surface of the original that passes through a reading position provided on the conveying means; a photoelectric converter that receives light from the original that is irradiated by the light source and converts it into an electrical signal; a reference color correction member provided at the reading position for reading white level correction data in order to correct an image signal including shading obtained from the photoelectric converter; An image reading device characterized in that data for correction of a correction member is read at the same reading position. (2) The image reading device according to claim 1, wherein the original is conveyed over a reference color correction member. (3) A patent claim characterized in that a light transmitting member having excellent light transmittance is brought into close contact with the reference color correction member so as to cover it, and the original is conveyed over the light transmitting member. The image reading device according to item 1. (4) The reference color correction member is a thin film that is closely attached to the back surface of a light-transmitting member with excellent light transmittance, and the document is conveyed on the surface of this light-transmitting member. An image reading device according to claim 1.