JPS62235850A - Signal disconnection detection circuit - Google Patents

Abstract

PURPOSE:To stably detect the disconnection of an input signal by providing a timing extraction circuit and a signal disconnection detector. CONSTITUTION:An identification circuit 10 outputs the output (c) of a comparator circuit 9 in synchronization with a clock output (h) from the timing extraction circuit 14. The signal disconnection detector 17 is comprised of a counter 15 to input the clock output (h) being the output of the timing extraction circuit 14, and a decision circuit 16 that inputs the output (j) of the counter 15 and the signal output (g) of the identification circuit 10 and outputs a signal disconnection detection signal (i). The decision circuit 16 checks the changing point of the output signal (g) at an interval of generating the pulse of a counted output (j). If no change occurs during one period of the counted output (j), the circuit 16 dicides that the signal is disconnected, and changes the signal disconnection detection output (i) at a level 'L'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Foreword and Object of the Invention] The present invention relates to a signal disconnection detection circuit, and particularly to a signal disconnection detection circuit suitable for detecting a signal disconnection in an optical receiving circuit! be.

First, the prior art will be explained using FIGS. 3 and 4. In FIG. 3, an optical signal a is converted into an electrical signal by a light receiving element 1, amplified by a main amplifier 4 via a preamplifier 2° capacitor 3, and then amplified by a main amplifier 4.
The DC voltage of the signal is determined by the resistor 6.7, and input to the comparator 9 whose threshold voltage is determined by the reference voltage J,f8. A signal output C is generated from 9.

On the other hand, a part of the output of the main amplifier 4 is transmitted to the peak detection circuit 2.
1, the output d of the peak detection circuit 21 is converted into a voltage proportional to the peak level by a rectifying capacitor 22, and is input to a comparator 24 whose threshold voltage is determined by a reference voltage 23. Accordingly, a signal-off detection signal e that switches to "H" level or "off" level depending on the presence or absence of the signal can be obtained.

Note that the capacitor 3.5 is for DC cutoff.

However, if the peak value of the signal from the main amplifier 4 increases, the output voltage (DC) d of the peak detection circuit 21 increases, and the signal disconnection detection signal e reaches the "H" level. According to the circuit shown in the figure, it is determined that the signal is disconnected when the AC amplitude becomes smaller than a predetermined level.

In short, the configuration shown in FIG. 3 has a major problem in that the temporal response is slow because the peak value of the signal is detected.

FIG. 4 is a time chart of operating waveforms of signals ae of each part in FIG. 3, where ae corresponds to signals ae of FIG. 1. First, from time t1 to time 12, Mitsunobu @a is input and the hour wheel is rlJ, [OJ is repeated], t
Consider the case where there is no optical signal a after time z. The input of the comparator circuit 9 is cut off from the direct current component as shown in FIG.

The change to a DC component between t2 and t3 is due to the time required for charging and discharging the coupling capacitor 5, and is determined by the time constant depending on the capacitance of the capacitor 5 and the load. At this time, since the average level of noise matches the threshold value of the comparison circuit 9 after t3, random noise pulses are outputted to the output C after t3.

On the other hand, the output d of the peak detection circuit 21 has a long hold time, so the fall time is particularly long, and Tz>Ls
Therefore, there was a problem in that it was not possible to detect signal interruption before noise was generated in the output. In other words, as shown in FIG. 4e, the time point t4 when the signal disconnection detection signal e reaches the "high" level is delayed from the time point t3 at which noise generally starts to occur.

In this case, it is impossible to determine whether the received signal is valid or not, so a method of detecting signal interruption at an earlier point in time is needed.

Incidentally, at the time of signal input, there is no such problem because the signal e becomes normal if the necessary time is waited after the rise of the signal e.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and provide a signal disconnection detection circuit that can stably detect input signal disconnection.

[Summary of Da 10] Book fiI! ? 1 is characterized by a timing extraction circuit that branches and inputs the output from the amplifier of the optical receiving circuit and sends out a reference clock, and a pulse output when the clock signal output from this timing extraction circuit is counted by a predetermined number of bits. The output of the comparison circuit of the optical receiver circuit and the clock signal from the timing extraction circuit are input to the output counter of the timing extraction circuit and the clock signal from the timing extraction circuit before the output of the timing extraction circuit disappears, and a signal is output in synchronization with the clock signal. a determination circuit that inputs the output of the identification circuit that sends out the signal and the output of the counter, and determines that the signal is disconnected when the output of the identification circuit does not correspond to one cycle of the pulse of the output of the counter. The structure consists of a signal disconnection detector.

[Example] The present invention will be described in detail below with reference to the example shown in FIG. 1 and FIG. 2.

FIG. 1 is a block diagram showing an embodiment of the signal disconnection detection circuit of the present invention, and FIG. 2 is a time chart of the operation waveforms of the various signals shown in FIG. In FIG. 1, an optical signal a is converted into an electrical signal by a light receiving element 1, and a preamplifier 2
．． The signal is amplified by the main amplifier 4 via the capacitor 3, and the signal is amplified by the resistor 6.7 via the capacitor 5.
The DC bias of b is determined, and the threshold voltage is determined by the reference voltage 8.
is digitized and becomes a signal output C, which is sent to the identification circuit 10.
A signal output Q is output from the identification circuit 10.

By the way, a part of the μ signal output through the capacitor 5 is transmitted through the full wave rectifier circuit 11° narrow band band pass filter (LC resonant circuit, crystal filter, S
The fundamental wave component (a line spectrum is obtained by nonlinear operation) that is inputted to a timing extraction circuit 14 consisting of an AW filter (such as an AW filter) 12 and a limit amplifier 13 and subjected to full-wave rectification by a full-wave rectification circuit 11 is converted into a band. Extracted as signal f by pass filter 12,
The limit amplifier 13 shapes the signal into a pulse and outputs a clock output.

Note that the identification circuit 10 outputs the output C of the comparison circuit 9 in synchronization with the output from the timing extraction circuit 14. That is, it is a so-called 3R optical repeater in which a timing extraction circuit 14 and an identification circuit 10 are added to the conventional circuit, and a signal disconnection detector 17 is newly added. Signal disconnection detector 1
7 is the output of the timing extraction circuit 14 or the output of the counter 15 and the output of the counter 15.
The signal output signal q of the identification circuit 10 is inputted to the determination circuit 16, which outputs the signal disconnection detection signal 1.

When the signal is cut off, the output f of the bandpass filter 12 is
As shown in FIG. f, although it is attenuated, the time constant is large; for example, in the case of a crystal filter with Q=1000, it takes a value of about 20 to 50 μs.

Therefore, the clock output will continue to be output for a while after the signal is cut off.

On the other hand, the signal disconnection detector 17 is a circuit that detects a signal disconnection from the signal output Q and the clock output, and functions as follows. The counter 15 has n bits of clock output (
For N, the signal code “Q II , 111N
A pulse j is generated every 1J (selected larger than the number of consecutive bits) (FIG. 2j). The determination circuit 16 is a circuit that checks the change point of the output signal Q during the pulse generation interval of the count output j, and is a circuit that checks the change point of the output signal Q during the pulse generation interval of the count output j.
It is determined that the signal is disconnected when there is no change, and the signal disconnection detection output i
is changed to the "L" level (Fig. 2 i).

The output C of the comparator circuit 9 is the signal shown in FIG.
Perform an action that continues at the 1″ level.

Furthermore, since this time constant usually takes a value of about several μs, it can be set to a value sufficiently large with respect to the number of bits N for counting the clock. Therefore, signal disconnection detection can be performed stably.

In addition, in the circuit shown in Figure 1, the value of N can be easily changed, so you can reduce N to speed up detection, or increase N to avoid responding to instantaneous signal interruptions. It becomes possible to do something like this.

In addition, in the above-mentioned present invention, since time is counted using the timing extraction port 14, it is difficult to count a long time. This is because the clock will eventually disappear due to signal interruption. Therefore, it cannot be used in a format such as NRZ, where the code used has a long series of "0" or "1".

According to the embodiment of the present invention described above, (1) Since peak detection repetition is not used, the time required for detection is short.

(2)Also, the mti required for detection can be changed to some extent by the logic circuit, so it is possible to reduce N to shorten the time until detection, or increase N to increase stability and prevent malfunctions. It can be made difficult.

(3) The circuit configuration is simple because the extraction, output, and signal output are used to detect a signal disconnection. is using.

That is, it utilizes the fact that the fundamental wave extracted by the bandpass filter 12 can be extracted for a while even after the signal is cut off. ).

[Effects of the Invention rA] As explained above, according to the present invention, it is possible to stably detect input signal disconnection, and the circuit configuration is ty! i
This has the effect of being tn.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the signal disconnection detection circuit of the present invention, FIG. 2 is a time chart of the operation waveforms of the various signals in FIG. 1, and FIG. 3 is an example of a conventional signal disconnection detection circuit. The block diagram shown in FIG. 4 is a time chart of the operation waveforms of the signals of each part shown in FIG. 1... Light receiving element. 2...Preamplifier. 3.5... Capacitor. 4... Main amplifier. 9... Comparison circuit. 10...Identification circuit. 11...Full wave rectification n-way. 12...Band pass filter. 13...Limit amplifier. 14...Timing extraction circuit. 15...Counter. 16... Judgment circuit. 17... Signal disconnection detector. Agent Patent Attorney 蒲 1) Toshi Kogun 1 Diagram Nz Concave

Claims (1)

[Claims] (1) In an optical receiving circuit in which a light receiving element, an amplifier, and a comparator circuit are connected through capacitors, the timing at which the output from the amplifier is branched and input to send out a reference clock is determined by the extraction circuit and the timing at which the output from the amplifier is branched and input. A counter that sends out a pulse output when a predetermined number of bits of the clock signal that is the output of the extraction circuit is counted; and a counter that sends out a pulse output when the clock signal that is the output of the extraction circuit is counted; When the output of the identification circuit which inputs and sends out a signal output synchronized with the clock signal and the output of the counter are input, and the output of the identification circuit has no signal for one period of the pulse of the output of the counter. 1. A signal disconnection detection circuit comprising: a signal disconnection detector comprising a determination circuit that determines that a signal is disconnected.