JPS62235750A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62235750A JPS62235750A JP61080518A JP8051886A JPS62235750A JP S62235750 A JPS62235750 A JP S62235750A JP 61080518 A JP61080518 A JP 61080518A JP 8051886 A JP8051886 A JP 8051886A JP S62235750 A JPS62235750 A JP S62235750A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- current
- circuit
- power supply
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000002131 composite material Substances 0.000 claims abstract description 22
- 239000000126 substance Substances 0.000 claims abstract description 5
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に集積回路内の回路
ブロックごとの電源供給の接断のできる半導体集積回路
に関する０
〔従来の技術〕
使用者が自由にプログラム可能なバイポーラのプログラ
ム可能読出し専用メモリ（Ｐ几ＯＭ）やフィールドプロ
グラマブルロジックアレイ（ＦＰＬＡ）を使用するにあ
たり、これらの集積回路では、プログラム書込み時のみ
に使用する書込み回路を有し、通常の読出し動作時にも
電力を供給しているＯすなわちプログラム書込み時以外
でも不必要な電力を供給しつづけている。プログラム書
込み以外の集積回路でも使用者が機能を全部使用せず不
必要となる回路ブロックが発生することがありこの場合
も不必要な電力を供給しつづけている。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which power supply can be disconnected or disconnected for each circuit block within the integrated circuit. When using freely programmable bipolar programmable read-only memory (PROM) or field programmable logic array (FPLA), these integrated circuits have a write circuit that is used only when writing a program. Power is supplied even during a normal read operation, that is, unnecessary power is continued to be supplied even when a program is not written. Even in integrated circuits other than program writing, there are cases where the user does not use all of the functions and some circuit blocks become unnecessary, and in this case too, unnecessary power continues to be supplied.
上述した従来の集積回路は、不必要になった回路ブロッ
クでも電力を消費して、装置の消費電力を増大させると
いう欠点があった。The conventional integrated circuit described above has the disadvantage that even unnecessary circuit blocks consume power, increasing the power consumption of the device.
本発明の目的は、不必要となった回路ブロックへの電力
の供給を外部から切断することのできる集積回路を提供
する事にある〇
また、一度電力を断った回路ブロックが再び使用する必
要が生じた時は、ふたたび電力を供給して使用できる集
積回路を提供する事にある。An object of the present invention is to provide an integrated circuit that can cut off the power supply from the outside to circuit blocks that are no longer needed. Also, it is an object of the present invention to provide an integrated circuit that can cut off the power supply from the outside to circuit blocks that are no longer needed. The goal is to provide an integrated circuit that can be powered and used again when a problem occurs.
本発明の半導体集積回路は、複数個の回路ブロックを有
する集積回路において、集積回路の電源と前記回路ブロ
ックとそれらの電源端子との間に、電気的に切断可能な
素子と電気的に短絡可能な素子とを並列に接続した複合
素子を設けて構成される０
〔実施例〕
次に、本発明について図面を参照しながら説明する。The semiconductor integrated circuit of the present invention is an integrated circuit having a plurality of circuit blocks, and can be electrically short-circuited with an electrically disconnectable element between the power supply of the integrated circuit and the circuit blocks and their power supply terminals. [Embodiment] Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の構成を示すブロック図、第
２図は本発明の半導体集積回路に使用する複合素子の第
一の実施例を示す回路図、第３図は本発明の半導体集積
回路に使用する複合素子の第二の実施例を示す回路図で
ある。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram showing a first embodiment of a composite element used in the semiconductor integrated circuit of the present invention, and FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a circuit diagram showing a second example of a composite element used in a semiconductor integrated circuit.
第１図を見るに、Ｖｃｃは、半導体集積回路の電源端子
であルミ源線３を通して回路ブロック１ａ〜１ｎに電源
が供給される。またＶｃｃＡａ −ＶｃｃＡｎは各回路
ブロックの電源端子である。各回路ブロックの電源端子
Ｖｃｃｈａ −ＶｃｃＡｎと電源ライン３の間に回路ブ
ロックへの電源供給の有無を決定する複合素子２３〜２
ｎがある。複合素子は、並列に接続された２組の素子か
らなり、第一の素子は電流が流れることにより発生した
ジュール熱などでその導体部分が切断されて回路ブロッ
クへ供給している電流を断ち、回路ブロックが電力消費
のないようにするものである。第二の素子はその両端の
電圧がある値まで上昇したときに例えばゼナーブレーク
して電流が流れ、その素子の両端が短絡するような素子
である。従って例えば読出し専用メモリのプログラムに
使った回路ブロックを電源回路から切断するには回路ブ
ロック電源端子電圧■ｃｃＡａ〜■ｃｃムｎのうち該当
する電圧、例えばｖｃｃＡａは、トランジスタ４ａの制
御端子５ａに電圧を加えこれを導通することにより複合
素子に電源端子電圧Ｖｃｃが加えられそのときの電流は
はとんど第一の素子に流れる電流となり第一の素子を切
断すれば回路ブロック１ａは独立して電流電源が流れな
くなる。Referring to FIG. 1, Vcc is the power supply terminal of the semiconductor integrated circuit, and power is supplied to the circuit blocks 1a to 1n through the luminous source line 3. Further, VccAa -VccAn are power supply terminals of each circuit block. Composite elements 23 to 2 between the power terminals Vccha - VccAn of each circuit block and the power line 3 determine whether or not power is supplied to the circuit blocks.
There is n. A composite element consists of two sets of elements connected in parallel, and the conductor of the first element is cut due to Joule heat generated by the flow of current, cutting off the current supplied to the circuit block. This ensures that the circuit block consumes no power. The second element is such an element that when the voltage across it rises to a certain value, for example, a zener break occurs and a current flows, causing a short circuit between both ends of the element. Therefore, for example, to disconnect a circuit block used for programming a read-only memory from the power supply circuit, the corresponding voltage among the circuit block power supply terminal voltages ccAa to ccmn, for example vccAa, is the voltage applied to the control terminal 5a of the transistor 4a. By adding this and making it conductive, the power supply terminal voltage Vcc is applied to the composite element, and the current at that time becomes a current flowing mostly to the first element, and when the first element is disconnected, the circuit block 1a becomes independent. Current power stops flowing.
次に、プログラムの修正をするためには第二の素子の短
絡をする必要がある。このときはトランジスタ４ａを導
通させて電源電圧Ｖｃｃを例えばゼナーブレークする電
圧まで上げてそのときに流れる電流により第二の素子を
短絡させて、ふたたび回路ブロックｌａを使うことがで
きるようになる。Next, in order to modify the program, it is necessary to short-circuit the second element. At this time, the transistor 4a is made conductive to raise the power supply voltage Vcc to, for example, a Zener break voltage, and the current flowing at that time short-circuits the second element, allowing the circuit block la to be used again.
次に、半導体集積回路に使用する複合素子の第一の実施
例の構成と作動を説明する。第２図に示すように半導体
集積回路に使用する複合素子の第一 ５−
一の実施例は、熱溶融素子１０とゼナーダイオード１１
とが並列に接続されている。熱溶融素子１゜は例えばタ
ングステン、ポリシリコンなどの薄膜で作られ一定以上
の電流が流れると切断される熱溶融物質からなっており
可溶片の役をしている。Next, the structure and operation of a first embodiment of a composite element used in a semiconductor integrated circuit will be explained. As shown in FIG. 2, a first embodiment of a composite element used in a semiconductor integrated circuit includes a thermal melting element 10 and a zener diode 11.
are connected in parallel. The heat-melting element 1° is made of a thin film of tungsten, polysilicon, or the like, and is made of a heat-melting substance that is cut when a certain amount of current flows, and serves as a fusible piece.
ゼナーダイオード１１は、電源電流の方向に対して逆方
向に接続され、あらかじめ規定された電位まで上昇する
とゼナーブレークして電流が流れ、一定電流以上流れる
と陰極と陽極間にアルミスパイクが走シ、短絡する事が
できる０このようにして、熱溶融素子１０およびゼナー
ダイオード１１を並列接続したものは電気的に切断・短
絡が可能となっている０もちろん熱溶融素子を切断する
のに必要な電流とゼナーが短絡されるのに必要な電流は
異なり、この場合熱溶融素子の方が小さい電流で切断さ
れる。The zener diode 11 is connected in the opposite direction to the direction of the power supply current, and when the potential rises to a predetermined potential, a zener breaks and current flows, and when the current exceeds a certain level, an aluminum spike runs between the cathode and the anode. Can be short-circuited 0 In this way, the parallel connection of the thermo-fusion element 10 and the zener diode 11 can be electrically disconnected and short-circuited. The current required for the current and zener to be shorted is different, in which case the thermofusible element is disconnected with a smaller current.
さらに、半導体集積回路に使用する複合素子の第二の実
施例の構成と作動を説明する。Furthermore, the structure and operation of a second embodiment of a composite element used in a semiconductor integrated circuit will be explained.
第３図に示すように本発明の半導体集積回路に使用する
複合素子の第二の実施例は電源電流方向と順方向に接続
されたダイオード２１と熱溶融物質からなる熱溶融素子
２０とを直列に接続した素子列と、エミッタの電流方向
が電源電流の方向と逆方向に接続されたオーブンペース
トランジスタ２２とを並列接続をして構成した例であり
、複合素子の第一の実施例と同一の動作を行う。この複
合素子ではダイオード２１とオープンベーストランジス
タ２２は電源電流の方向と逆方向に耐電圧をもたせるこ
とができるので、複合素子の第二の実施例を使用した半
導体集積回路は回路ブロック１８〜１ｎの作動状況によ
って電源端子電圧Ｖｃｃが回路ブロック電源端子電圧Ｖ
ｃｃム（すなわちＶｃｃＡａ〜ＶＣＣＡｎ ）より高く
なっても複合素子の熱溶融素子が誤った動作をしないと
いう特徴がある。As shown in FIG. 3, the second embodiment of the composite element used in the semiconductor integrated circuit of the present invention has a diode 21 connected in the forward direction of the power supply current direction and a thermofusible element 20 made of a thermofusible substance connected in series. This is an example in which an array of elements connected to the circuit is connected in parallel to an oven-based transistor 22 whose emitter current direction is opposite to the direction of the power supply current, and is the same as the first embodiment of the composite element. perform the following actions. In this composite element, the diode 21 and the open base transistor 22 can have a withstand voltage in the direction opposite to the direction of the power supply current, so the semiconductor integrated circuit using the second embodiment of the composite element has circuit blocks 18 to 1n. Depending on the operating condition, the power supply terminal voltage Vcc may change to the circuit block power supply terminal voltage V.
There is a feature that the thermal melting element of the composite element does not operate erroneously even if it becomes higher than ccm (that is, VccAa to VCCAn).
以上説明したように本発明は、不必要になった回路ブロ
ックへの電源供給を外部から停止させることや、再び供
給する事のできる効率的な電力の使用を可能とした集積
回路を提供できるという効果がある。As explained above, the present invention can provide an integrated circuit that enables efficient use of power by stopping the power supply to circuit blocks that are no longer needed from the outside and resupplying power. effective.
第１図は本発明の一実施例の構成を示すブロック図、第
２図は本発明の半導体集積回路に使用する複合素子の第
一の実施例の構成を示す回路図、第３図は本発明の半導
体集積回路に使用する複合素子の第二の実施例の構成を
示す回路図。
１ａ〜１ｎ・・・・・・回路ブロック、２ａ〜２ｎ・・
・・・・複合素子、３・・・・・・電源線、４ａ〜４ｎ
・・・・・・トランジスタ、５ａ〜５ｎ・・・・・・制
御端子。
ジ≧３
（） Ｓ−FIG. 1 is a block diagram showing the structure of an embodiment of the present invention, FIG. 2 is a circuit diagram showing the structure of a first embodiment of a composite element used in a semiconductor integrated circuit of the present invention, and FIG. FIG. 3 is a circuit diagram showing the configuration of a second embodiment of a composite element used in the semiconductor integrated circuit of the invention. 1a~1n...Circuit block, 2a~2n...
...Composite element, 3...Power line, 4a to 4n
......Transistor, 5a-5n...Control terminal. Di≧3 () S−
Claims (1)
集積回路の電源と前記回路ブロックとそれらの電源端子
との間に、電気的に切断可能な素子と電気的に短絡可能
な素子とを並列に接続した複合素子を設けたことを特徴
とする集積回路。 ２、前記複合素子が、熱溶融物質を備えてなる熱溶融素
子と、電源電流の方向と逆方向に接続されたゼナーダイ
オードとを、並列接続されてなることを特徴とする特許
請求の範囲第２項記載の半導体集積回路。 ３、前記複合素子が、前記電源電流の方向と順方向に接
続されたダイオードと熱溶融物質を備えてなる熱溶融素
子とを直列に接続した素子列と、エミッタの電流方向が
前記電源電流の方向と逆方向に接続されたオープンベー
ストランジスタとを、並列接続されてなることを特徴と
する特許請求の範囲第１項記載の半導体集積回路。[Claims] 1. In an integrated circuit having a plurality of circuit blocks,
An integrated circuit characterized in that a composite element in which an electrically disconnectable element and an electrically short-circuitable element are connected in parallel is provided between the power supply of the integrated circuit, the circuit blocks, and their power supply terminals. circuit. 2. Claims characterized in that the composite element is formed by connecting in parallel a thermofusible element comprising a thermofusible substance and a zener diode connected in a direction opposite to the direction of the power supply current. The semiconductor integrated circuit according to item 2. 3. The composite element includes an element array in which a diode connected in the forward direction of the power supply current and a heat melting element comprising a heat melting substance are connected in series, and an emitter current direction is in the direction of the power supply current. 2. The semiconductor integrated circuit according to claim 1, wherein open base transistors connected in opposite directions are connected in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61080518A JPS62235750A (en) | 1986-04-07 | 1986-04-07 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61080518A JPS62235750A (en) | 1986-04-07 | 1986-04-07 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62235750A true JPS62235750A (en) | 1987-10-15 |
| JPH0563018B2 JPH0563018B2 (en) | 1993-09-09 |
Family
ID=13720529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61080518A Granted JPS62235750A (en) | 1986-04-07 | 1986-04-07 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62235750A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6469943B2 (en) | 2001-01-23 | 2002-10-22 | Mitsubishi Denki Kabushiki Kaisha | Switching circuit and semiconductor device |
-
1986
- 1986-04-07 JP JP61080518A patent/JPS62235750A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6469943B2 (en) | 2001-01-23 | 2002-10-22 | Mitsubishi Denki Kabushiki Kaisha | Switching circuit and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0563018B2 (en) | 1993-09-09 |
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