JPS62235660A - Blocking addressing device for multidimensional arrangement - Google Patents

Abstract

PURPOSE:To realize the blocking mapping to a one-dimensional storage space of a multidimensional arrangement by generating a block address, and an in- block address from the sum of products of a subscript value of each dimension and a subscript size of each dimension, and from its subscript value, respectively. CONSTITUTION:In case of referring to an array element A (i, j), subscript values (i), (j) of each dimension are held in registers 11, 12, respectively, and a value which raised fractions of the quotient obtained by dividing a subscript size of the subscript (i) by 2N is held in a register 13. Also, the lower N bits of the registers 11, 12 are sent as they are to an output register 16, as in-block address generating bits of a one-dimensional storage space. On the other hand, the upper bits of the registers 11, 12 are sent to a multiplier 14 and a full adder 15 in order to generate a block address and calculated with a value of the input register 13, and an output of the full adder 15 is sent to an output register 13, and an output of the full adder 15 is sent to an output register 16 as a block address of the one-dimensional storage space.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a blocking addressing system for multidimensional arrays, and in particular to a computer system equipped with a hierarchical storage system virtualized by a basing method.

This paper relates to mapping methods and referencing methods for multidimensional array data in systems.

[Conventional technology]

This type of conventional blocking addressing device for multidimensional arrays is used in many programming languages because it can be used to map and reference multidimensional arrays to one-dimensional storage and convert them into one-dimensional addresses using relatively simple calculation methods. has been done. A one-dimensional address is calculated from an array subscript using an adder/subtractor and a multiplier that are included in a normal computer.

A reference method to array element A (It, Ix+111w+) can be obtained using the following calculation formula.

(4Ix+ld heavy IX(tm-I *+ld 11X(
* *・lawt-tX(tm-Is+)"')))X
8+b Note that the array declaration is a(dl, d, a**, d,
)::s (n>=1). a is a sequence group, d1-d1
1 is a dimension declarator, and 1 dimension declarator dt is written as a pair of t(:h(). tl indicates the lower limit value, and hi indicates the upper limit value.

ld+ l is the dimension of the dimension declarator d* hI−
4"l. The storage unit occupied by an array element is 3 bytes. Furthermore, the starting address of the array data storage area is determined by the language processing system (compiler, interpreter, etc.) for the array declared in the programming language. 'Ib.b is array element a(ts+tx,...,t,]
is equivalent to an address pointing to .

For example, the mapping method for multidimensional arrays in two-dimensional arrays is the third
As shown in figure (a), the array element A (1:4
．． 1:4), the reference to A(i,j) is determined by the calculation formula (i-1+3X(j-1))Xs+b. As a result, the arrangement of array elements on the s-dimensional space becomes as shown in FIG. 3(b).

When programming with array data, a typical reference butter 7 to an array element is A(i.

When constructing a loop that refers to j) by changing i or j, as shown in Figure 3(b), refer to array A by shifting the subscript it by +1 or -1. is a reference to nine consecutive storage areas in one-dimensional storage, but the subscript j is shifted by +1 or -1 and the array A
Referring to a non-contiguous storage area is a reference to a discontinuous storage area on -dimensional storage.

In addition, in FIG. 3(b), array element A (1:4゜l:
4) is expanded on the virtual storage space using the paging method, the page size is element 4 of array A.
Equal to one piece. Assume that the processing unit of the computer references four array elements during a certain time interval τ. This reference is A(i,
1) If i=i, 4, the memory page referenced during this time is 1 page, but this reference is A(1,j)
If j=x, 4, the storage page referenced during this time is 4.page KIf. Obviously, the latter reference lacks locality.

If the entire array A cannot fit into the main memory, the number of pages transferred between the main memory and the secondary storage increases. On average, the number of main memory pages required is 2.5, and A(
1,j) The number of required main memory pages increases due to references such as j≠1.4.

This phenomenon increases program execution time.

Performance degradation often occurs in scientific computing programs that use large-scale arrays, and is considered to be one of the working set abnormalities. In order to avoid this phenomenon, it is common practice to carefully design programs so that the locality of memory references is maintained during the program coding method and algorithm design stage. There is.

Therefore, a high-locality mapping method of memory reference is required for relatively any reference pattern.

Regarding this, there is a method called a submatrix method or a blocking method. As an example of mapping a multidimensional array to a one-dimensional storage space using the blocking method, in the method of converting a two-dimensional array to one-dimensional array, a partial array of the original two-dimensional array is treated as one block, and mapping related to the block and The mapping is performed independently. Array element A (1:4
.
A case where the size is equal to four elements of array A is shown. Assume that the processing unit of the computer references four array elements during a certain time interval τ. This reference is A(t.

1) If i = 1, 4, the number of memory pages referenced during this period is 2 pages, and this reference is A(1°j)j = 1
, 4, the number of storage pages referenced during this period is 2 pages. Compared to the former mapping method, AC1h 1 )
In the case of 1-1 and 4, the required number of main memory pages is 1 to 2.
However, the number of required main memory pages in the case of A(1,j)j-1,4 is reduced from 4 to 2. On average, two main memory pages are required, pushing it lower than the former mapping method.

[Problem that the invention seeks to solve]

As described above, conventional methods of mapping and referencing a multidimensional array to a one-dimensional storage space cause problems when the expanded one-dimensional storage space is realized as a virtual storage space using a paging method. Namely.

The virtual storage system utilizes locality of reference, secures the defined storage space in secondary storage, and makes effective use of main memory by placing only the memory pages that are actually currently being referenced in main memory. is being measured. In order for a pseudomemory system to function effectively, locality of reference, which is a precondition, must hold. Mapping and referencing a multidimensional array into a one-dimensional storage space in this manner may violate this locality.

In addition, the block mapping method has a high cost for mapping from a multidimensional space to a one-dimensional space, and the conversion involves cutting out bit fields, and there is a problem in performing the conversion using software.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a blocking addressing system for multidimensional arrays that eliminates the drawbacks of conventional addressing systems and is solved by addressing hardware in a computer.

[Means for solving problems]

The multidimensional array blocking addressing device of the present invention, when mapping/referencing multidimensional array data to a one-dimensional address space, has a first register that holds the subscript value of each dimension pointing to the array element to be referenced, and the second holding the subscript dimension of
It has a register.

A block address of the one-dimensional storage space is generated from the product sum of the block address part of the register of @l and the second register, and an intra-block address of the one-dimensional storage space is generated from the intra-block address part of the first register. It consists in generating.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. 9 in FIG. 1 This embodiment is an addressing device that maps a two-dimensional array to a one-dimensional storage space using a block mapping method.
i s j ) 1 - index value i of each dimension when referencing,
je holding registers 11 and 12, and input register 13
The input register 13 and the register 11 are connected to a multiplier 14, the register 12 and the multiplier are connected to the multiplier 14, a full adder 15, and the register 11 . register 12
and an output register 16 which holds a one-dimensional address at the subscript level and which is connected to the full adder 15.

Register 11 is the first register that holds array index 1, register 12 is the second register that holds array index 1, and these are the inputs that are converted to -dimensional addresses. The first and second registers 11 and 12 are composed of two fields with the Nth bit and the N+1th bit from the lowest order as boundaries. The value of N must be determined based on the page size of the target computer, but if the page size is 4 bytes and a 4-byte single-precision real number is used as the standard for array elements, it will be around N-5. becomes. That is, a 32x32 partial array will occupy two pages.

The input register 13 is a register that holds a value obtained by dividing the subscript dimension of subscript i by 2 to the N power and rounding it up.

The lower N bits of input registers 11 and 12 are the intra-block address generation bits! The upper bits of input registers 11 and 12 are sent to a multiplier 14 and a full adder 15, respectively, for generating a block address. Full adder 15 sends this result to output register 16. The output of output register 1G is sent out as a one-dimensional address.

Next, array A (1:128, 1:128) according to this example
To explain the operation of an example of referencing A(i% j) in a state where 32x32 blocks are used for ::4, first, registers 11.
12 with subscript 'Is increment i-1, j from the lower limit of J
-1 is set. The registers 11 and 12 that hold the subscript value of each dimension are divided into blocks in units of 32x32, so the lower 5 bits are recessed in the address part within the block, and the lower 5 bits are
The upper bits excluding bits and bits are the block address part. The register 11 that holds subscript dimensions has dimension 1 of subscript i.
Set the value 4, which is the quotient of 28 divided by 32, rounded up. In the case of a two-dimensional array, the subscript dimension j is not necessary.

As a result, the result is obtained in the multi-output register 16, and the block address part of the output register is the value obtained by multiplying the value of the register that holds the subscript size i by the block address part of the register that holds the entire value of the subscript value j. and the block address of the register that holds the value of index value i. On the other hand, the intra-block address section of the output register 16 is obtained by arranging in series the intra-block address section of the register that holds the value of subscript value j and the intra-block address section of the register that holds the value of subscript value i.

Therefore, since the value obtained in the output register 16 is a one-dimensional address at the subscript level, the arithmetic processing unit (not shown) multiplies the storage size 4 occupied by the array element by the value of the output register, and then By adding the starting point address b of A, the desired one-dimensional address is generated.

In this embodiment, it is placed in the arithmetic unit of the computer, the input signal is supplied from the register of the arithmetic unit, and the output signal is sent to the register of the arithmetic unit. Therefore, it goes without saying that the input/output register may be a register of the arithmetic processing device itself. Furthermore, although this embodiment maps a two-dimensional array into blocks into a one-dimensional storage space, it goes without saying that a similar device can also be constructed for arrays of three or more dimensions.

〔Effect of the invention〕

As described above, the present invention performs mapping/reference to a one-dimensional storage space of a multidimensional array using a blocking mapping method, thereby transferring pages between the main memory and the secondary storage of a virtual storage system using a paging method. The number of times can be reduced. The block mapping method has a register that holds the subscript value of each dimension that points to the array element to be referenced, and a register that holds the subscript size of each dimension, and holds the block address part and subscript size of the register that holds the subscript value. Generate a block address in the one-dimensional storage space from the sum of products of the registers.
A conventional mapping method is to provide a blocking addressing device for a multidimensional array in the arithmetic processing unit of a computer, which generates an intra-block address of a one-dimensional storage space from an intra-block address part of a register that holds a subscript value. It is possible to perform mapping with the same time cost as .

[Brief explanation of drawings]

FIG. 1 is a diagram showing an apparatus for mapping a two-dimensional array into a one-dimensional storage space in blocks according to an embodiment of the present invention, and FIG. 2 is a diagram showing a device for mapping a two-dimensional array into a one-dimensional storage space using a blocking mapping method. FIG. 3 is a diagram showing a conventional method for mapping a two-dimensional array to a one-dimensional storage space. 11.12...Register, 13...Input register, 4...Multiplication calculator, 5...
Full adder, 6... Output register.

Claims (1)

[Claims] In a blocking addressing device that maps/references multidimensional array data to a one-dimensional address space, a first register holds the subscript value of each dimension pointing to the referenced array element, and a second register holds the subscript size of each dimension. a block address section of the first register and a block address section of the first register;
A block address of a one-dimensional storage space is generated from the sum of products of the registers, and an intra-block address of the one-dimensional storage space is generated from the intra-block address part of the first register. Addressing device.