JPH0559453B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a blocking addressing device for multidimensional arrays, and in particular to mapping of multidimensional array data in a computer system equipped with a hierarchical storage system virtualized by a paging method. law and reference law.

[Conventional technology]

This type of conventional blocking addressing device for multidimensional arrays is used in many programming languages because it can be used to map and reference multidimensional arrays to one-dimensional memory and convert them into one-dimensional addresses using relatively simple calculation methods. has been done. A one-dimensional address is calculated from an array subscript using an adder/subtracter and a multiplier that are included in a normal computer.

The reference method for array element A (I ₁ , I ₂ , . . . , In) is given by the calculation formula shown below.

(l ₁ −I ₁ + |d ₁ |×(l ₂ −I ₂ + |d ₂ |×(……|d _o-1
｜×( _lo −I _o )……)))×s+b Note that the array declaration is a(d ₁ , d ₂ ,……, d _o )::
Let s be (n>=1). a is an array name, d ₁ to _{d o} are dimension declarators, and the dimension declarator d _i is written as a pair of l _i :h _i . l _i indicates the lower limit value, and h _i indicates the upper limit value. ｜d _i
| is called the dimension of the dimension declarator d _i and is equal to h _i −l _i +1. The storage unit occupied by an array element is s bytes. Further, let b be the starting address of the array data storage area determined by the language processing system (compiler, interpreter, etc.) for the array declared in the programming language. This starting point address b is equivalent to the address pointing to array element a (l ₁ , l ₂ , . . . , _lo ).

For example, the conventional mapping method for a multidimensional array in a two-dimensional array is vertically divided, as shown in Figure 4a, and in the case of array element A (1:4, 1:4),
Reference to A(i,j) is calculated using the formula (i-1+3
It is determined by ×(j-1))×s+b. As a result, the array elements are arranged in a one-dimensional space as shown in FIG. 4b. When programming using array data, a typical reference pattern to array elements is when constructing a loop that refers to A(i, j) by changing i and j. As can be seen from Figure b, shifting the subscript i by +1 or -1 and referencing array A is a reference to a continuous storage area in one-dimensional storage, whereas shifting the subscript j by +1 or -1 refers to a continuous storage area. Referring to array A is a reference to a discontinuous storage area on one-dimensional storage.

In addition, in FIG. 4b, array element A (1:4,
1:4) is expanded on the virtual storage space using the paging method, the page size is equal to four elements of array A. Assume that the processing unit of the computer references four array elements during a certain time interval γ. If this reference is A (i, 1) i = 1, 4, the memory page referenced during this time is 1 page, but if this reference is A (1, j) j = 1, 4
If so, the number of memory pages referenced during this time is 4.
Across the page. Obviously, the latter reference lacks locality, and if the entire array A cannot fit into the main memory, the number of pages transferred between the main memory and the secondary memory will increase. On average, the number of main memory pages required is 2.5, and the number of main memory pages required increases as the reference becomes A(1,j)j=1,4. Increased program execution time and decreased performance due to such phenomena often appear in scientific and technical calculation programs that use large-scale arrays, and are considered to be one of the working set abnormalities. In order to avoid this phenomenon, it is common practice to carefully design programs so that the locality of memory references is maintained during program coding and algorithm design steps, making program creation difficult. There is.

Therefore, a mapping method with high locality of memory reference is required for relatively any reference pattern. Regarding this, there is a method called a submatrix method or a blocking method. As an example of mapping a multidimensional array to a one-dimensional storage space using the blocking method, in the method of converting a two-dimensional array to one-dimensional, a subarray of the original two-dimensional array is treated as one block. The mapping is performed independently. For example, array element A
(1:4, 1:4) is mapped as a 2x2 subarray in one-dimensional storage space, as shown in Figure 2b, the page size is equal to 4 elements of array A. It shows the case. Assume that the processing unit of the computer references four array elements during a certain time interval γ. If this reference is A (i, 1) i = 1, 4, the number of memory pages referenced during this time is 2 pages, and if this reference is A (1, j) j = 1, 4, the number of memory pages referenced during this time is 2 pages. The number of memory pages referenced by is 2 pages. Compared to the former mapping method, A(i,1)i
= 1, 4, the required number of main memory pages is 1 to 2
However, the number of required main memory pages is reduced from 4 to 2 when A(1,j)j=1,4. On average, two main memory pages are required, which is lower than the former mapping method.

[Problem that the invention seeks to solve]

As described above, the conventional method of mapping and referencing a multidimensional array to a one-dimensional storage space causes a problem when the expanded one-dimensional storage space is realized as a virtual storage space using a paging method. That is,
Virtual memory systems utilize locality of reference, secure defined storage space in secondary storage, and place only the memory pages that are actually currently being referenced in main memory, thereby making effective use of main memory. I'm planning. In order for a virtual memory system to function effectively, locality of reference, which is a prerequisite, must be established. Mapping and referencing multidimensional arrays into one-dimensional storage space in conventional ways may violate this locality.

We also demonstrated the effectiveness of the block mapping method, but
The blocking method has a higher cost for mapping from a multidimensional space to a one-dimensional space than the conventional method, and the conversion involves cutting out bit fields, so there are problems with performing the conversion using software as in the past. There are also problems such as collisions on the main memory bank. SUMMARY OF THE INVENTION An object of the present invention is to provide a multidimensional array blocking addressing device that solves these problems using computer addressing hardware.

[Means for solving problems]

According to the present invention, in a blocking addressing device that maps/references multidimensional array data to a one-dimensional address space, the subscript value I _i of each dimension indicating an array element A (I ₁ , I ₂ , ... I _o ) is used. n subscript value registers holding (0≦I _i ≦d _i −1:1≦i≦n) and subscript size d _i of each dimension.
Block subscript dimension RM _i obtained by dividing (1≦i≦n-1) by 2 ^N and rounding up the quotient to a power of 2.
n-1 subscript size registers holding (1≦i≦(n-1)); a block address part RB _i (1≦i≦n) of the upper N-1 bits of the above-mentioned subscript value register; From the block index dimension value RM _i of the index dimension register, the block address of the one-dimensional storage space is calculated as RB ₁ + RM ₁ × (RB ₂ + RM ₂ × (... (RM _o-1 ×
RB _o )...), and a block address calculation means for calculating RI _o , ( _{RI o} +RI _o-1 ), (RIn+RI _o-1 +RI _o-2 ),
Find n calculated values of (RI _o +...RI ₁ ),
Intra-block address generation means for arranging lower bit strings of operation results to generate an intra-block address in a one-dimensional storage space; and an output for holding the one-dimensional address connected to the block address arithmetic means and the intra-block address generation means. A multidimensional array blocking addressing device is obtained, which is characterized in that it is composed of registers.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In FIG. 1, this embodiment is a device that generates a one-dimensional subscript address from a three-dimensional subscript address using a one-dimensional addressing method for a multidimensional array.
When referencing (i, j, k), use registers 11, 12, and 13 that hold array index k, array index j, and array index i, respectively, and divide the index size of index i by 2 to the N power and round up the quotient. an input register 14 that holds a value obtained by dividing the subscript dimension of subscript j by 2 to the N power, and an input register 15 that holds a value obtained by rounding up the quotient, and an output register 22 that outputs a one-dimensional address at the subscript level. include.

Registers 11, 12 and 13 are composed of two fields with the Nth bit and N+1th bit from the lowest order as boundaries. The value of N needs to be determined based on the page size of the target computer, etc., but if a single-precision real number with a page size of 4K bytes is considered as the standard for array elements, N = about 4. In other words, a 16×16×16 partial array constitutes one block, and the storage size occupied by this partial array corresponds to 4 pages in the case of a single-precision real number array. 16×16×16 if the array element is an 8-byte double-precision real number array
The partial array will occupy 8 pages.

Furthermore, in this embodiment, a multiplier 16 is connected to the register 11 and the input register 15, a full adder 18 is connected to the register 12 and the multiplier 16, and a full adder 18 is connected to the input register 14 and the full adder 18. a multiplier 17 connected to the register 13 and the multiplier 17, a full adder 20 connected to the register 11 and the register 12, and a full adder 20 and the register 13. a full adder 21 connected to the full adder 1;
9 to 21 and the register 11 are configured to be connected to the output register 22.

In this embodiment, one of the subscripts i, j, and k is continuously changed in one-dimensional address calculation within a block to avoid bank collisions with respect to references. This process does not directly lead the lower N bits of subscript inputs i and j to the output, but instead directs the subscripts k and j
The sum of the lower N bits of (overflows are discarded), index k,
The sum of the lower N bits of j and i (overflows are discarded) is used. FIG. 2 shows a case where blocks are mapped to a main memory device consisting of a plurality of banks. FIG. 2 shows a state in which an array A(1:16, 1:16, 1:16)::8 is mapped to a main memory device consisting of 8 bytes in parallel and 16 banks. Here, N=4. A(i,1,1)j=1,16A(1,1,
k) No bank collision occurs when access is made by continuously sliding one of the subscripts such as k=1, 16, etc. However, if the subscripts are changed in such a way that the sum of subscripts i, j, and k is constant, the references will be to the same bank, so for programs that include references in this way, the subscripts i, j , k are directly led to the output.

In this way, this embodiment is provided with a mechanism for avoiding bank collisions. The main memory of a computer is sometimes divided into a plurality of banks for high-speed data transfer to and from an arithmetic processing unit, and accesses to different banks can be processed at high speed. i for array A(i, j, k)
Alternatively, continuous references by changing j and k can be processed at high speed as long as the same bank is not accessed in the main memory.

Furthermore, although this embodiment is designed to block a three-dimensional array as a basic operation, it can also be used to convert a two-dimensional array and an array of four or more dimensions into one-dimensional array. FIG. 5 shows an embodiment in which the present invention is configured for a multidimensional array.

In Figure 5, array element A (I ₁ , I ₂ , ... I _o )
When referring to the subscript values of each dimension I ₁ , I ₂ , ... I _o
n subscript value registers 50 ₁ to 50 _o
and the subscript dimensions d ₁ , d ₂ , ... d _{o -1} of _{I 1} , I ₂ , ... I o
2 Block subscript dimension RM _i (1≦i≦(n-1)) divided by ^N and rounded up so that the quotient becomes a power of 2
n-1 subscript dimension registers 51 ₁ to
51 _o-1 , multipliers 52 1 to 52 o-1 connected to subscript value registers 50 ₁ to 50 _o , subscript size registers _{51 1 to} 51 _{o- 1} , and full adders 53 ₁ to 53 _o-1 ,
54 ₁ to 54 _o-1 and an output register 55 that holds one-dimensional addresses.

The subscript value registers ₅₀₁ to _50o are similar to the registers 11 and 12 in FIG. , the upper N-1 bits consist of a block address part RBi (1≦i≦n).

Block internal address part of subscript value register 50 _o
RI _o is sent to the output register 55 and the full adder 54 _o-1 , and the intra-block address part RI _i (1≦i≦n) of the subscript value registers 50 ₁ to 50 _o-1 is sent to the full adder 54 o-1.
4 ₁ to 54 _o-1 , RI _o , (RI _o + R1 _o-1 ),
n calculation values of (RI _o + RI _o-1 + RI _o-2 ), . . . (RI _o + . . . RI ₁ ) are determined and sent to the output register 55 as an intra-block address.

Also, in order to generate block addresses, block _address parts RB _i ( ₁
≦i≦n), multiplier 52 _o-1 and full adder 5
3 ₁ to 53 _o-1 , subscript size register 51 ₁
~51 Block subscript dimension held in _o-1
RM ₁ , RM ₂ , ...RM _o-1 are multipliers 52 ₁ to 52
_o , the following equation is calculated as a block address in the one-dimensional storage space, and the result is sent to the output register 54.

RB ₁ + RM ₁ × (RB ₂ + RM ₂ × (……(RM _o-1 ×
RB _o )...) The output of the output register 55 is sent out as a one-dimensional address.

FIG. 3 shows a method of mapping a two-dimensional array to a one-dimensional storage space using the block mapping method. In FIG. 3, when converting a two-dimensional array into one-dimensional array, the value 0 is set in the input register 13. Also, the input register 14 is set to the value 1. That is, for a reference to array element A(i, j), input register 11 has array index j, input register 12
Set the value of array index i to input register 15.
The value obtained by dividing the subscript dimension of subscript i by 2 to the N power and rounding it up is used. In this case, the lower N bits of the output register 22 have no meaning, so
Before calculating the one-dimensional address to be obtained from the one-dimensional address at the subscript level, it is necessary to shift N bits to the right. Array A (1:128, 1:128)::
When A(i, j) is referenced in a state where A(i, j) is blocked in 32×32 for 4, the increment i- from the lower limit value of subscripts i, 1, set j-1. Since the registers 12 and 11 that hold the subscript values of each dimension are divided into blocks of 32×32, the lower 5 bits are the intra-block address part, and the upper part excluding the lower 5 bits is the block address part. The register 14 that holds subscript dimensions has the dimension 128 of subscript i.
Divide by 32, round up the quotient, and set the value 4. In the case of a two-dimensional array, the subscript dimension j is not necessary.

The result is then obtained in the output register 22 by operating the device. The block address part of the output register 22 is the value obtained by multiplying the value of the register 12 holding the subscript size i by the block address part of the register 11 holding the value of the subscript value j, and the value of the register holding the value of the subscript value i. This is the sum of block addresses. On the other hand, the intra-block address section of the output register 22 is obtained by adding the intra-block address section of the register 11 that holds the value of subscript value j and the intra-block address section of register 12 that holds the value of subscript value i to this value. It is a series of values (overflows are discarded).

Since the value finally obtained in the output register 22 is a one-dimensional address at the subscript level, the arithmetic processing unit further multiplies the storage size 4 occupied by the array element by the value in the output register 22, and then multiplies the value in the output register 22, and then the starting address b of the array A. The desired one-dimensional address is generated by adding .

Furthermore, in the case of mapping an array of four dimensions or more, in this case, the array subscripts can be divided into three-dimensional units and made into blocks, and a conventional method can be used for composing them. That is, array A(i, j, k, 1)
, consider this as A(ijk, 1) and subscript
This device is used to calculate ijk, and the conventional method is used to combine the subscript ijk and 1.

〔Effect of the invention〕

As described above, the present invention performs mapping/reference to a one-dimensional storage space of a multidimensional array using a blocking mapping method, thereby transferring pages between the main memory and secondary storage of a virtual storage system using a paging method. The number of times can be reduced. The block mapping method has a register that holds the subscript value of each dimension that points to the array element to be referenced, and a register that holds the subscript size of each dimension, and indicates the block address part and subscript size of the register that holds the subscript value. A block address in the one-dimensional storage space is generated from the sum of products of the registers, and an intra-block address in the one-dimensional storage space is generated from the addition result of the intra-block address portion of the register that holds the subscript value. By providing a blocking addressing device for a multidimensional array in the arithmetic processing unit of a computer, it is possible to avoid bank collisions and perform mapping at the same time cost as the conventional mapping method.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an apparatus for mapping a three-dimensional array into a one-dimensional storage space into blocks according to an embodiment of the present invention, and FIG. 3 is a diagram showing a method of mapping a two-dimensional array to a one-dimensional storage space using the block mapping method, FIG. 4 is a diagram showing a method of mapping a two-dimensional array to a one-dimensional storage space using a conventional method, and FIG. FIG. 5 is a diagram showing an apparatus for mapping a multidimensional array into a one-dimensional storage space into blocks according to an embodiment of the present invention. 11, 12, 13...Register that holds array index, 14, 15...Input register, 16, 17
... Multiplier, 18, 19 ... Full adder, 20,
21... Adder, 22... Output register.

Claims (1)

[Scope of Claims] 1. In a blocking addressing device that maps/references multidimensional array data to a one-dimensional address space, a subscript value I of each dimension pointing to array element A (I ₁ , I ₂ , ... I _o ) _i (O≦I _i ≦d _i −1:1≦i≦n) and the subscript size d _i of each dimension.
Block subscript size method that divides (1≦i≦n-1) by 2 ^N and rounds up so that the quotient becomes a power of 2.
RM _i (n-1 subscript size registers holding 1≦i≦(n-1); a block address part RB _i (1≦i≦n) of the upper N-1 bits of the subscript value register; From the block index dimension value RM _i of the index dimension register, RB ₁ + as the block address of the one-dimensional storage space.
RM ₁ × (RB ₂ + RM ₂ × (... (RM _o-1 × RB _o )...
...) from the n bit strings of the block internal address part RI _i (1≦i≦n) of the lower N bit strings of the subscript value register, RI _o , (RI _o +RI _o-1 ), (RIn+RI _o-1 +RI _o-2 )
Find n calculated values of (RIn+...+RI ₁ ),
an intra-block address generating means for arranging the lower N bit strings of the operation results to generate an intra-block address in a one-dimensional storage space; and holding a one-dimensional address connected to the block address arithmetic means and the intra-block address generating means. 1. A multidimensional array blocking addressing device comprising: an output register;