JPS62234428A - Power supply circuit - Google Patents
Power supply circuitInfo
- Publication number
- JPS62234428A JPS62234428A JP61078542A JP7854286A JPS62234428A JP S62234428 A JPS62234428 A JP S62234428A JP 61078542 A JP61078542 A JP 61078542A JP 7854286 A JP7854286 A JP 7854286A JP S62234428 A JPS62234428 A JP S62234428A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- base
- emitter
- collector
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 4
- 230000007423 decrease Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Devices For Supply Of Signal Current (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、２線（ベア線）を用いた電源回路に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a power supply circuit using two wires (bare wires).
従来の技術
第２図に２線（ベア線）を用いた有線通信回路の基本構
成を示す。この様な構成は電話通信、ホームバス等の有
線通信に用いられている。第２図において、局は局電源
回路１５から、線路１４を通して端子３及び４に接続さ
れる複数個の端末装置に一定レベルの電源電圧を供給し
ている。また局は配線１２及び１３を通して端子１〜２
間に送受話信号を入力している。端末装置は、局より供
給される電源電圧を端末電源回路１６でレギュレートシ
、端末回路１７を駆動して種々の信号処理を行なう。な
お、端末回路１７は端子７及び８を通して信号の送信、
受信を行なう。このため、線路１４から端子１〜２間及
び端子３〜４間を見た信号の周波数におけるインピーダ
ンスは高いことが必要である。Background Art FIG. 2 shows the basic configuration of a wired communication circuit using two wires (bare wires). Such a configuration is used in wired communications such as telephone communications and home buses. In FIG. 2, the station supplies power supply voltage at a constant level from a station power supply circuit 15 to a plurality of terminal devices connected to terminals 3 and 4 through a line 14. The station also connects terminals 1 to 2 through wires 12 and 13.
A transmitting and receiving signal is input between the two. The terminal device regulates the power supply voltage supplied from the station with a terminal power supply circuit 16, drives a terminal circuit 17, and performs various signal processing. Note that the terminal circuit 17 transmits signals through terminals 7 and 8,
Perform reception. For this reason, it is necessary that the impedance at the frequency of the signal seen between the terminals 1 and 2 and between the terminals 3 and 4 from the line 14 be high.
従来の局電源回路の等価回路を第３図に示す。FIG. 3 shows an equivalent circuit of a conventional station power supply circuit.
端子９〜１０間に直流電圧源Ｅ１を接続し、インダクタ
ンスＬ１を通して端子１〜２間に直流電圧を供給する。A DC voltage source E1 is connected between terminals 9 and 10, and a DC voltage is supplied between terminals 1 and 2 through an inductance L1.
端子１，２は線路に接続され、線路側から端子１〜２間
を見たインピーダンスは２πｆＬ１となる。（但し、ｆ
は信号の周波数であ発明が解決しようとする問題点
従来の回路においては、インダクタンスＬ１を用いるた
め、小型化、低価格化が困難であった。Terminals 1 and 2 are connected to the line, and the impedance seen between the terminals 1 and 2 from the line side is 2πfL1. (However, f
is the frequency of the signal. Problems to be Solved by the Invention In the conventional circuit, since the inductance L1 is used, it is difficult to reduce the size and cost.
また線路電圧は線路に流れ込む電流が増加するとインダ
クタンスＬ１の直流抵抗により低下するという欠点があ
った。Another disadvantage is that the line voltage decreases due to the direct current resistance of the inductance L1 when the current flowing into the line increases.
本発明は上記の欠点に濫み、インダクタンスを用いず、
また、線路に流入する電流によらず一定の電圧を発生す
る電源回路を与えるものである。The present invention overcomes the above drawbacks, does not use inductance,
It also provides a power supply circuit that generates a constant voltage regardless of the current flowing into the line.
問題点を解決するための手段
電源に接続される第１の端子と定電圧を出力するための
第２の端子と接地用の第３の端子とを有し、前記第１の
端子と前記第２の端子との間に、第１の抵抗および、エ
ミッタを前記第１の端子に、コレクタを前記第２の端子
に、おのおの、接続した第１のＰＮＰトランジスタを並
列接続し、前記第１のＰＮＰトランジスタのベースに、
エミッタを前記第３の端子に接続した第２のＮＰＮ ト
ランジスタのコレクタを接続し、同第２のＮＰＮ トラ
ンジスタのベースに、エミッタを第２の抵抗を通して前
記第２の端子に接続した第３のＰＮＰトランジスタのコ
レクタを接続し、同第３のＰＮＰトランジスタのベース
に、エミッタを前記第３の端子に接続した第４のＮＰＮ
トランジスタのコレクタを接続し、同第４のＮＰＮ ト
ランジスタのベースに、エミッタを前記第３の端子に接
続した第５のＨＰＮトランジスタのコレクタを接続し、
同第５のＮＰＮ トランジスタのベースに、第５の抵抗
及び第４の抵抗を接、続し、前記第５の抵抗の他端を前
記第３の端子に接続し、前記第４の抵抗の他端を前記第
３のＰＮＰトランジスタのエミッタに接続し、前記第３
のＰＮＰトランジスタのエミッタと前記第４のＮＰＮト
ランジスタのベースとの間に第３の抵抗を接続し、前記
第３のＰＮＰ トランジスタのエミッタと前記第３の端
子との間に容量を接続した構成を有する電源回路である
。Means for Solving the Problems The device has a first terminal connected to a power source, a second terminal for outputting a constant voltage, and a third terminal for grounding, and the first terminal and the third terminal are connected to each other. A first resistor and a first PNP transistor having an emitter connected to the first terminal and a collector connected to the second terminal are connected in parallel between the second terminal and the second terminal. At the base of the PNP transistor,
A third PNP transistor whose emitter is connected to the third terminal, the collector of which is connected to the base of the second NPN transistor, and whose emitter is connected to the second terminal through a second resistor. a fourth NPN transistor whose collector is connected to the base of the third PNP transistor, and whose emitter is connected to the third terminal;
connecting the collector of the transistor, and connecting the collector of a fifth HPN transistor whose emitter is connected to the third terminal to the base of the fourth NPN transistor;
A fifth resistor and a fourth resistor are connected to the base of the fifth NPN transistor, the other end of the fifth resistor is connected to the third terminal, and the other end of the fifth resistor is connected to the base of the fifth NPN transistor. an end connected to the emitter of the third PNP transistor;
A third resistor is connected between the emitter of the PNP transistor and the base of the fourth NPN transistor, and a capacitor is connected between the emitter of the third PNP transistor and the third terminal. It is a power supply circuit with
作用
本発明によると、電源回路の出力電圧を抵抗およびトラ
ンジスタによる制量回路によって検出帰還し、出力電圧
に応じて、第１のＰＮＰ トランジスタの電流すなわち
線路の電流供給量を加減して、これにより、出力電圧を
一定に保つことができる。According to the present invention, the output voltage of the power supply circuit is detected and fed back by a control circuit including a resistor and a transistor, and the current of the first PNP transistor, that is, the amount of current supplied to the line, is adjusted or decreased according to the output voltage. , the output voltage can be kept constant.
実施例 本発明を、第１図の実施例回路によシ、詳しくのべる。Example The present invention will be described in detail with reference to the embodiment circuit shown in FIG.
電圧源Ｅ１を接続するための入力側端子９と共通端子１
ｏ、線路に接続される出力測定電圧端子１と共通端子２
とを有し、ＰＮＰ トランジスタＱ１のエミッタを端子
９に、ＰＮＰトランジスタＱ１のコレクタを端子１に、
同ＰＩＰ トランジスタＱ１のベースをＮＰＮトランジ
スタＱ２のコレクタに接続し、同ＮＰＮ トランジスタ
Ｑ２のエミッタを端子１０，２に、同ＮＰＮ トランジ
スタＱ２のベースをＰＮＰトランジスタＱ３のコレクタ
に接続し、同ＰＮＰトランジスタＱ３のベースをＮＰＮ
トランジスタＱ４のコレクタに、同ＮＰＮ トランジス
タＱ４のエミッタを共通端子１ｏ、２に、同ＮＰＮ ト
ランジスタＱ４のベースをＮＰＮ トランジスタＱ５の
コレクタに、そして、同ＮＰＮトランジスタＱ５のエミ
ッタを端子１０．２に接続する。端子１に抵抗Ｒ２を接
続し、この抵抗Ｒ２の他端にＰＮＰトランジスタＱ３の
エミッタ、抵抗Ｒ３、同Ｒ４および容量Ｃ１を接続し、
この容量Ｃ１の他端を端子１０，２に、また、抵抗Ｒ４
の他端をＮＰＮ トランジスタＱ６のベースに、抵抗Ｒ
３の他端をＮＰＮトランジスタＱ５のコレクタに接続し
、さらに、ＮＰＮ トランジスタＱ６のベースと端子１
０，２の間に抵抗Ｒ６を接続する構成の電源回路である
。Input side terminal 9 and common terminal 1 for connecting voltage source E1
o, output measurement voltage terminal 1 and common terminal 2 connected to the line
, the emitter of PNP transistor Q1 is connected to terminal 9, the collector of PNP transistor Q1 is connected to terminal 1,
The base of the PIP transistor Q1 is connected to the collector of the NPN transistor Q2, the emitter of the NPN transistor Q2 is connected to terminals 10 and 2, the base of the NPN transistor Q2 is connected to the collector of the PNP transistor Q3, and the emitter of the PIP transistor Q2 is connected to the collector of the PNP transistor Q3. NPN base
Connect the collector of transistor Q4, the emitter of NPN transistor Q4 to common terminals 1o and 2, the base of NPN transistor Q4 to the collector of NPN transistor Q5, and the emitter of NPN transistor Q5 to terminal 10.2. . A resistor R2 is connected to terminal 1, and the emitter of a PNP transistor Q3, resistors R3 and R4, and a capacitor C1 are connected to the other end of this resistor R2.
The other end of this capacitor C1 is connected to terminals 10 and 2, and the resistor R4
The other end is connected to the base of NPN transistor Q6, and resistor R
The other end of 3 is connected to the collector of NPN transistor Q5, and the base of NPN transistor Q6 and terminal 1
This is a power supply circuit having a configuration in which a resistor R6 is connected between 0 and 2.
第１図の回路において端子１〜２間に発生する直流電圧
すなわち、出力電圧をＶｒｅｇとし、ＮＰＮトランジス
タＱ５と同Ｑ４とのそれぞれのベース・エミッタ間の電
圧をｖＢＥｓ各トランジスタの１ｉｆｅを十分に大きく
、無限大と仮定すると、Ｖｒｅｇは次式で表わせる。In the circuit shown in Figure 1, the DC voltage generated between terminals 1 and 2, that is, the output voltage, is Vreg, and the voltage between the base and emitter of NPN transistors Q5 and Q4 is vBEs. , are assumed to be infinite, Vreg can be expressed by the following equation.
（１）式で設定した値より出力電圧Ｖ ｒ６ ｇが増加
した場合、ＰＮＰトランジスタＱ１のベース電流は減少
し、したがって、出力電圧ｖｒｅｇが下る。また出力電
圧Ｖｒｅｇが低下すると、ＰＮＰ トランジスタＱ１の
ベース電流が増加し、これに応じ、出力電圧ｖｒｅｇが
上る。このように回路動作し、出力電圧Ｖｒｅｇが一定
に保たれる。When the output voltage V r6 g increases from the value set by equation (1), the base current of the PNP transistor Q1 decreases, and therefore the output voltage vreg decreases. Further, when the output voltage Vreg decreases, the base current of the PNP transistor Q1 increases, and the output voltage Vreg increases accordingly. The circuit operates in this way, and the output voltage Vreg is kept constant.
また、線路側から端子１〜２を見たインピーダンスをＺ
ｏとすると、線路上の信号の周波数ｆに関係無りＺｏは
次式で表わせる。Also, the impedance when looking at terminals 1 and 2 from the line side is Z
If o, Zo can be expressed by the following equation, regardless of the frequency f of the signal on the line.
（１）式および（２）式より、出力電圧Ｖ、θｇおよび
線路インピーダンスＺｏを任意に設定できる。From equations (1) and (2), the output voltage V, θg and line impedance Zo can be set arbitrarily.
第１図の回路にオイテ、Ｒ１＝１２＝１００にΩ。Apply the circuit shown in Figure 1, and set Ω to R1 = 12 = 100.
Ｒ５＝２００にΩ、Ｒ２＝３７にΩ、Ｒ５：１３．７に
Ω。Ω at R5=200, Ω at R2=37, Ω at R5:13.7.
Ｃ，＝＝１００μＦと設定し、本発明を実施した結果、
Ｒａｇ＝１０．５Ｖ、Ｚｏ＝２２にΩの局電源回路が得
られた。As a result of setting C,==100μF and implementing the present invention,
A local power supply circuit with Rag=10.5V and Zo=22Ω was obtained.
発明の効果
本発明によると、無負荷時の低電流化が可能であり、ま
た、インダクタンスを用いないので、ＩＣ化が容易であ
り、小型化、低価格化が可能な局電源回路が得られる。Effects of the Invention According to the present invention, it is possible to reduce the current when there is no load, and since no inductance is used, it is possible to obtain a station power supply circuit that can be easily integrated into an IC, and which can be made smaller and lower in price. .
第１図は本発明実施例の電源回路の回路図、第２図は従
来の有線通信回路の基本構成図、第３図は２線（ペア）
線を用いた従来電源回路の基本等価構成図である。
２．４，６，１０・・・・・・共通端子、１．３．５・
・・・・・入力端子、７・・・・・・端末回路の送信端
子、８・・・・・・端末回路の受信端子、１４・・・・
・・線路、１６・・・・・・局電源回路、１ｅ・・・・
・・端末電源回路、１７・・・・・・端末回路、Ｅｌ・
・・・・・電圧源、Ｌｌ・・・・・・インダクタンス、
０１、Ｃ２・・・・・・容量、Ｒ１−Ｒ５・・・・・・
抵抗、Ｑｌ。
Ｃ３・・・・・・ＰＮＰ トランジスタ、Ｃ２、Ｃ４、
Ｃ５・・・・・・ＮＰＮトランジスタ。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図Figure 1 is a circuit diagram of a power supply circuit according to an embodiment of the present invention, Figure 2 is a basic configuration diagram of a conventional wired communication circuit, and Figure 3 is a two-wire (pair) diagram.
FIG. 2 is a basic equivalent configuration diagram of a conventional power supply circuit using wires. 2.4, 6, 10... Common terminal, 1.3.5.
...Input terminal, 7...Transmission terminal of terminal circuit, 8...Reception terminal of terminal circuit, 14...
...Line, 16...Station power supply circuit, 1e...
...Terminal power supply circuit, 17...Terminal circuit, El.
...Voltage source, Ll...Inductance,
01, C2... Capacity, R1-R5...
Resistance, Ql. C3...PNP transistor, C2, C4,
C5...NPN transistor. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure
Claims (1)
第２の端子と接地用の第３の端子とを有し、前記第１の
端子と前記第２の端子との間に、第１の抵抗および、エ
ミッタを前記第１の端子に、コレクタを前記第２の端子
に、おのおの接続した第１のＰＮＰトランジスタを並列
接続し、前記第１のＰＮＰトランジスタのベースに、エ
ミッタを前記第３の端子に接続した第２のＮＰＮトラン
ジスタのコレクタを接続し、同第２のＮＰＮトランジス
タのベースに、エミッタを第２の抵抗を通して前記第２
の端子に接続した第３のＰＮＰトランジスタのコレクタ
を接続し、同第３のＰＮＰトランジスタのベースに、エ
ミッタを前記第３の端子に接続した第４のＮＰＮトラン
ジスタのコレクタを接続し、同第４のＮＰＮトランジス
タのベースに、エミッタを前記第３の端子に接続した第
５のＮＰＮトランジスタのコレクタを接続し、同第５の
ＮＰＮトランジスタのベースに、第５の抵抗および第４
の抵抗を接続し、前記第５の抵抗の他端を前記第３の端
子に接続し、前記第４の抵抗の他端を前記第３のＰＮＰ
トランジスタのエミッタに接続し、前記第３のＰＮＰト
ランジスタのエミッタと前記第４のＮＰＮトランジスタ
のベースとの間に第３の抵抗を接続し、前記第３のＰＮ
Ｐトランジスタのエミッタと前記第３の端子との間に容
量を接続した構成を有する電源回路。It has a first terminal connected to a power supply, a second terminal for outputting a constant voltage, and a third terminal for grounding, and between the first terminal and the second terminal, A first resistor and a first PNP transistor each having an emitter connected to the first terminal and a collector connected to the second terminal are connected in parallel, and the emitter is connected to the base of the first PNP transistor and the emitter is connected to the second terminal. The collector of the second NPN transistor connected to the third terminal is connected, and the emitter is passed through the second resistor to the base of the second NPN transistor.
The collector of a third PNP transistor whose emitter is connected to the third terminal is connected to the base of the third PNP transistor, and the collector of a fourth NPN transistor whose emitter is connected to the third terminal is connected. The collector of a fifth NPN transistor whose emitter is connected to the third terminal is connected to the base of the NPN transistor, and the base of the fifth NPN transistor is connected to a fifth resistor and a fourth
, the other end of the fifth resistor is connected to the third terminal, and the other end of the fourth resistor is connected to the third PNP terminal.
a third resistor connected to the emitter of the third PNP transistor and between the emitter of the third PNP transistor and the base of the fourth NPN transistor;
A power supply circuit having a configuration in which a capacitor is connected between an emitter of a P transistor and the third terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61078542A JPS62234428A (en) | 1986-04-04 | 1986-04-04 | Power supply circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61078542A JPS62234428A (en) | 1986-04-04 | 1986-04-04 | Power supply circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62234428A true JPS62234428A (en) | 1987-10-14 |
Family
ID=13664800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61078542A Pending JPS62234428A (en) | 1986-04-04 | 1986-04-04 | Power supply circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62234428A (en) |
-
1986
- 1986-04-04 JP JP61078542A patent/JPS62234428A/en active Pending
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