JPS62234269A - Audio signal recording and reproducing system - Google Patents

Abstract

PURPOSE:To repeatedly reproduce audio stored contents with which a storage capacity is not filled, by latching the output of an address counter and using this output as an end address and using the counter as an interval timer after reaching the end address. CONSTITUTION:The address outputted from a counter 12 of a digital control part 10 is latched as the end address in a latch circuit 13 through a sequencer 16 by the pause operation or the like. A digital audio signal is read out from a RAM 2 by the output of the counter 12 until a coincidence output is applied to the sequencer 16 from a comparator 14 because of arrival at the end address. Thereafter, the counter 12 functions as the interval timer through the sequencer 16 in accordance with the set time of an interval time setting circuit 19 to form a silent section having a prescribed length, and the counter 12 is reset to repeat the same operation. Thus, good repeated reproducing is performed based on the contents of the RAM 2 with which the storage capacity is not filled.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B0 Overview of the invention C1 Prior art 9 Problems to be solved by the invention E1 Means for solving the problems F0 Effect G. Example G-1. Schematic structure (Fig. 1) ) G-2, Overall configuration of tape recorder (Figure 2) G-3,
Explanation of operation of main parts (Fig. 3) G-4, Other configuration example H, Effects of the invention A, Industrial field of application The present invention relates to an audio signal recording and reproducing method, and in particular to a method for converting an audio signal into a digital signal. The present invention relates to an audio signal recording and reproducing method that controls writing and reading in a storage means such as a memory.

B1 Summary of the Invention The present invention provides an audio signal recording and reproducing method that converts an audio signal into a digital signal and writes it into a storage means, reads out the content written in the storage means in response to an operation input, converts it into an analog audio signal, and retrieves it. In,
A counter for obtaining an address for accessing the storage means is also used as an interval timer, and the output of this counter is latched by the latch means in response to an operation input, so that the signal written to the storage means does not reach the storage capacity of the storage means. Sometimes, the count value stored in the latch means is used as an end address, and the storage means is sequentially read and reproduced according to the counting operation from the initial value of the counter, and when the end address is reached, the interval of the counter is set. By repeatedly performing an operation that forms a predetermined silent section using a timer operation, smooth digital repeating can be performed without any inconvenience even if an operation input is received when the memory content is less than the full storage capacity of the storage means. This makes regeneration possible.

C1 Conventional technology Tape recorders and the like have been widely used to record and play back audio signals, but because the recording and playback is performed by mechanically running and driving magnetic tape, there is a limit to response speed. .

By the way, Japanese Patent Application Laid-open No. 49-83472 and Japanese Patent Application Laid-open No. 52
JP-A-143007 and the like disclose a technique for digitizing an audio signal and storing it in a memory device or the like. With such technology, it is easy to achieve so-called random access playback in which the desired recorded content is read out instantly, but it is difficult to ensure a recording time comparable to that of a normal tape recorder (for example, about 1 hour). Even if digital signal compression technology is used, this would require an extremely large storage capacity of the memory device, which would not only be extremely expensive compared to the price of the general analog tape recorders that are currently in widespread use. In particular, it is difficult to apply it to portable tape recorders.

Therefore, the applicant has decided to use a general analog tape recorder,
For example, we have proposed a tape recorder for language teaching (so-called LL) that is made by adding a digital circuit system to perform digital recording and playback only for a short period of time (for example, several seconds) required for repeat playback. There is. This tape recorder has the advantage that not only can the repeat playback described above be performed with good responsiveness and high accuracy, but also that the scale of the digital circuit system, particularly the memory capacity, can be small.

B0 Problems to be Solved by the Invention Incidentally, when performing such repeat playback digitally, it is troublesome to access or control addresses of digital storage means consisting of semiconductor memory such as RAM. If you try to perform repeat playback with a playback time shorter than the repeat time corresponding to the entire storage capacity, the settings for the start address (start address) and end address (end address) of repeat playback will become complicated, and it will be difficult to set the appropriate repeat playback time. Problems arise, such as reproduction becoming impossible and the circuit configuration becoming complicated.

The present invention has been made in view of the above-mentioned circumstances, and when digitally repeating playback is performed by sequentially and repeatedly reading out a storage means such as a RAM, the present invention is intended to be applied to storage contents smaller than the capacity of the storage means. It is an object of the present invention to provide an audio signal recording and reproducing method which enables effective and smooth repeat playback, and which is particularly suitable for use in small-sized language learning (LL) tape recorders.

Means for Solving the E0 Problem The audio signal recording and reproducing method of the present invention converts an input audio signal into a digital signal and writes it into a storage means, repeatedly reads out the stored contents from the storage means in response to an operation input, and converts the input audio signal into a digital signal and writes it into a storage means. An audio signal recording and reproducing method for converting into an audio signal and outputting the same includes: a counter having an interval timer function and an address counter function of the storage means; a latch means for capturing and temporarily storing the output of the counter; Comparing means for comparing the count output and the output from the latch means, and a sequencer for sequentially controlling the operations of at least the counter and the latch means according to the operation input and the output from the comparison means, the sequencer causes the count output from the counter to be stored in the latch means in response to the operation input, and when the signal written in the storage means is less than the storage capacity of the storage means, the count value stored in the latch means is is set as an end address, the storage means is sequentially read and reproduced according to the counting operation from the initial value of the counter, and when the end address is reached, a predetermined silent section is formed using the counter as an interval timer. However, the above-mentioned problems are solved by repeatedly performing these playback operations and silent section forming operations.

When there is an operation input in a state where the memory content is less than the storage capacity of the F0 action storage means, the address at the time of the operation input is set as the end address, a counter is counted from the initial value to the above end address, and the memory is stored in a RAM, etc. By sequentially accessing the means and repeating the operation of forming a predetermined silent section using the counter as an interval timer when the end address is reached, the stored contents are repeated over a predetermined time interval. It is possible to read out and smoothly realize so-called repeat playback.

G, Embodiment G-1, Schematic configuration (Fig. 1) Fig. 1 is a block diagram for explaining an audio signal recording and reproducing method that is an embodiment of the present invention. This figure shows an example of a circuit suitable for digitally realizing a repeat playback function by adding it to an analog tape recorder, particularly a small portable tape recorder for language lessons.

The input terminal 1 in FIG. 1 is supplied with a digital signal obtained by AD converting (analog-to-digital conversion) an analog audio signal from the audio circuit system of an analog tape recorder, which will be described later. The audio signal is stored in RAM2, which is a storage means.
are sent to and written sequentially. The digital signals sequentially read out from the RAM 2 are sent to the digital mute circuit 1 in the system controller or the digital control section 10.
1 to the output terminal 3. The digital signal taken out from the output terminal 3 is subjected to DA conversion (digital-to-analog conversion) to become an analog audio signal, and is sent to an audio circuit system to be described later.

The digital control unit 10 is used as a RAM controller and a system controller, and is used as a RAM controller and a system controller.
2, a latch circuit 13 that temporarily holds (so-called latch) the count output from this counter 12, and a latch circuit 13 that temporarily holds (so-called latch) the count output from this counter 12. Comparing means for comparing the output with the output from the counter 12, a so-called comparator 14, and a gate circuit 15 for gate-controlling the output from the latch circuit 13 and sending it to the preset data input terminal (or data load terminal) of the counter 12. , and a sequencer 16 for controlling the operation of each part.

The sequencer 16 controls the digital mute circuit 11, the counter 12, the latch circuit 13, and the gate circuit 15 according to the operation input (for example, pause operation input) from the control input terminal 6 of the digital control section 10 and the output from the comparator 14. This is for sequentially controlling each operation. Such a digital control unit 10 is further provided with a timing controller 17, a multiplexer 18, and an interval time setting circuit 19. Supplied via. Various timing pulses from the timing controller 17 are supplied to the sequencer 16, multiplexer 18, external RAM 2, and the like. The multiplexer 18 converts the count output from the counter 12 into R
The interval time setting circuit 19 is used to send data to the address input terminal of AM2, and the interval time setting circuit 19 is used to send data to the sequencer 1 when the count output from the counter 12 reaches a predetermined value IEA.
This is for sending an interval end signal to the terminal 6.

Further, when the counter 12 counts a value corresponding to the storage capacity (total address space) of the RAM 2, it sends a carry output to the sequencer 16, and the sequencer 16 sets an overflow flag ○■F according to the condition.

G-2. Overall configuration of tape recorder (Figure 2) A digital recording/reproducing circuit system having the above configuration as the main part,
A specific example applicable to a general analog tape recorder will be described with reference to FIG.

The tape recorder schematically shown in Fig. 2 digitally performs short-term repeat playback (for example, about 4 seconds or 8 seconds), and in normal playback mode with repeat mode on, which will be described later. , AD the analog playback signal
The converted data is constantly written to the RAM 2, which is a storage means, and when the pause button etc. is operated (during a pause operation), the content stored in the RAM 2 is sequentially and repeatedly read out and converted to DA, thereby enabling repeat playback. We are making it happen.

First, to explain the analog audio circuit system in FIG. 2, the recording/playback amplifier 51 includes a recording/playback head 52
A playback signal from the amplifier 51 is inputted via the selected terminal P of the mode selector switch 53, and a signal from the microphone 54 is also inputted, and a recording output (so-called Rec, 0ut) from the amplifier 51 is input. The signal is sent to recording and playback via the selected terminal R of the mode selector switch 53.
2. This recording/playback amplifier 51 is connected to a circuit power supply from a 10B power supply terminal 55, so-called V
cc is supplied. The 10B power supply voltage is supplied to the common terminal of a mode changeover switch 57 via a resistor 56, and the selected terminal R of this mode changeover switch 57 is connected to the recording/playback changeover terminal (PB/REC) of the recording/playback amplifier 51. connected, and the selected terminal P is grounded. These mode changeover switches 53 and 57 are interlocked with each other.
When each switch 53, 57 is switched and connected to each selected terminal R, the recording mode is selected, and when each switch 53, 57 is switched and connected to each selected terminal P, the playback mode is selected.

Playback output from the recording/playback amplifier 51 (Line 0ut
) signal is supplied to a variable resistor 60 for volume adjustment via a capacitor 58 and a resistor 59, and an output signal from this variable resistor 60 is supplied to a power amplifier 61 via a resistor, a capacitor, etc. The output signal from the power amplifier 61 is taken out from the output terminal 62 as an audio output signal.

Regarding the above schematic configuration of the analog audio circuit system,
In order to perform digital repeat playback as described above, the following digital circuit system is added.

That is, the output of the recording/playback amplifier 51 (LineOut
) terminal is supplied to an AD (analog-digital) converter 24a of an AD-DA converter 24 via a capacitor 21, a resistor 22, and an LPF (low-pass filter) 23. A
For example, a digital signal subjected to delta modulation (specifically, ADM, adaptive delta modulation) is output from the D conversion unit 24a, and this digital signal is sent to the RAM, which is a storage means, via the terminal l shown in FIG. (random access memory) 2 and are sequentially written. This RAM2 is
Writing and reading operations are controlled by the system controller or the digital control unit 10 as described above, and the digital signals read from the RAM 2 are sent to the AD-DA converter 24 via the digital control unit 10. DA (digital-analog) converter 24b
sent to.

Regarding the input/output terminals of this digital control section 10, those corresponding to those in FIG. 1 are given the same reference numerals. The output signal from the DA converter 24b is sent to the muting circuit 30 via the LPF 27, the resistor 28, and the capacitor 29. The muting circuit 30 is
A switching transistor 31 is connected between the signal transmission line and ground, and this muting circuit 30
The output signal from is supplied to the buffer amplifier 32 via a capacitor. The output signal from the buffer amplifier 32 is supplied via a capacitor 33 and a resistor 34 to a connection point between a resistor 59 and a variable resistor 10 in the analog audio circuit system. At this time, the resistors 59.34 act as so-called mixing resistors.

Regarding the circuit power supply for this digital circuit system, please refer to the above 10B.
Power from the power supply terminal 55 is supplied to the DC-DC converter 37 via the switching circuit 35, the repeat mode changeover switch 36, etc., and is obtained from the DC-DC converter 37. The transistor 35a of the switching circuit 35 is turned on when the mode changeover switch 57 is connected to the reproduction side terminal P, and supplies the 10B power to the repeat mode changeover switch 36.

The repeat mode selector switch 36 is used to select a repeat operation in which, for example, when a pause button is operated during playback operation, the recorded content for a predetermined period of time (for example, 4 seconds, 8 seconds, etc.) immediately before the pause is repeatedly played back. belongs to. Specifically, this repeat mode changeover switch 36 has, for example, three selected terminals a, b, and c. mode, and terminal C corresponds to the 8-second repeat mode. When the repeat mode selector switch 36 is connected to the selected terminal A or C, the 10B power obtained through the transistor 35a is supplied to the DC-DC converter 37, and the power from the DC-DC converter 37 is AD-DA converter 24 whose output is the above-mentioned digital circuit system, RAM
2 and the digital control unit 10, etc. Further, when the repeat mode selector switch 36 is switched and connected to the selected terminal a, the +Bffi source from the transistor 35a of the switching circuit 35 is applied to the base of the transistor 31 of the muting circuit 30 via the time constant circuit 41. The muting is turned on.

Here, switching the repeat time when selecting the repeat mode can be realized, for example, by switching the sampling clock frequency of the AD-DA converter 24. By switching the time constant, for example, by switching the capacitors 38b and 38c with the changeover switch 39, the sampling clock frequency can be changed to 64, for example.
kHz (64kbps) and 32kHz (32kbps)
s). That is, the AD-converted delta modulation (ADM modulation jI) from the AD-DA converter 24
The resulting digital output signal is 1 sample l bits,
If the storage capacity of RAM2 is 256 kb (kilobits), when the sampling frequency is 54 kllz, 4
It can record for 8 seconds at 32kllz. The sampling clock in the AD/DA converter 24 is sent to the digital control section 10 via the clock input terminal 7 as the reference synchronization pulse shown in FIG. It goes without saying that the changeover switches 36 and 39 are interlocked with each other.

Here, when the repeat mode selector switches 36 and 39 are connected to either terminals A or C to select the repeat mode and the playback mode is in progress,
The playback output (Line 0ut) signal of the recording/playback amplifier 1 is supplied to the AD converter 24a of the AD/DA converter 24 via the LPF 23 and the like, and the AD-converted digital signals are sequentially written into the RAM 2. At this time, when a pause operation signal is input to the terminal 44 of the digital control section 10 by operating a so-called pause button, the control section 10
switches the RAM 2 to the read mode, sequentially and repeatedly reads out the recorded contents for 4 seconds or 8 seconds immediately before the pause input, and sends them to the DA converter 24b of the AD-DA converter 24 via the digital controller 10. During this repeat playback operation, the contents stored in the RAM 2 are repeatedly read out and played back, for example, with predetermined intervals (silent sections) in between.

The analog audio signal extracted from the DA converter 24b via the LPF 27 is sent to the buffer amplifier 32 via the muting circuit 30 and the like. The output signal from the buffer amplifier 32 is connected to a capacitor 33 and a resistor 34.
The variable resistor 60 of the analog audio circuit system is connected through
is amplified by a power amplifier 61 and sent to an output terminal 62.
taken from. Therefore, after the pause operation, the playback content for 4 seconds or 8 seconds immediately before the pause operation (playback output from the recording and playback amplifier 51 of the analog audio circuit system) is repeatedly digitally played back at intervals of the predetermined time, So-called repeat playback is realized digitally. Here, if the time from when the pause is released until the next pause operation is shorter than the above repeat time (for example, 4 seconds or 8 seconds), the audio playback content within this short time will be repeated digitally with the above interval in between. will be played.

G-3. Explanation of main part operation (Figure 3) Refer to Figure 3 for the control operation for performing digital repeat playback as described above in the digital circuit system of the tape recorder having the above-mentioned schematic configuration. I will explain while doing so. That is, the example shown in FIG. 3 shows the operation when the repeat mode selector switches 36 and 39 are connected to terminals 36 and 39 corresponding to repeat mode ON, and playback mode is selected.

The control operation shown in FIG. 3 roughly consists of four basic operations, and these basic operations are an initial setting operation (step 5ll-313) immediately after power-on or immediately after canceling repeat playback; The digital recording operation to the RAM 2 which is a storage means (steps SL4 to 519), the operation of forming a silent section (interval) between the sound playback sections during repeat playback (steps 321 to 524), and the above R
This is a digital reproduction operation (steps 325 to 533) by reading AM2.

First, when power is turned on to the digital circuit system in step 510 of FIG. , respectively, the process proceeds to step Sll, where the sequencer 16 shown in FIG.
is controlled to be in the ON state (Mieto applied state).

Next, the sequencer 16 clears the counter 12 (resets it to zero), sets the count output that becomes the address Adr of the RAM 2 to O (Adr-0), and sets the overflow flag OVF of the counter 12 as shown in step S12. Reset (OVF-Q). Note that the counter 12 may be reset to zero by, for example, closing the gate circuit 15 and performing load control on the counter 12.

After the initial setting operation as described above is completed, step SL
Control moves to the digital recording operation of steps 4 to S19. In this digital recording operation, it is determined in step S14 whether or not there is the human power to operate the pause, and the following series of operations are repeated until the pause operation is input. That is, the synchronization pulse (
The chip S16 writes data into the RAM 2 in synchronization with the input timing of the sampling clock), and the address Adr is incremented (Adr←
Adr+1)L, that is, the counting operation by the counter 12 is performed by 1, and in step 318, whether or not the counter 12 has overflowed, that is, Adr=0.
If there is an overflow, set the overflow flag OVF-1 (OvF-).
1), the process returns to step S14. Therefore, until there is a pause operation, the digital signal of the AD conversion output is written sequentially from address 0 of RAM2 at a timing synchronized with the sampling clock, and this time corresponds to the repeat time (4 seconds or 8 seconds). When it exceeds the limit, 1 is set in the overflora flag OVF and the RAM is
Digital signals are sequentially written starting from address 2, and the previous data is rewritten. In this case, the RAM 2 stores digital data for the above-mentioned repeat time just before the current time.

Next, when a pause operation input is detected in step S14, control moves to step S20, where an interval timer operation and a digital playback operation are executed.

In step S20, the current address Adr from the counter 12 is taken into the latch circuit 13 by the control signal from the sequencer 16 (LA-Adr).
, the counter 12 is reset (Adr←-〇) in the next step S21. From this state of count value 0, while synchronization with the synchronization pulse (sampling clock) is achieved in step S22, step S
At 23, the counting operation of counter 12 starts to progress.
"Adr +1), the count value Adr in step S24
The series of operations from step S22 is repeated until the interval reaches the interval end value IEA. During this time, the digital mute in step Sll remains on, so a silent interval section is formed. Note that the determination of the interval end in step S24 is performed when the output from the counter 12 is determined to be the predetermined value IE.
This is done by detecting that the interval time setting circuit 19 has reached A. Therefore, counter 12
has both the function of the address counter of the RAM 2 described above and the function of the interval timer.

When the interval end is detected in step S24, the process advances to the next step S25, and the digital playback operation for repeat playback as described above is started. First, in step S25, it is determined whether the overflow flag OVF is 1 or not. When it is 1, the process proceeds to step S26, where the gate circuit 15 is
The value LA latched by the latch circuit 13 is preset or loaded as the start address.
dr←LA), and when OV F -h<O, the process proceeds to step S27, where O is set in the counter 12 as the start address (A dr=0). After the start address is set in these steps S26 or S27, the process proceeds to step 328, where the digital mute circuit 11 is controlled to be off, and the actual read operation of the RAM 2 is sequentially performed through steps 329 to 333. .

That is, in step S29, it is determined whether or not the above-mentioned pause state is released, and until the pause state is released, while synchronization is maintained by the synchronization pulse detection in step S30,
Read RAM2 in step S31, and step S32
Increment the address Adr (Adr=Adr+
1) L, that is, the counting operation by the counter 12 is performed by 1 count, and the operation is sequentially repeated until it is determined in step S33 whether or not the output of the counter 12 has reached the latch address LA, which is the end address. ing. When the count value Adr reaches the LA in step S33 before the pause is released, the process returns to step S21 to perform the interval timer operation, and then proceeds to step S25 again to repeat the digital reproduction operation.

In this way, digital repeat playback is performed with predetermined interval times in between. If the pause is released during this period, step S29 is followed by step S29.
After the control is transferred to step S11 and the initial settings from step S11 to step 513 are performed, the control is transferred to step S11.
Digital recording operations from step S4 to step S19 are executed.

Here, the determination of the overflow flag OVF in step 325 is performed from the pause operation (pause on) from the pause release point (or the digital circuit system power on point).
The time up to the point is the reheat time (4 seconds or 8 seconds).
This is to determine whether it is longer or shorter than the OVF (seconds); if it is longer, the OVF is 1; the latched count value above becomes the start address and end address of repeat playback; If it is, the OVF remains set to O in step S13, and the start address of repeat playback becomes 0. Therefore, if the time from pause release to pause (on) operation is shorter than the above repeat time, the interval timer counts for the above predetermined time and the RAM 2 starts from address 0 as the start address to the latched end address. By repeatedly performing the operation of sequentially reading the contents,
Digitally realize repeat playback.

G-4. Other configuration examples Note that the present invention is not limited to the above-mentioned embodiments; for example, delta modulation is simultaneously performed in the AD-DA converter of the embodiment, but in addition to this, normal AD
- Bit compression may be achieved by combining DA conversion with predictive encoding processing such as adaptive differential PCM, orthogonal transformation processing such as Hadamard transform, or the like. In addition, each functional block of the digital control unit does not need to be configured in terms of hardware.
It may be realized by software by controlling the CPU etc. by a program. Furthermore, the sampling clock frequency, repeat time, interval time, number of bits per sample, etc. may be determined depending on the required sound quality, the purpose of repeat playback, etc. Of course, it may be set arbitrarily.

H1 Effect of the invention According to the audio signal recording and reproducing method of the invention, the RAM
When repeating is performed with the memory content not reaching the memory capacity due to a pause operation (from pause off to pause on) at a time interval shorter than the repeat time corresponding to the total memory capacity of the storage means, such as, Since the value (address) of the counter at the time of the pause (on) operation is latched as the end address, the area from the initial value (address 0) of the RAM, etc. to this end address corresponds to the memory contents before the pause operation, and this By sequentially and repeatedly reading out the data, repeat playback can be performed without any inconvenience.

In addition, when the counter output reaches the above end address, the sequencer uses the counter as an interval timer, and an interval (silent section) is inserted between the audio playback sections of repeat playback, so that it can be used in language lessons, etc. Repeat playback of formats can be performed effectively.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing the configuration of essential parts for explaining an embodiment of the present invention, FIG. 2 is a block circuit diagram schematically showing the entire tape recorder to which the present invention is applied, and FIG. The figure is a flowchart for explaining the operation of the main part of the present invention. 1... Digital signal input terminal 2... RAM 3... Digital signal output terminal 10... Digital control section 12... Counter 13... Latch circuit 14... Comparator 15... Gate circuit 16...Sequencer 19...Interval time setting circuit 24...AD-DA converter 51...Recording/playback amplifier Patent distributor Sony Corporation

Claims (1)

[Scope of Claims] An audio signal recording and reproducing method that converts an input audio signal into a digital signal and writes it into a storage means, repeatedly reads out the stored contents from the storage means in response to an operational input, converts it into an analog audio signal, and outputs it. A counter having an interval timer function and an address counter function of the storage means, a latch means for capturing and temporarily storing the output of this counter, and a count output from the counter and an output from the latch means are compared. Comparing means; and a sequencer that sequentially controls the operation of at least the counter and the latch means according to the operation input and the output from the comparison means, and the sequencer outputs the count from the counter according to the operation input. is stored in the latch means, and when the signal written in the storage means is less than the storage capacity of the storage means, the count value stored in the latch means is used as the end address, and the count from the initial value of the counter is started. The storage means is sequentially read and played according to the operation, and when the end address is reached, a predetermined silent section is formed using the counter as an interval timer, and these playback operations and silent section forming operations are repeated. An audio signal recording and reproducing method characterized by: