JPS622333A - State recognizing system for data processing system - Google Patents

Abstract

PURPOSE:To prevent degradation of the processing efficiency of a controller and a host device by constituting the title system so that the host unit generates a processing request to all the controllers and serves as both a state recognition and a processing start, without executing the state recognition of the controller at every state variation. CONSTITUTION:Whether a processing request from a host unit 200 exists or not is decided by a host circuit sub-CPU 160, and when the processing request is executed, a main CPU 110 refers to a spare mode flag in a subordinate circuit sub-CPU 150. When the spare mode flag is in an on state a main controller 100a is operating and its own spare controller 100b is monitoring, therefore, a telegraphic message showing a stand-by state is transmitted to the host unit 200 from a host circuit lH through the host circuit sub-CPU 160, and the processing request from the host is waited for again. When the spare mode flag is in an off state the main controller 100a is faulty, and the spare controller 100b is in the course of a circuit service, therefore, the requested processing is executed.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Examples (al-Configuration of Examples) Explanation (Figures 2 and 3) (b)
Explanation of the operation of one embodiment (Figures 4 and 5) (C) Detailed explanation of internal processing (Figures 6 and 7) (diExplanation of other embodiments Effects of the invention [Summary] Multiple terminals In a system where multiple controllers are provided to control devices, and when one controller fails, the other controller performs bank-up control, in which a host unit connected to the multiple controllers issues a processing request to the multiple controllers. By recognizing the states of a plurality of controllers, it is possible to easily recognize which controller is communicating.

[Industrial application field]

The present invention provides a data processing system that performs data collection processing such as a POS system, in which a plurality of controllers are provided to control a plurality of terminal devices, and when one controller fails, the other controller performs bank-up control. This invention relates to a method for recognizing the state of a controller in a computer.

In a system in which a large number of terminal devices are connected by a controller, and the controller and the terminal devices communicate with each other to execute desired processing, if an error occurs in the controller, the entire system will go down, so multiple controllers are installed. Therefore, a system is used in which when an error occurs in one controller, the other controller provides backup and the other controller continues processing.

In such a backup system, an error in one controller automatically switches to the other controller, so the upper unit of the controller needs to recognize this.

[Conventional technology]

For example, in a POS system, as shown in FIG. 8, a plurality of PO31 terminals 130 to 13n each having a keyboard, display, printer, barcode scanner, etc. are provided, and each PoS terminal 130 to 13n is connected to a plurality of ( Controllers 100a and 100b (two in the figure)
The controllers 100a and 100b are connected to a management computer 200 such as a business computer or an office computer via an upper line j2H to form a system.

In such a POS system, controller 1
00a and 100b are price lookup files PLU files (hereinafter referred to as PLU files) that are comparison tables between product codes and prices.
At the PO3 terminals 130 to 13n, the product code is entered from the keyboard or scanner during a product transaction, and transmitted to the controllers 100a and 100b using the downlink βL. , refers to the price from the PLU table, receives this from the downlink JL, calculates the total amount, and issues a receipt.

PoS terminals 130 to 13n and controller 10 for each transaction
Communication with the controllers 100a and 100b is performed, and as a result, the controllers 100a and 100b can perform cash registers, that is, aggregation of sales for each PoS terminal, aggregation of sales for each product, and the like.

Since communication is performed for each transaction in this way, multiple controllers are provided as described above, and one controller (
For example, even if a non-serious error such as a data error occurs while 100a) is communicating with a PO8 terminal, it will take time to process the error and it will not be able to respond to requests from other PO8 terminals. controller (e.g. 10
0b), and if such an error occurs, one controller 100a is brought down and the other controller 100b is turned down for backup as shown in FIG.
It is designed to perform communication processing with the O3 terminal.

On the other hand, when one controller 100a in the town state recovers after completing error processing, the other controller 100b returns to the monitoring state, and one controller 100a communicates with the PoS terminal.

In a system having such an automatic backup amplifier function, it is necessary for the upper management computer 200 to request (instruct) the controllers 100a and 100b to perform processing such as periodic aggregation. The controller must recognize whether the image processing is in progress.

Conventionally, in order to recognize the upper level, each controller 100
A and 100b report to the higher-level management computer 200 when switching states from communication processing to down, from monitoring to communication processing, and so on.

[Problem that the invention seeks to solve]

However, in a bank-up system that does not require terminals to wait, even a small error causes the controller 100 to
Since the states of the controllers 100a and 100b are switched relatively frequently, the state is reported one by one.

A problem has arisen in that processing for 10ob becomes a burden.

That is, the controller must perform a reporting process to the host computer 200 via the host line βH every time the state changes, while the host combinator 200 interrupts the process every time the state changes and performs state recognition processing based on the report. However, there was a problem in that the processing efficiency was lowered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a state B recognition method for a data processing system that can prevent the processing efficiency of the controller and host device from decreasing by not recognizing the state of the controller every time the state changes. do.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In the present invention, in a data processing system having a system configuration in which a plurality of controllers connected to the plurality of terminals described above are installed, and the controller is connected to a host device,
A processing request from a higher level side is issued to multiple controllers regardless of the controller status. When the controller receives the processing request, the controller that is monitoring issues a status message indicating that it is monitoring, while the controller that is communicating performs the processing according to the processing request and sends the processing results and the higher-level device. The notification is sent as a processing message.

[Effect]

The present invention is based on the knowledge that when a host unit needs to recognize the state of a controller, it is when the host unit issues a processing request to the controller, and that it is not necessary to always recognize the state.

That is, in the present invention, the host unit issues processing requests to all controllers, thereby recognizing the state and starting the processing. As a result, the monitoring controller responds to the processing request with a status message indicating that it is monitoring, so it recognizes that the controller that does not respond with the status message is in the process of communicating, and the controller responds to the processing request. It waits for the processing result and receives a processing message according to the processing request.

Therefore, the state can be easily recognized and processing efficiency can be prevented from decreasing.

[Embodiment] fal-Explanation of the structure of the embodiment FIG. 2 is a block diagram of one embodiment of the present invention, showing the internal structure of the controller 100a and i_oob.

In the figure, the same components as those shown in FIG. 8 are indicated by the same symbols, and 110 is the main CPU, and
and pos terminal 130 = 13n □ 150 is a lower line sub-CPU that processes and executes the requested task, and lower line j2 for PO8 terminals 130 to 13n.
160 is an upper line sub-CP that performs control regarding L.
170 is an arithmetic CPU that performs arithmetic processing necessary for processing. Furthermore, the controller 10
0b also has the same configuration.

FIG. 3 is a functional block diagram of such a controller, in which the processing of the main CPU 10 is divided into blocks.

In the figure, 101 is a total file for each terminal, and 102 is a PL
103 is a recovery processing unit that performs recovery processing for a failed PLU controller; 104 is a polling monitoring unit; This indicates that the controller on the other side (PLU) monitors the polling signal issued by the controller on the other side to check whether the controller on the other side (PLU) is in a healthy state or in a faulty state. Although not shown, the illustrated PLU controller IOOa also includes a recovery processing section 103, a polling monitoring section 104, and the like.

As will be described later, the recovery processing unit 103 shown in FIG. 3 includes: (i) a link processing function 105, (11 ) A backup processing function 106 that takes over table inquiry request processing, etc.; (iii) Aggregation that occurred during the above-mentioned handover period in response to the reception of a recovery message from the main controller side corresponding to the recovery of the main controller (controller in communication). It has at least a PLU file load processing function 107 for notifying data to the main controller, and (iv) a function 108 for sending a parental rights relinquishment message in response to a restart message from the main controller.

(bl-Explanation of operation of the embodiment) Figure 4 is a flowchart of the operation processing of the control;
Figure (A) is an error processing operation flow diagram for the lower line.
FIG. 4(B) is a flowchart of processing operations for the upper line. FIG. 5 is an explanatory diagram of the operation of failure (error) detection.

First, the controller 100a will be described as a main controller, and the controller 100b as a backup controller.

In the flowchart of FIG. 4(A), ■ the spare side controller 100b is replaced by the main side controller 100a.
The polling monitoring unit 104 determines that a failure has occurred in the main controller 100a when the polling monitoring unit 104 detects that the commands sent at regular intervals have stopped (processing A). This turns off the backup mode flag, which will be described later.

(2) Along with this, the link processing function 105 in the recovery processing unit 103 sends a command to initialize the lines to all POS terminal devices 130 to 13n (processing B). Correspondingly, each terminal device initializes the message processing at that point in time and performs the processing again.

■The bank amplifier processing function 106 thereafter executes PLU table inquiry request processing from each terminal device, notifies the contents of the PLU table 102 to each requesting terminal device, and performs aggregation processing for sold products, etc. is executed as executed by the main controller 100a (processing C). However, processing such as file updating is effective only for updating the PLU table 102, and accesses to other files are rejected as an operational error (processing C).

■While the standby controller 100b is operating in this way, the polling monitoring unit 100 informs the main controller 100a that the main controller 100a has recovered and sent a recovery message.
'04 is detected (processing D), ■The controller 100b updates the contents of the PLU table 102 including the data collected during the above handover.
Transmit to the main controller 100a (processing E)
As a result, the main controller 100a updates the contents of its own PLU table 102.

(2) Next, the polling monitoring unit 104 monitors whether the main controller 1ooa issues a restart message (processing F).

■And the controller 100 that received the restart message
b turns on the backup mode flag, sends a message relinquishing parental rights, stops the line service by the controller 100b, and the controller 100b returns to the line monitoring mode again (processing G).

In the case of the present invention, the bowling monitoring section 104 monitors the polling signal from the main controller 100a.

FIG. 5 therefore shows an explanatory diagram for explaining the principle.

FIG. 5(A) shows a state in which the main side controller tooa is in a healthy state, and FIG. 5(B) shows a state in which it is in a faulty state.

The main controller 100a polls the backup controller 100b at predetermined intervals in the same way as it polls the terminal devices 130 to 13n. In the case shown in FIGS. 5A and 5B, the polling signal to the standby controller 100b is rNs.
Denoted as P#OJ. In the polling monitoring unit 104 shown in FIG. 3, the online flag is turned off at the end of the polling signal, and then turned on immediately after.Meanwhile, a monitoring timer is started at the same time as the online flag is turned on. There is. Therefore, as long as the polling signal is detected at a predetermined interval as shown in FIG. 5(A), it can be determined that the controller 100a is healthy. but,
As shown in FIG. 5(B), if the polling signal is absent for about 5 seconds, for example, it is determined that the controller 10Qa is at fault.

In addition to the above, the polling monitoring unit 104 has a recovery message reception function and a restart message reception function as shown in FIG. omitted.

Next, the processing from the top ranked line will be explained with reference to FIG. 4(B).

■Upper line sub CPU checks whether or not there is a processing request from the top 200.
160 makes a decision, and if there is a processing request, May 7 CPU 11
0 refers to the reserve mode flag in the lower line sub CPUI 50.

■If the backup mode flag is on, the main controller 100a is operating and its own backup controller 1oo
Since b is under monitoring, it sends a message indicating the standby state to the upper line 20 from the upper line /H via the upper line sub CPU 60.
0 and return to step ■.

On the other hand, if the backup mode flag is off, the main controller 100a is in trouble (down) and the backup controller 100b is in line service, so the refined process is executed. For aggregation, the main CPU 10 instructs the calculation CPU 170 to
The total data in the PLU table 102 is subjected to a total calculation.

■Then, the aggregated results are sent to the upper line sub-C to the upper unit 200.
Through PU160, even higher rank, %1ljl! Send via H and return to step ■.

Similarly, in the main controller 100a, in response to a processing request from the upper level 200, if the main controller 100a is not down (
In other words, if the backup mode flag is not on), the aggregation process corresponding to the processing request (in this case, the aggregation file 1
01 (accounting processing within 01 is also possible according to instructions) and sends it to the top 200 in the same way as steps Send in the same way as Step 200.

In this way, the states of the controllers 100a and 100b can be recognized in response to a processing request (request) from the host 200, and processing in response to the processing request is also executed.

For this reason, the host side 200, controllers 100a, 10
Even if 0b and 0b do not report and recognize status B in response to status switching, the host side 200 can recognize the status when necessary.

(Detailed explanation of C1 internal processing FIG. 6 is a functional block diagram of each CPU in the controller shown in FIGS. 2 and 3, and FIG. 7 is a software configuration diagram in FIG. 6.

In FIG. 6, the lower line sub CPU 150 is the main C
Uplink and downlink DMA (direct memory access) functional units 151 and 152 for PUI 10, main CPUI
Command to 10, status interface section 1
53, a timer part 154, and a message control part 155, and it is composed of a timer part 154 and a message control part 155, and is
The message control section 155 exchanges messages through the main CPU 10, the DMA sections 151 and 152, and the interface section 153 exchange commands, status, and data.

The main CPU 10 includes uplink/downlink DMA units 121, 123 and interface unit 123 for the lower line sub CPU 150, downlink/uplink DMA units 124, 125 and interface unit 126 for the upper line sub CPU 160, and each unit for the lower line and upper line. control tasks 111 and 112.

In addition, as shown in FIGS. 7(A) and 7(B), the main CPU 10 performs received message analysis tasks 113 and 114 from the lower and upper lines, a branching task 115, a floppy processing task 116, and a module (0). ~n) 117
These tasks are performed in a predetermined order (in this example, the numbers 1 and 2 assigned to each part) are performed by a monitor unit (not shown).
11 to 116), the execution right is granted. Further, processing data (including transmitted and received messages) between each task is received and passed through queues 118 to 120 and 127 to 129 provided between each task.

Furthermore, as shown in FIG. 7(B), the main CPU i o sends a processing request to the calculation CPU 70,
It includes an operation information reception section 131 and DMA sections 132 and 133.

On the other hand, the upper line sub CPU 160 is the main CPU
It has uplink and downlink DMA sections 164, 165, interface section 1.66, timer section 167, and message control section 168 for 0, and the message control section 168 exchanges messages with the upper layer 200 via the upper line JH. CPU
Commands, status, and data are exchanged between ll0, DMA sections 164 and 165, and interface section 166.

As shown in FIG. 7(B), the calculation CPU is the main CPU
It includes a processing request receiving section 179 for J110, an operation information sending section 171, a DMA section 172, 173, a requested task analysis/branching section 174, and tasks (0 to n) 175.

If the controller shown in FIG. 6 is the above-mentioned standby controller 100b, its operation will be as follows.

First, by turning on the power to the controller, the main CPU
0 determines whether or not it should become the backup controller. This is done by checking whether or not a telegram or the like has already been exchanged on the lower level wAjltL.

Then, if a message is exchanged on the line NL, the lower line control task 111 of the main CPUILO
A flag (not shown) indicating the backup mode is sent to the message control unit 155 of U150.

In response to this backup mode instruction, the message control unit 155 sets the timer section 154 and monitors the message on the line iL. That is, line 7! Every time a message is received on L, the timer part 154 is reset.

In the example described above, the polling interval sent from the main controller 100a to the spare unit is monitored. On the other hand, in this example, the interval between messages sent on the line AL from the controller side and the PO3 terminal side is monitored.

Therefore, line 7! If no message is received from L within a predetermined time (for example, 4 seconds), a time-up signal from the timer part 154 is sent to the status interface 1.
It will be sent to the main CPU 10 side via 53.123.

Note that the message received by the message control section 155 is sent to the main CPU110 side via the DMA control section 151.121. Then, through the message analysis task 113 on the main CPU 110 side, normal processing for the message is performed. This processing is executed by modules 1.17 organized into processing units (for example, PLU processing, aggregation processing, etc.) via branch task 115.

If a response such as a processed result is required, a response message is assembled by the module 117 and sent to the lower line control task 111 and the DMA control unit 122.152.
It is sent to the sub CPUI 50 side via. Sub C
The message control unit 155 of the PU150 is connected to the main CPUll0
When receiving a response message (transmission message) sent from the side, the above-mentioned backup mode flag is referred to. If the backup mode flag is on (valid), the received response message is discarded.

That is, the backup controller 100b also performs PLU processing, aggregation processing, and file update processing in the same way as the main controller 100a. The configuration is such that only transmission of transmitted and received messages to line 199 is prohibited.

Therefore, it is possible to always have a file (not shown) on the standby side that has the same content as the PLO file 102 held by the main controller 100a.

On the other hand, the message control unit 1 is sent from the upper level 200 via the upper line NH.
The message received at 68 is sent to the DMA control unit 165.12.
5 to the main CPU 10 side, and is processed through the upper line control task 112 and message analysis task 114 of the main CPU 110. This processing is performed by module 117 via branch task 115.

As described above, if the received message is the above-mentioned processing request, the module 117 executes to refer to the backup mode flag of the message control unit 155 of the lower line CPU 150, and if the backup mode flag is on, the backup message is sent as described above. A status message is assembled and sent to the sub CPU 60 via the upper line control task 112 and the DMA control unit 124.164, and further transmitted from the message control unit 168 to the upper level 200 via the upper line -NH.

Conversely, if the backup mode flag is off, the request process is executed. For example, for aggregation processing, 'iJ$cPU
170C! 71m (B) Request aggregation within D'lrJ< 7 ft/L=, transfer the data to be aggregated,
Perform calculation processing. This tally result is received via the queue 127, a processing message including the processing results is assembled in the same way, and sent to the sub CPU 160 via the upper line control task 112 and the DMA control section 124, 164, and then sent to the message control section 16.
8 and is transmitted to the upper level 200 via the higher level line IH.

(dl Description of Other Embodiments In the above embodiments, a POS system has been described, but it can also be applied to other data processing systems.

Similarly, failure monitoring is detected by the interval of polling or the interval of messages addressed to the device itself, but other methods may be used.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, when the higher level needs to understand the state of the controller, it issues a processing request and can thereby recognize the state of the controller, reducing the processing required for the higher level to recognize the state. In addition to the effect of improving efficiency, it also has the effect of recognizing the state only when it is necessary.

In addition, since the controller does not need to report the status every time the status changes, the load required for this is small.
Improve processing efficiency.

Furthermore, the means for this purpose is simple and can be easily realized, which is an excellent practical effect.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the invention, Fig. 3 is a functional block diagram of an embodiment of the invention, and Fig. 4 is an operational process of an embodiment of the invention. Flowchart, FIG. 5 is an explanatory diagram of failure detection operation according to an embodiment of the present invention, FIG. 6 is an internal configuration diagram of the controller configured in FIG. 2, and FIGS. FIG. 8 is a software configuration diagram, FIG. 8 is a system configuration diagram, and FIG. 9 is an explanatory diagram of the prior art. In the figure, 100a, 100b - controller, 130 -
13 n-PO3 terminal, 200-.- Upper device.

Claims (1)

[Scope of Claims] It has a plurality of controllers connected to a plurality of terminal devices and for communicating with the terminal devices, and a host device connected to the plurality of controllers, one of the plurality of controllers While communicating with the terminal device,
The other controller monitors the operation of the one controller, and when the one controller fails, the other controller communicates with the terminal device on behalf of the one controller, the data processing system comprising: When the higher-level device issues a processing request to the controller, the controller issues the processing request to the plurality of controllers, and the controller performing the monitoring notifies the higher-level device that it is monitoring in response to the processing request, A state recognition method for a data processing system, characterized in that the host device recognizes the states of a plurality of controllers.