JPS62233074A - Telephone exchange power unit - Google Patents

Abstract

PURPOSE:To miniaturize the title unit by providing a high-frequency switching portion with a current transformer. CONSTITUTION:A telephone exchange power unit consists of a switching circuit S mainly composed of a power transistor, a transformer Tl, a current transformer CT, a rectifying and smoothing circuit R and a DC/AC inverter I Composed of a transistor bridge. In this unit, a DC power E1 is converted into a square waved AC voltage by means of a high switching frequency of 15 KHz and over at the switching circuit S to be further converted into DC. This DC voltage is converted into a low-frequency AC by the DC/AC inverter I and supplied from output terminals Ul, U2 to a load circuit Z. In this manner, the current transformer CT is provided on a primary or secondary side of the transformer T to detect the electric current of a high-frequency switching portion, to rectify and smooth said current to feed it back to the DC/DC converter portion or DC/AC inverter portion I, and to stabilize and control an output from said Converter or inverter portion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a power supply device for a telephone exchange installed in the exchange for ringing a telephone bell.

(Prior Art) In general, a power supply device (hereinafter referred to as a ringer power supply) installed in an exchange for ringing a telephone bell has a power supply of 20
A low frequency AC power source of Hz is used.

The configuration of a conventional telephone exchange is shown in FIG.

In the same figure, ■ is a DC/AC inverter that converts the direct current from the DC power supply E+ (-48V) into low-frequency alternating current (20Hz), the king is the output voltage of this DC/AC inverter ■, D is the telephone, and R is the telephone. A relay that switches and connects the line from the communication path and the line from the output transceiver T, L is a detection circuit that detects when the telephone is in an off-footer state (the receiver is disconnected), and C0NT is described later. The control circuit is shown.

In this device, when a call is received, the control circuit C0NT switches the relay R to the terminal B side, and supplies 85 V/20 Hz alternating current to the telephone from below the output ramp. This activates the telephone bell (resistance 10Ω), and the control circuit C
0NT switches the terminal of relay R to No. 2 (child B) at regular intervals until the telephone ■D enters the off-footer state, causing the telephone's bell to ring intermittently.

When the telephone laD enters the off-footer state, the resistance of the bell disappears, but the detection circuit detects the accompanying voltage change from the charging state of the capacitor C.

Then, the control circuit C0NT locks the relay R to the terminal A side by the signal from the detection circuit.

If a plurality of telephones are connected to this exchange, the AC voltage supplied to each telephone will drop, making it impossible for the detection circuit to correctly detect whether the telephone is on-hook or off-hook.

For this reason, in the conventional exchange, a DC power supply E2 (-48V) is connected between the output transformer T and the terminal B of the relay R, and the AC voltage is shifted up.

However, the conventional phosphorus power supply as mentioned above is
/There was a problem in that the size of the AC inverter I under the output voltage was extremely large. This point will be explained below.

Generally speaking, the size of the core of a transformer is determined by the cross-sectional area of the core being Ae
(cze), and if the window area of the core is AW(cze), it can be expressed as Ae XAW.

Here, the input voltage is V (V), and the switching frequency is f
(Hz), the magnetic flux density is B (G), and the number of primary windings of the transformer is Np (T>), the following equation holds true.

V=4xfXBXAe XNP
The following formula holds true when the number of secondary windings is Ns (T>).

Np X IP = Ns
Np X IP 1NS X Is ) /Ac holds true. If the copper wire occupancy rate is β (=Ac/Aw>), then Ac=βXAw-(2XNpXIP)/δ.

And if we transform this formula, we get 1+□=(δ×βXAW>/(2XNp).

From the above, if the maximum input of the transformer is P (VA), then p=vxIP =2X(5Xβ×BXfXAeXAWX
It becomes IO-8. Therefore, the formula for determining the core size is Ae x Aw=
P/ (2Xδ×βx13xfxlO-8),
When the switching power transistor is operated at a low frequency, the above-mentioned f becomes smaller, and Ae/AW, that is, the core size of the transformer becomes larger.

Also, the output stage of the DC/AC inverter I (output transformer T)
Superimposing a direct current on the output line of the DC/AC inverter (2) also causes the size of the transformer of the DC/AC inverter (2) to increase.

Generally, when direct current is superimposed μ and excited with alternating current, the B-H curve of the transformer core forms a loop around the origin in the shape of (1^ (Figure 19)), and draws a loop around the biased point. shape (Fig. 20), it is necessary to increase the saturation magnetic flux density of the transformer core.For this reason, the size of the lance becomes larger.

Furthermore, as shown in FIG. 21, current 1 to lance C are connected to output transformer T for current detection to stabilize the output by feedback controlling the duty factor of the switching element of DC/AC inverter I. If installed on the primary or secondary side, the switching frequency will be 2
Since the current transformer CT has a low value of 0)1z, the problem of increasing the size of the current transformer CT has also been encountered.

(Problems to be Solved by the Invention) The present invention was made in view of the above-mentioned circumstances, and is an attempt to provide a ringer power supply in which the size of the switching transformer and current transformer is small and the device can be miniaturized. There is.

[Structure of the Invention] (Means for Solving the Problems) The ringer power supply of the present invention includes a first switching circuit that converts input direct current into alternating current by high-frequency switching with a switching element, and a first switching circuit that converts input direct current into alternating current by high-frequency switching with a switching element; a smoothing circuit connected to the secondary side of the converter transformer, and a second circuit connected to the output terminal of the smoothing circuit, which converts input DC to AC by low-frequency switching with a transistor bridge. and a switching circuit of the converter transformer.
A current detection element is provided on the next side, the secondary side, or the output stage of the smoothing circuit, and detects a current for feedback control of the duty factor of the switching element.

(Function) Since the low-frequency switching on the primary side of the transformer of the DC/AC inverter, which was indispensable in the past, is eliminated, the size of the switching section transformer and current transformer becomes smaller, allowing the device to be made more compact. .

(Example) Hereinafter, details of an example of the power supply device for a telephone exchange according to the present invention will be described based on the drawings.

FIG. 1 is a circuit diagram showing the overall structure of a device according to an embodiment of the present invention.

In the figure, El is a DC power supply, S is a switching circuit mainly composed of power transistors, T1 is a transformer connected to this switching circuit S, and 0 is one of transformers T1.
A current transformer that detects the current flowing through the secondary coil N1 or the secondary coil N2, R is a rectifier and smoothing circuit, Rs is a current detection resistor connected to the output stage of the rectifier and smoothing circuit R,
■ is a DC/AC inverter configured with a transistor bridge without using a transformer as shown in (E), P, N are DC/AC inverter ■ DC input terminals, Ul, U
2 is an AC output terminal of the DC/AC inverter I. Note that E2 in the figure is a DC power supply connected to the AC output terminals LJ+ and U2 in order to flow DC for shifting up the AC voltage into the load circuit Z, that is, the telephone circuit.

In this circuit, a DC power source E1 is converted into a square wave AC voltage by a switching element of a switching circuit S at a high switching frequency of 15k)12 or more.

This square wave AC voltage is input to the primary winding N1 of the transformer T1, transformed, and output from the secondary winding N2.

The output voltage is then input to the rectifying and smoothing circuit R and converted into a DC voltage. Roughly speaking, this DC voltage is DC/AC
It is converted into a low-frequency alternating current by the inverter (2), outputted from Ul and U2, and supplied to the load circuit Z.

As in the device of this embodiment, the DC/AC inverter I performs switching at a high frequency (15 kHz or more) by a DC/DC converter consisting of a switching circuit S, a transformer T1, and a rectifying and smoothing circuit R, and is configured by a transistor bridge without using a transformer. If the desired low-frequency alternating current is obtained, the only transformer required is the small-sized transformer T1 for the DC/AC converter, so the device can be downsized. .

In the device of this embodiment, the primary side or the secondary side of the transformer T
Provide a current transformer CT on the next side b) or D
A detection resistor R5 is inserted between the C/DC converter and the DC/AC inverter I to detect the current in the high frequency switching section, and this current is rectified and smoothed to be converted to DC/AC by an amplifier.
The output is stabilized and controlled by feeding back to the DC converter section or the generating circuit of the DC/AC inverter (2).

That is, since the current transformer CT or Rs is provided in the high frequency switching section rather than in the low frequency switching section as in the conventional device, its size can be small enough, and the device can be further miniaturized.

FIG. 2 is a circuit diagram showing a specific configuration of the DC/AC inverter I in FIG. 1.

In the figure, P and N are input terminals, I and C2 are capacitors for dividing the power supply voltage into two, Ql and C2 are power transistors, and Dl and C2 are so that the direct current from the power supply F2 flows superimposed on the alternating current. power transistors Q1 and C2
shows a diode connected in parallel with . This circuit is a so-called half-bridge inverter.

First, in this circuit, the input voltage is divided by capacitors C1 and C2 of the same capacity.

And ON and OFF of power transistors Q1 and C2
As a result, a square wave alternating current having an amplitude of 1/2 of the input voltage is extracted from the output terminal.

Further, FIG. 3 is a circuit diagram that does not show another example of the inverter I shown in FIG. 1.

In the figure, P and N are input terminals, 01 to Q4 are power transistors, D1 to D4 are diodes for superimposing direct current on alternating current, and Ul and U2 are output terminals as an inverter I. This circuit is a so-called full bridge type inverter.

In this circuit, the input voltage is the power transistor Ql,
During the period when C4 is in the ON state, the voltage is applied to the load so that the output terminal U1 becomes positive and the output terminal U2 becomes negative. During the period when the power transistors Q2 and C3 are turned on, a voltage is applied to the load so that the output terminal U1 becomes negative and the output terminal U2 becomes positive. In this way, a square wave AC voltage is generated at the output terminals LJ+ and LJ2.

Note that when direct current is superimposed on the circuit shown in FIG. 3, when transistors Q1 and 04 are in the ON state, the fourth
Direct current flows in a loop like the one shown in the figure.

On the other hand, when transistors Q2 and C3 are in the ON state,
Direct current flows in a loop as shown in Figure 5.

FIG. 6 is a diagram showing the relationship between the ON times of power transistors Q1 and C2 in the half-bridge type circuit shown in FIG. 2.

In the same figure, (1/2)T is the half period of the input waveform, TI2
, T21 is power transistor Q+, C2 are both OFF
(hereinafter referred to as dead time). This dead time is provided to avoid a short circuit between the terminals P and N that would occur if the power transistors Q1 and C2 are turned on at the same time due to their respective storage times or the like.

Note that the diodes D+ and C2 mentioned above are inserted so that during this dead time, there is no insulation between the circuit terminals U1 and U2, and the direct current from the power source E2 always flows. .

FIG. 7 is a diagram showing the relationship between the ON times of power transistors 01 to Q4 in the full bridge type circuit shown in FIG. 3.

In the same figure, (1/2>T is a half period of the input pulse, T+
2 and T2 + indicate dead times when power transistors Q1 and C2 are both turned off, and T34 and T43 indicate dead times when power transistors Q3 and C4 are both turned off.

In this example, power transistors Q1 and 03 are 1
Repeat ON and OFF alternately in 80° increments (T/2 increments).

On the other hand, the ON time width of power transistors Q2 and C4 is narrower than that of power transistors Q+ and C3. O of Zunawara power transistors Q1 and C3
The N time is (1/2) T - (lT+ 2 +T2 + > or (1/2) T - (T3 a + T43 ).

By setting dead time in this way, the power
・Transistors Q1 and Q2 or Q3 and Q4 are turned O at the same time.
A short circuit between the terminal P and the terminal N that would occur if the terminal is N is avoided. In this case, power transistors Q2 and Q4 are turned on and off by 180 degrees, and power transistor Q1
, it is also possible to endure dead time in Q3.

Note that during this dead time, the diodes D1 to D4
The terminals U1 and U2 of the circuit are interposed so that direct current from the power source E2 always flows therebetween, so that the terminals U1 and U2 are not insulated.

By the way, as described above, the dead time is the time provided for the transistors Q2 and 04 to prevent the transistors Q1 and Q2 and Q3 and Q4 from being turned on simultaneously. Therefore, transistors Q1 and 03 have no dead time. , FIG. 8 shows the DC current loop during the dead time.

1~When transistor Q1 is OFF and Q3 is ON,
Direct current flows in a loop like the one shown in the figure.

Note that when transistor Q1 is ON and Q3 is OFF, no direct current can flow, but as shown in Figure 9, this period is 1/2 of the dead time, which is the ON time of transistors Q+ and Q2. This is negligible compared to 25m5.

FIG. 10 is a circuit diagram showing an example of the configuration of an auxiliary power supply circuit for power 1 to transistors in the full bridge type inverter shown in FIG. 3.

In this example, the auxiliary power source is obtained from a bias winding magnetically coupled to the primary winding of converter transformer T1.

In the same figure, El is a DC power supply, and S is the aforementioned DC/DC.
In the switching circuit of the converter, T1 is the converter transformer mentioned above, N1 is the primary winding of the converter transformer TA, N2 is the secondary winding of the converter transformer TA, and Ns1 to NS4 are bias windings magnetically coupled to the primary winding N1 of the converter transformer T1. line, DAI~D84 is a diode for adjustment, CAI~CA
4 is a smoothing capacitor, and Do+ to DQ4 are drive circuits. Note that the drive circuits DAI to DA4 are the third
It is connected to each of the power transistors Q+ to Q4 of the full bridge type inverter shown in the figure.

In addition, DRV in the figure indicates a drive signal generation circuit.
The input terminal 1.2 is connected to the secondary winding NS4, and the output terminals 3 to 6 are connected to the photodiodes Po+ to PO of the photocoupler.
Connected to 4. Also, the photodiode Po+~P
O4 is connected to the inlet J terminal 1 via current limiting resistors R1 to R4.

In addition, in the same figure, the power transistors Q1 to Q4 of the inverter
The diodes connected between the collector and emitter of the DC superimposing diodes are omitted.

In FIG. 10, the power supply voltage E1 is converted into an alternating current voltage by the switching circuit S and applied to the primary winding N1 of the transformer T1.

A transformed AC voltage is taken out from the bias windings Ns+ to NS4, rectified by diodes DAI to D4, smoothed by capacitors CAT to CA4, and a DC voltage is obtained, which is used for drive circuits DQ1 to DQ4 and drive signal generation. It becomes the power supply for circuit DRV.

Note that drive circuits DQ+ to DQ4 receive drive signals through photocouplers and drive power transistors 01 to Q4.

Here, the drive signal is generated as follows.

First, the auxiliary power supply voltage across the capacitor CA4 becomes the power supply for the drive signal generation circuit DRV.

In the drive signal generation circuit DRV, the fifth
A signal is generated according to the time chart shown in the figure (described later).

This signal is output from output terminal 3 of the drive signal generation circuit DRV.
6 and is output from the photocoupler's photodiode Po.
+ to drive PO4. Note that the phototransistor of the photocoupler is provided in the drive circuits DQI to DQ4.

FIG. 11 is a circuit diagram without showing the structure of another embodiment of the auxiliary power supply circuit. .

In this embodiment, an auxiliary power source is generated by providing a dedicated switching circuit.

In the figure, El is a DC power supply, QAUX is a switching transistor, Dp + is a diode for circuit protection when the input power supply is reversely connected, RP1 is a starting resistance of transistor Q, RP2 is a base resistance of transistor Q4u,
CP 2 is a speed up capacitor, CP 3 and RP
3 indicates a capacitor and a resistor that constitute the snubber circuit.

TA is a converter transformer for auxiliary power supply, Np]
is the primary winding of the converter transformer TA, Np2 is the drive winding of the switching transistor Q, Ns+~N
S4 is the secondary winding to converter transformer T, DAI~D
A4 is a rectifier diode, CAI to CA4 are smoothing capacitors, and DQI to DQ4 are drive circuits.
It is connected to each of the power transistors 01 to Q4 of the full bridge type inverter shown in FIG.

In addition, DRV in the figure is the same drive signal generation circuit as shown in FIG. 10, and the input terminal 1.2 is connected to the secondary winding NS4.
The output terminals 3 to 6 are connected to photodiodes Po+ to PO4 of a photocoupler. Moreover, the photodiodes Pa+~PD4 are current limiting resistors R1~R4.
It is connected to input terminal 1 via. Also in the same figure, the diodes for direct current superimposition connected between the collectors and emitters of the power transistors 01 to Q4 of the inverter are omitted.

- Then, in FIG. 11, the power supply voltage E1 is converted into an alternating current voltage by the switching transistor Qp,v< and is applied to the primary winding N1.1 of the transformer TA.

A transformed AC voltage is taken out from the secondary windings NS+ to NS4, rectified by diodes DAI to DA4, smoothed by capacitors Cx+ to CA4, and a DC voltage is obtained, which becomes the power source for the drive circuits DQs to DQ4. .

The drive circuits DQ+ to DQ4 receive drive signals through photocouplers, and power 1 transistors 01 to Q4.
to drive.

FIG. 12 is a diagram showing an example of the configuration of drive circuits Do 1 to DQ4 in FIGS. 10 and 11. In addition, i shows 1-4 below.

In the same figure, 1.2 is an input terminal, 3.4 is an output terminal,
Po+ indicates a phototransistor of a photocoupler coupled to a photodiode Pot.

Also, R51SR61 is a resistor, Qo+ is a transistor, 3
．． 4 indicates an output terminal.

Note that the output terminal 3.4 is connected between the base and emitter of the transistor Q1 of the inverter (2) shown in FIG.

In this figure, the phototransistor Pcz (
i=1~4) is the photodiode Po+(i
= 1 to 4).

The signal of this phototransistor is amplified by drive 1 to transistor Qo+, and the power 1 of the inverter I is
~ Drive transistor QI (!=1 to 4).

That is, when the photodiode po+ is in the ON state, the phototransistor Po+ is in the ON state.

Then, the drive transistor Qo+ becomes OFF state, and from power 1 to transistor Q+, (terminal 1) → (resistance R
61) →(The base of the power transistor Q) A current flows through the path, and the power transistor Q is turned on.

Therefore, in order to make the time chart of the power transistor Q1 as shown in FIG.
It is sufficient to match the current to the time chart shown in FIG.

Finally, the configuration of the drive signal generating circuit DRV which operates the power transistor Q+ (!=1 to 4) according to the time chart shown in FIG. 7 will be explained.

This drive signal generation circuit DRV consists of (a) an oscillation circuit that generates a high frequency signal (Fig. 13), (b> a logic circuit that converts a high frequency signal into a low frequency signal (Fig. 14), and (C) the logic circuit described above. FIG. 13 is a diagram showing the configuration of the above-mentioned J/C circuit, which is composed of a transmission circuit (FIG. 15) that transmits the signal generated in the power transistor drive circuit to the drive circuit of the power transistor.

In the figure, INV+ to INV3 are three inverters connected in series, Rv+ is a resistor connected in parallel with these inverters, RT2 is a resistor connected in series with these inverters, and CT is connected in parallel with these inverters. It is a capacitor.

FIG. 14 is a diagram showing the configuration of the logic circuit.

In the same figure, INV4 to INV++ are inverters,
NAND 1 to NAND7 are NAND gates, NOR+
~N0R4 is a NOR gate, and BC is a binary counter.

FIG. 15 is a diagram roughly showing the configuration of the transfer circuit.

In the same figure, Dz is a Zener diode, QP, QP,
Q11 to Q14 are transistors.

The operation of the drive signal generation circuit DRV will be described below with reference to FIG. 16, taking as an example the case where the drive signals for the power transistors Q1 and Q02 are generated.

In the logic circuit shown in FIG. 14, each drive signal is output from the CJa terminal which is the output of the inverter INV7 and the D terminal which is the output of the inverter INVa.

That is, the C terminal is connected to the base of the transistor Q1, the D terminal is connected to the transistors 1 to Q2, and each terminal turns on the power transistor when the transistor is at torque.

(1) When transistors Q1 and 02 are both turned off (corresponds to period ■ in Fig. 16) In the binary counter BC in Fig. 14, output Q9 (i high position bit) is set to trubel, and output Q+ (lowest All consecutive output bits from P1 to Q8 are set to trubel or trubel.

(2) When turning 1 to Ranjisk Q1 OFF and QP ON (corresponding to period ■ in Figure 16), the output Q9 of binary counter BC is set to I level, and all consecutive output bits from output 01 to QB Gato! Avoid reaching the same level, or prevent everything from reaching the same level.

(3) When transistor Q1 is turned ON and QP is turned OFF (corresponding to period 3 in FIG. 16), output Q9 of binary counter BC is set to trubel. Outputs 01 to Q8 may be at any level.

(4) 1 - This state cannot occur when transistors Q1 and QP are both turned on.

The output turn of the binary counter BC as described above is obtained by the oscillation circuit dividing the high frequency signal input from the terminal A and converting it into a low frequency signal.

Note that the period of the oscillation circuit shown in FIG. 13 is T=−Rv
+・CT (K is a constant of proportionality).

As mentioned above, the output of the ringer power supply is 20Hz = 50r
rlS is specified.

Further, the consecutive output bits of outputs 01 to Q9 of the binary counter BC are 28=256 counts, and the cycle for one output count is 50 (ms)/256-:195 (μs).

Therefore, the values of the capacitor CT and the resistor RTI may be determined so that the period T of the oscillation circuit is 195 μs.

Furthermore, in the circuit of FIG. 15, the power supply Vc of the logic IC
When c becomes more than the zener of the zener diode Dz (
When the logic IC operates normally), transistor Qz turns on and clears the binary counter BC (CLEA).
R> terminal becomes trubel and starts counting. At the same time, transistor QP is turned on and the collectors of transistors Qz to Q14 are connected to power supply Vcc.

On the other hand, when the power supply Vcc becomes lower than the Zener voltage, the collectors of the drive transistors Qz to QI4 and the power supply CC are disconnected.

This is to prevent a situation where a signal with a different timing is applied to the base of the power transistor due to a malfunction of the logic IC when the power supply Vcc is low, causing a short circuit or the like and damaging the power transistor.

According to FIG. 17, how to obtain consecutive output bits in the binary counter BG will be explained.

In Figure 14, outputs Q1 to Q3 are taken, but the period of the power transistor drive signal can be increased or decreased by increasing or decreasing the number of consecutive output bits without changing the period of the oscillation circuit. I can do it.

In this case, it is not necessarily necessary to select the least significant bit Q1, and if we take the middle Q, to Q, then 2%+'
-10 counter, time Tc to count from 01 to Qk = 2'-'XT.

are transistors Q1 and 02 or transistors Q3 and 0
4 dead time. Note that To is the period of the oscillation circuit.

Thus, the put-time of the ringer output is
Since it is the sum of the dead times of transistors 1 and 02 and transistors Q3 and 04, Td=2'T.

becomes.

In the embodiments shown in FIGS. 10 and 11, the drive signal generation circuit DR is insulated from the drive circuits DQ1 to DQ4. However, by obtaining the power supply for the drive signal generation circuit DRV from CA3, for example, the drive signal It is also possible to hold the generation circuit DRV at the same potential as DQ 2 and DQ 4.

In this case, there is no need to isolate the drive circuits DQ 2 , DQ 4 and the drive signal generation circuit DRV in terms of direct current, and the output terminals 4 and 6 of the drive circuits DQ 2 , DQ 4 and the drive signal generation circuit DRV The photocoupler between can be omitted.

[Effects of the Invention] As explained above, the ringer power supply of the present invention eliminates the low frequency switching on the primary side of the transformer of the DC/AC inverter, which was indispensable in the past, so The size is reduced and the device can be made smaller.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a first configuration example of an inverter in the device according to the embodiment, and FIG. 3 is a circuit diagram showing a first configuration example of an inverter in the device according to the embodiment. 4 and 5 are diagrams showing the flow of direct current in each case of the circuit shown in FIG. 3, and FIG. 6 is a circuit diagram showing the second configuration example. A time chart showing the 0N10FF time relationship, Figure 7 is the 0N10 of the transistor in the circuit shown in Figure 3.
Time chart 1 showing the FF time relationship, Figure 8 is a diagram showing the flow of direct current during the dead time period of the transistor in the circuit shown in Figure 3, and Figure 9 is a diagram showing the flow of DC during the dead time period of the transistor in the circuit shown in Figure 3. Figure 10 is a circuit diagram illustrating the first configuration example of the auxiliary power supply circuit of the circuit shown in Figure 3. Figure 11 is a diagram illustrating the second configuration example of the auxiliary power supply circuit. 12 is a circuit diagram showing the configuration of the drive circuit in the circuit shown in FIGS. 10 and 11, and FIGS. 13 to 15 are the circuit diagrams showing the drive circuit in the circuit shown in FIGS. 10 and 11. FIG. 16 is a diagram showing the configuration of each part of the signal generation circuit. FIG. 16 is a diagram explaining the operation of the drive signal generation circuit. FIG. 17 is a diagram explaining the binary counter in the drive signal generation circuit.
The figure is a circuit diagram showing the configuration of a conventional telephone exchange, Figures 19 and 20 are diagrams explaining why the size of the transformer becomes large in the conventional telephone exchange VA equipment, and Figure 21 is a circuit diagram of the conventional telephone exchange. 2 is a diagram showing the insertion position of the current transformer B1t. El, E2...DC power supply S......Switching circuit■
・・・・・・・・・・・・・・・Trans R・・・・・・
・・・・・・・・・ Rectifier and smoothing circuit■・・・・・・・・・
・・・・・・Inverter 01 to Q4・・・Discrete transistor DRV・・・・・・Drive signal generation circuit Qa
1 to DQ4...Drive circuit Fig. 4 Fig. 5 Fig. 8 Fig. 9 CT Fig. 19 Fig. 20

Claims (5)

[Claims] (1) A first switching circuit that converts input DC into AC by high-frequency switching with a switching element, a converter transformer connected to this switching circuit, and a smoothing circuit connected to the secondary side of this converter transformer. a second switching circuit that is connected to the output terminal of the smoothing circuit and converts the input direct current into alternating current by low frequency switching with a transistor bridge; and the primary side, secondary side or smoothing circuit of the converter transformer. 1. A power supply device for a telephone exchange, comprising: a current detection element that is provided at an output stage of the switching element and detects a current to perform feedback control of a duty factor of the switching element. (2) The power supply device for a telephone exchange according to claim 1, wherein the current detection element is a current transformer, and this current transformer is provided on the primary side or secondary side of the converter transformer. (3) A power supply device for a telephone exchange according to claim 1, wherein the current detection element is a resistor, and this resistor is provided at the output stage of the smoothing circuit. (4) The power supply device for a telephone exchange according to any one of claims 1 to 3, wherein the second switching circuit is a half-bridge type switching circuit. (5) Claims 1 to 3, wherein the second switching circuit is a full-bridge switching circuit.
A power supply device for a telephone exchange power supply device according to any one of the paragraphs.