JP2006204000A - Inverter circuit and photovoltaic generator device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter circuit which can suppress the low frequency components of an input current and also can reduce power loss while using a small-capacity input capacitor. <P>SOLUTION: It turns on one hand of n-type MOS transistors Q2 and Q3, according to the polarity of AC voltage vac, and switches an n-type MOS transistor Q1 in this condition. Thus, an AC current is outputted from terminals TN3-TN4. Moreover, in parallel with this, it controls the time ratio of ON and OFF of n-type MOS transistors Q4 and Q5, so that an average current idc inputted in TN1-TN2 on DC side may be constant. Power is transmitted in both directions between a capacitor Cs and the terminals TN1-TN2 on DC side so that the low frequency components of the input current at the terminals TN1-TN on DC side may be suppressed by this control. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an inverter circuit that converts an input DC voltage into an AC current, and a grid-connected photovoltaic device that converts a DC voltage generated in a photovoltaic cell into an AC voltage and outputs the AC voltage to a system line. .

Patent Document 1 relates to a photovoltaic device that outputs the generated power of a photovoltaic cell as an alternating current to a system line, and an inverter circuit suitable for the photovoltaic device.
In general, the power generated by a photovoltaic cell with a constant amount of light has the property of being maximized at a specific voltage and current. Therefore, an inverter circuit connected to the next stage of the photovoltaic cell is required to have an ability to keep the current on the input side constant so as not to deviate from the maximum power operating point. The inverter circuit described in this document makes it possible to suppress fluctuations in the input current with a simple configuration without using a large-capacitance capacitor on the input side.
JP 2003-289678 A

The inverter circuit of the above document has such excellent characteristics, but has the following disadvantages.
In this inverter circuit, the transformer is excited and its energy is released twice during one switching period. That is, when the electric power input from the DC side is once stored in the capacitor and when the electric power of the capacitor is output to the AC side, the transformer is excited and released of energy, respectively.

  Therefore, the period during which the transformer can be used for power output to the AC side is shortened during one switching cycle, and an excitation current having a large peak value must be passed through the transformer in a short period. In general, the effective value of an electric signal increases as the peak value increases even if the average value is equal. Therefore, the effective value of the current flowing through the transistor or the like increases, and the power loss in these elements increases.

  The present invention has been made in view of such circumstances, and an object thereof is to reduce fluctuations in current and voltage on the DC side and reduce power loss without using a large-capacitance capacitor on the DC side. An object of the present invention is to provide an inverter circuit that can be used.

The present invention is an inverter circuit that converts a direct current voltage input to a first node pair into an alternating current and outputs the alternating current to the second node pair. A transformer including a winding; a first switch connected in series with the first winding; a capacitor; and transferring power in both directions between the capacitor and the first node pair. Converter circuit, a series circuit of a second switch and a third switch connected in parallel to the second winding, and turning on the first switch, the second switch, and the third switch And a second control circuit for controlling the transmission of power in the converter circuit so that the average voltage or current input at the first node pair is constant. Have
A series circuit of the first winding and the first switch is connected between the first node pair.
The connection node between the second switch and the third switch is connected to one node of the second node pair, and the tap of the second winding is connected to the other node of the second node pair. The
The first control circuit turns on the first switch and turns off the second switch and the third switch in the first mode, and turns off the first switch in the second mode following the first mode. The switch is turned off, and either the second switch or the third switch selected according to the polarity of the voltage on the AC side applied to the second node pair is turned on, and the second mode is switched from the first mode to the second mode. The control up to the mode is periodically repeated.

According to the present invention, in the first mode, a DC voltage input to the first node pair is applied to the first winding via the first switch, and the first winding is excited. . Next, in the second mode, the excitation energy of the transformer accumulated by the excitation of the first winding is discharged as a current from the second winding. This current is output from the second node pair via either the second switch or the third switch corresponding to the polarity of the AC voltage applied to the second node pair. Such control from the first mode to the second mode is periodically repeated, and an alternating current is output from the second node pair.
Therefore, when the first mode and the second mode are set to one cycle, the excitation and energy release of the transformer are performed once during one cycle.
In parallel with the above-described control, in the converter circuit, bidirectionally between the capacitor and the first node pair so that the average voltage or current input in the first node pair is constant. Electric power is transmitted. Thereby, the voltage or current input / output in the first node pair is controlled to be constant.

Preferably, the capacitor has one terminal connected to one node of the first node pair. The converter circuit includes a fourth switch connected between the other terminal of the capacitor not connected to the first node pair and the other node of the first node pair not connected to the capacitor. And a fifth switch, a fourth switch and a connection node of the fifth switch, and an inductor connected between one terminal of the capacitor connected to the first node pair . The second control circuit controls ON and OFF of the fourth switch and the fifth switch so that the average voltage or current input in the first node pair is constant.
In this case, the present invention may include a clamp circuit that clamps the surge voltage generated in the first switch to a combined voltage of the voltage of the first node pair and the voltage of the capacitor. The clamp circuit may include, for example, a diode connected between the other terminal of the capacitor not connected to the first node pair and the connection node of the first winding and the first switch. .

  Preferably, the second switch and the third switch change from on to off when the on-current flowing from the second winding is stopped in the second mode, and the first control circuit includes: In the state where the on-current flowing from the second winding to the second switch or the third switch is extinguished, the mode is shifted from the second mode to the first mode.

Furthermore, preferably, the present invention includes a current detection circuit that detects a current flowing through the first winding, and the first control circuit has a second detection value of the current detection circuit in the first mode. When the command value of the alternating current flowing through the mode pair is reached, the mode shifts from the first mode to the second mode.
As a result, the current flowing through the second node pair is controlled to a level corresponding to the command value.

  According to the present invention, fluctuations in current and voltage on the DC side can be suppressed without using a large-capacitance capacitor on the DC side, and the effective value of the excitation current flowing in the transformer can be reduced to reduce power loss. Reduction can be achieved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing a configuration example of a photovoltaic device according to the present embodiment, which is configured by connecting a plurality of photovoltaic modules in parallel.
The photovoltaic device shown in FIG. 1 has n photovoltaic modules (MD1 to MDn), and current output terminals thereof are connected in parallel to the system line UL.
Each of the photovoltaic modules (MD1 to MDn) includes one or more photovoltaic cells PV and an inverter circuit IVT that converts the DC voltage into an AC current.

  In this photovoltaic system, in each photovoltaic module (MD1 to MDn), the generated voltage of the photovoltaic cell PV is converted into an alternating current by the inverter circuit INV and output to the system line UL. Therefore, even if the generated power of the photovoltaic modules (MD1 to MDn) is supplied to the load connected to the system line UL and the generated power fluctuates according to the amount of light received by the photovoltaic cell PV, the load Is supplied with stable power from the system line UL.

FIG. 2 is a diagram illustrating a configuration example of the main circuit 100 of the inverter circuit IVT according to the embodiment of the present invention.
The main circuit 100 includes a transformer TR1, switches SW1,..., SW5, a diode D4, current detection units 6 and 8, a voltage detection unit 7, capacitors Ci, Co and Cs, inductors Lo and L1, and a direct current. It has side terminals TN1 and TN2, and AC side terminals TN3 and TN4.

  The transformer TR1 includes a winding W1 and a winding W2 provided with a tap TP. In this winding W2, one portion sandwiching the tap is the winding W21, and the other portion is the winding W22.

Switch SW1 includes an n-type MOS transistor Q1, a diode D1, and a drive circuit 1.
Switch SW2 includes an n-type MOS transistor Q2, a diode D2, and a drive circuit 2.
Switch SW3 includes an n-type MOS transistor Q3, a diode D3, and a drive circuit 3.
Switch SW4 includes an n-type MOS transistor Q4 and a drive circuit 4.
Switch SW5 includes an n-type MOS transistor Q5 and a drive circuit 5.

In the configuration of the inverter circuit IVT described above, the transformer TR1 is an embodiment of the transformer of the present invention.
Winding W1 is an embodiment of the first winding of the present invention.
Winding W2 is an embodiment of the second winding of the present invention.
The switch SW1 is an embodiment of the first switch of the present invention.
The switch SW2 is an embodiment of the second switch of the present invention.
The switch SW3 is an embodiment of the third switch of the present invention.
The capacitor Cs is an embodiment of the capacitor of the present invention.
The circuit including switches SW4 and SW5 and inductor L1 is an embodiment of the converter circuit of the present invention.
The switch SW4 is an embodiment of the fourth switch of the present invention.
The switch SW5 is an embodiment of the fifth switch of the present invention.
The inductor L1 is an embodiment of the inductor of the present invention.
The diode D4 is an embodiment of the clamp circuit of the present invention.

  First, connection of the components of the inverter circuit IVT described above will be described.

A terminal TN1 to which a positive DC voltage is applied is connected to the node N1, and a terminal TN2 to which a negative DC voltage is applied is connected to the node N2. However, the current detection unit 8 is inserted on the connection wiring between the terminal TN1 and the node N1.
Capacitor Ci is connected between nodes N1-N2.

  Switch SW1 and winding W1 are connected in series between nodes N1-N2. That is, the first terminal of the winding W1 (refers to a terminal marked with a circle. The same applies to other windings) is connected to the node N1, and the second terminal of the winding W1 (refers to a terminal without a circle). The same applies to the other windings.) Is connected to the node N2 via the switch SW1. However, the current detection unit 6 is inserted on the connection wiring between the first terminal of the winding W1 and the node N1.

  The circles attached to the windings of the transformer TR1 indicate the winding direction of the windings. That is, when a voltage is applied between the first terminal and the second terminal of any winding, a voltage having the same polarity is generated between the first terminal and the second terminal of the other winding.

In the switch SW1, the n-type MOS transistor Q1 and the diode D1 are connected in series with each other. That is, the drain of the n-type MOS transistor Q1 is connected to the second terminal of the winding W1, and its source is connected to the anode of the diode D1. The cathode of the diode D1 is connected to the node N2.
The drive circuit 1 applies a drive signal corresponding to a control signal Sq1 of the control unit 200, which will be described later, between the gate and source of the n-type MOS transistor Q1, and turns this on or off.

Capacitor Cs has one terminal connected to node N1.
The anode of the diode D4 is connected to the second terminal of the winding W1, and the cathode thereof is connected to the terminal on the side not connected to the node N1 of the capacitor Cs.

  The switch SW4 and the switch SW5 are connected in series, and the series circuit is connected between the terminal of the capacitor Cs that is not connected to the node N1 and the node N2.

In the series circuit of the switches SW4 and SW5, the drain of the n-type MOS transistor Q4 is connected to the capacitor Cs together with the cathode of the diode D4, and the source thereof is connected to the drain of the n-type MOS transistor Q5. The source of n-type MOS transistor Q5 is connected to node N2.
The drive circuits 4 and 5 apply drive signals according to control signals Sq4 and Sq5 of the control unit 300, which will be described later, between the gates and sources of the n-type MOS transistors Q4 and Q5, and turn them on or off.

  Inductor L1 is connected between connection node N5 of switches SW4 and SW5 and node N1.

  In winding W2 of transformer TR1, the first terminal of winding W21 is connected to tap TP together with the second terminal of winding W22. The tap TP is connected to the node N4.

  The switch SW2 and the switch SW3 are connected in series, and this series circuit is connected in parallel with the winding W2. That is, the second terminal of the winding W21 and the switch SW2 are connected, and the first terminal of the winding W22 and the switch SW3 are connected. A connection node between the switch SW3 and the switch SW4 is connected to the node N3.

In the switch SW2, the n-type MOS transistor Q2 and the diode D2 are connected in series with each other. That is, the drain of the n-type MOS transistor Q2 is connected to the second terminal of the winding W21, and its source is connected to the anode of the diode D2. The cathode of the diode D2 is connected to the node N3.
The drive circuit 2 applies a drive signal corresponding to the control signal Sq2 of the control unit 200 between the gate and the source of the n-type MOS transistor Q2, and turns it on or off.

In the switch SW3, the n-type MOS transistor Q3 and the diode D3 are connected in series with each other. That is, the source of the n-type MOS transistor Q3 is connected to the first terminal of the winding W22, and the drain thereof is connected to the cathode of the diode D3. The anode of the diode D3 is connected to the node N3.
The drive circuit 3 applies a drive signal corresponding to the control signal Sq3 of the control unit 200 between the gate and source of the n-type MOS transistor Q3, and turns it on or off.

The node N3 is connected to the AC side terminal TN3 via the inductor Lo, and is connected to the node N4 via the capacitor Co.
The inductor Lo and the capacitor Cs are smoothing circuits for attenuating the switching components of the inverter circuit at the AC side terminals TN3 to TN4.

  A voltage detector 7 is connected between the AC side terminals TN3 and TN4. The AC side terminal TN4 is connected to the node N4.

  Next, the control units 200 and 300 of the inverter circuit IVT according to the present embodiment will be described with reference to FIGS.

FIG. 3 is a diagram illustrating an example of the configuration of the control unit 200.
The control unit 200 includes an AC command value generation unit 201, a polarity determination unit 202, and a sequence control unit 203.
The control unit 200 is an embodiment of the first control circuit of the present invention.

  The AC command value generation unit 201 performs full-wave rectification on the voltage detection signal Svac between the AC side terminals TN3 and TN4 detected by the voltage detection unit 7, and further adjusts the amplitude according to the amplitude setting signal Samp. Then, an AC current command value signal SL2 is generated. The peak envelope of the pulse current flowing through the winding W1 during the operation of the inverter circuit has a waveform obtained by full-wave rectifying the output alternating current iac. The AC command value generation unit 201 generates a command value signal SL2 having a waveform similar to this peak envelope.

  The polarity determination unit 202 determines the polarity of the voltage vac between the AC terminals TN3 and TN4 based on the detection signal Svac of the voltage detection unit 7, and outputs the determination result as the polarity determination signal SP.

  The sequence control unit 25 receives the alternating current command value signal SL2, the polarity determination signal SP of the alternating voltage vac, and the current detection signal Si1 of the current detection unit 6, and based on these signals, the n-type MOS transistors Q1 to Q1. Control signals Sq1 to Sq3 for turning on / off Q3 are generated.

FIG. 4 is a diagram illustrating an example of the configuration of the control unit 300.
The control unit 300 includes an error amplification unit 301, a PWM signal generation unit 302, and a control signal output unit 303.
The control unit 300 is an embodiment of the second control circuit of the present invention.

  The error amplifying unit 301 amplifies an error between the detection signal Sidc of the input current idc of the DC terminals TN1 to TN2 by the current detection unit 8 and the command value signal SL3, and outputs it as an error signal.

  A PWM (pulse width modulation) signal generator 302 generates a logic signal that is pulse-width modulated in accordance with the error signal output from the error amplifier 301.

The control signal output unit 303 generates control signals Sq4 and Sq5 that turn on one of the n-type MOS transistors Q4 and Q5 and turn off the other in accordance with the logic signal output from the PWM signal generating unit 302.
In the control signals Sq4 and Sq5, a period (dead time) in which the n-type MOS transistors Q4 and Q5 are simultaneously turned off may be provided to prevent these transistors from being turned on simultaneously.

  Here, the operation of the inverter circuit IVT having the above-described configuration will be described.

  First, taking the switching sequence shown in FIG. 5 as an example, the switching operation of the n-type MOS transistors Q1, Q2, and Q3 based on the control of the control unit 200 will be described.

  FIG. 5 is a diagram illustrating an example of a switching sequence of the inverter circuit IVT according to the present embodiment. The symbol “◯” means that the transistors and diodes in the corresponding column are turned on, and the symbol “x” means that they are turned off.

  The “AC voltage polarity” in FIG. 5 indicates the polarity of the voltage vac at the terminals TN3 to TN4. Here, the case where the potential of the terminal TN3 is higher than the potential of the terminal TN4 is “positive”, and the opposite case is “negative”.

  As shown in FIG. 5, the switching sequence pattern in the sequence control unit 203 is divided into two patterns in which the AC voltage polarity is positive or negative. The sequence control unit 203 determines which switching sequence of these two patterns is used based on the polarity determination signal SP indicating the polarity of the AC voltage vac.

  In the following, the operation in each of the two switching sequences will be described in detail.

(1) When AC voltage polarity is 'positive'

FIG. 6 is a diagram illustrating an example of signal waveforms and operation states of each part of the inverter circuit IVT when the AC voltage polarity is “positive”.
FIG. 6A is a diagram illustrating a waveform example of the current detection signal Si1 of the current detection unit 6. A current i1 having a waveform similar to that in this figure flows through the winding W1.
FIG. 6B is a diagram illustrating a waveform example of the voltage v1 of the winding W1.
FIG. 6C is a diagram illustrating a waveform example of the current i2 flowing from the node N3 to the AC side terminal TN3.
FIGS. 6D to 6F are diagrams showing examples of the on / off states of the n-type MOS transistors Q1 to Q3.

  With reference to FIG. 6, two operation modes (M1p, M2p) in the case where the AC voltage polarity is “positive” will be described.

// mode M1p: period T1 //
In mode M1p, n-type MOS transistors Q1 and Q2 are turned on, and the other transistors are turned off.
In this case, since the voltage Vi of the DC side terminals TN1 to TN2 is applied to the winding W1 via the switch SW1 (FIG. 6B), an exciting current i1 that increases linearly flows in the winding W1. (FIG. 6 (A)). At this time, since a negative voltage is generated at the second terminal of the winding W21, the diode D2 is turned off, and the current i2 does not flow (FIG. 6C). That is, although the n-type MOS transistor Q2 is turned on, the switch SW2 is turned off.

  In this example, the n-type MOS transistor Q2 that is turned on in the next mode M2p is turned on in advance in the mode M1p. However, in the mode M1p, it is sufficient that at least the switch SW2 is turned off. May be turned off.

// mode M2p: periods T2 and T3 //
When current i1 increases linearly and current detection signal Si1 reaches alternating current command value signal SL2 (FIG. 6A), sequence control unit 203 shifts from mode M1p to mode M2p. In mode M2p, n-type MOS transistor Q2 is turned on and the other transistors are turned off.

  When the n-type MOS transistor Q1 is switched from on to off during the transition from the mode M1p to the mode M2p, a voltage is generated in each winding of the transformer TR1 so that the magnetic flux due to the excitation current i1 before this switching is maintained. . Due to this voltage, a positive voltage is generated at the second terminal of the winding W21, a forward voltage is applied to the diode D2 via the n-type MOS transistor Q2, and the diode D2 is turned on. Thereby, the excitation energy accumulated in the transformer TR1 in the period T1 is released as a current from the winding W21, and this current is output to the AC side via the switch SW2 (FIG. 6C).

  When the discharge of the excitation energy of the transformer TR1 is completed and the current output from the winding W21 is stopped, the diode D2 is turned off (period T3).

  An alternating current is output from the AC side terminals TN3 to TN4 by periodically repeating the above-described switching sequence with the period T1 to T3 as one period Ts1.

(2) When AC voltage polarity is negative

  Also in this case, there are two operation modes (M1n, M2n) as in (1) above. The modes M1n and M2n are modes corresponding to the above-described modes M1p and M2p, respectively, and both are the same regarding the operation of the DC side switch (SW1). The difference from the above (2) is the operation of the AC side switches (SW3, SW4).

// Mode 1n //
In mode M1n, n-type MOS transistors Q1 and Q3 are turned on, and the other transistors are turned off.
As a result, the voltage Vi of the DC side terminals TN1 to TN2 is applied to the winding W1 via the switch SW1, and an exciting current flows through the winding W1. At this time, since a positive voltage is generated at the first terminal of the winding W22, the diode D3 is turned off. That is, although the n-type MOS transistor Q3 is turned on, the switch SW3 is turned off.

  In this example, the n-type MOS transistor Q3 that is turned on in the next mode M2n is turned on in advance in the mode M1n. However, in the mode M1n, it is sufficient that at least the switch SW3 is turned off. May be turned off.

// Mode M2n //
When exciting current i1 of winding W1 increases linearly and current detection signal Si1 reaches command value signal SL2 of alternating current, sequence control unit 203 shifts from mode M1n to mode M2n. In mode M2n, n-type MOS transistor Q3 is turned on and the other transistors are turned off.

When the n-type MOS transistor Q1 is switched from on to off during the transition from the mode M1n to the mode M2n, a negative voltage is generated at the first terminal of the winding W22, and the diode D3 is forwarded to the diode D3 via the n-type MOS transistor Q3. A direction voltage is applied, and the diode D3 is turned on. Thereby, the excitation energy accumulated in the transformer TR1 in the period of the mode M1n is discharged as a current from the winding W22, and this current is output to the AC side via the switch SW3.
When the discharge of the excitation energy of the transformer TR1 is completed and the current output from the winding W22 is stopped, the diode D3 is turned off.

  By repeating the switching sequence described above periodically, AC power is output from the AC side terminals TN3 to TN4.

  The switching operation of the n-type MOS transistors Q1, Q2, Q3 based on the control of the control unit 200 has been described above.

The switching operation described above makes it possible to output an alternating current iac from the alternating-current side terminals TN3 to TN4. However, with this operation alone, vibration at a low frequency on the alternating-current side occurs in the direct-side voltage and current.
In the inverter circuit IVT according to the present embodiment, a converter circuit including switches SW4 and SW5 and an inductor L1 is provided in order to eliminate this low-frequency vibration. This converter circuit is a circuit capable of transmitting power bidirectionally between the capacitor Cs and the DC side terminals TN1 to TN2. Control unit 300 switches switches SW4 and SW5 such that current idc input at DC side terminals TN1-TN2 is constant, and controls the transmission of power in the converter circuit.

  Hereinafter, power transmission operation in the converter circuit will be described.

FIG. 7 is a diagram for explaining the waveforms and operating states of each part of the converter circuit.
FIG. 7A is a diagram illustrating a waveform example of the current iL flowing through the inductor L1.
FIG. 7B is a diagram showing a waveform example of the current iq5 flowing through the n-type MOS transistor Q5.
FIG. 7C is a diagram showing a waveform example of the current iq4 flowing through the n-type MOS transistor Q4.
FIG. 7D shows an on / off state of n-type MOS transistor Q5.
FIG. 7E is a diagram showing an on / off state of the n-type MOS transistor Q4.

  In period T4, control unit 300 sets n-type MOS transistor Q5 on and n-type MOS transistor Q4 off. Thereby, the inductor L1 and the DC side terminals TN1-TN2 are connected in parallel, and the current flows from the DC side terminals TN1-TN2 to the inductor L1 with the current flowing in the inductor L1 immediately before the period T4 as an initial value. This current changes at a constant time slope when the inductor L1 is excited by the voltage Vi of the DC side terminals TN1 to TN2.

  Next, in the period T5, the controller 300 sets the n-type MOS transistor 5 off and the n-type MOS transistor Q4 on. Thereby, the inductor L1 and the capacitor Cs are connected in parallel, and the current flows through the capacitor Cs with the current flowing through the inductor L1 at the end of the period T4 as an initial value. This current changes at a constant time slope when the inductor L1 is excited by the voltage Vcs of the capacitor Cs. However, since the polarity of the voltage applied to the inductor L1 is opposite to that in the period T4, the current in the inductor L1 changes in a direction to cancel the change in the period T4.

  The controller 300 periodically repeats the switching operation for alternately turning on the n-type MOS transistors Q4 and Q5 with the periods T4 and T5 as one switching cycle Ts2. Thereby, as shown in FIG. 7A, the current of the inductor L1 alternately changes to the opposite polarity in accordance with the switching operation.

  Here, when the polarity of the current iL flowing in the inductor L1 is defined with the direction of flowing from the node N1 to the node N5 being “positive” and the opposite direction being “negative”, the ON period of the n-type MOS transistor Q5 is the n-type MOS transistor Q4. As the ON period becomes longer, the amount of change of the current iL to “positive” in one switching period becomes larger than the amount of change of “negative”, so that the current iL increases to “positive”. Conversely, the current iL increases to 'negative' as the ON period of the n-type MOS transistor Q5 becomes shorter than the ON period of the n-type MOS transistor Q4.

  On the other hand, when the current iL is “positive”, an average current flows from the DC side terminals TN1 to TN2 toward the inductor L1, and an average current flows from the inductor L1 toward the capacitor Cs. That is, power is transmitted from the DC side terminals TN1-TN2 to the capacitor Cs. On the contrary, when the current iL is “negative”, power is transmitted from the capacitor Cs to the DC side terminals TN1 to TN2.

  Therefore, the control unit 300 controls the ratio between the ON period and the OFF period of the n-type MOS transistors Q4 and Q5, so that the direction and magnitude of the power transmitted between the DC side terminals TN1-TN2 and the capacitor Cs are controlled. Is controlled.

For example, if the current value detected by the current detection unit 8 is larger than the current value of the command value signal SL3, the error is amplified by the error amplification unit 301 and converted into a change in pulse width by the PWM signal generation unit 302. The control signals Sq4 and Sq5 are generated so that the ON period of the n-type MOS transistor Q5 becomes longer. As a result, the power transmitted from the capacitor Cs to the DC side terminals TN1-TN2 decreases (or the power transmitted from the DC side terminals TN1-TN2 to the capacitor Cs increases), and the input current of the DC side terminals TN1-TN2 idc becomes smaller.
Conversely, when the current value detected by the current detection unit 8 is smaller than the current value of the command value signal SL3, the control signals Sq4 and Sq5 are generated so that the ON period of the n-type MOS transistor Q5 is shortened. The input current idc of the DC side terminals TN1-TN2 increases.
Due to such negative feedback, the input current idc of the DC side terminals TN1 to TN2 is controlled so as to approach the current of the command value signal SL3.

As described above, according to the inverter circuit IVT according to the present embodiment, in the first mode (M1p, M1n), the voltage Vi input to the DC side terminals TN1-TN2 is wound through the switch SW1. Applied to W1, the winding W1 is excited. Next, in the second mode (M2p, M2n), the excitation energy of the transformer TR1 accumulated by the excitation of the winding W1 is released as a current from the winding W21 or W22. This current passes through one of the switches SW2 and SW3 selected according to the polarity of the AC voltage vac of the AC side terminals TN3 to TN4, passes through the smoothing circuit (Lo, Co), and passes to the AC side terminals TN3 to TN4. Is output. Such control from the first mode to the second mode is periodically repeated, and an alternating current is output from the AC side terminals TN3 to TN4.
Thus, according to this embodiment, it is possible to convert the DC voltage input from the DC side terminals TN1 to TN4 into an AC current and output the AC current from the AC side terminals TN3 to TN4.

  In addition, according to the inverter circuit IVT according to the present embodiment, in parallel with the control described above, the converter circuit and the DC are connected by the converter circuit so that the average current input at the DC side terminals TN1 to TN2 is constant. Power is transmitted bidirectionally between the side terminals TN1 and TN2.

FIG. 8 shows the waveforms of the power P12 input to the DC side terminals TN1-TN2 of the inverter circuit IVT according to the present embodiment, the power P34 output from the AC side terminals TN3-TN4, and the power Pcs discharged from the capacitor Cs. It is a figure which shows an example.
As shown in FIG. 8A, the power P34 of the AC side terminals TN3-TN4 fluctuates at twice the frequency of the AC voltage vac. If the converter circuit described above is not provided, this low frequency power fluctuation appears at the DC side terminals TN1 to TN2. Therefore, in order to attenuate the ripple component of the voltage and current, the capacitance of the capacitor Ci is very large. Need to do.
On the other hand, when the converter circuit described above is provided and the average input current of DC side terminals TN1-TN2 is controlled to be constant, as shown in FIG. 8A, power P12 of DC side terminals TN1-TN2 is set. Becomes a certain level according to the average value of the power P34 of the AC side terminals TN3-TN4. On the other hand, the electric power Pcs of the capacitor Ci fluctuates following the fluctuation of the electric power P34, as shown in FIG. This is because power is transmitted bidirectionally between the DC side terminals TN1-TN2 and the capacitor Ci so as to equalize the power fluctuations of the DC side terminals TN1-TN2.
Therefore, according to the present embodiment, it is possible to make the capacitance of the input capacitor Ci very small while effectively suppressing low frequency components of voltage and current on the DC side of the inverter circuit.

  Since the capacitance of the input capacitor Ci can be reduced, it is possible to replace a large-volume capacitor such as an electrolytic capacitor used in a conventional inverter circuit with a small-volume capacitor such as a film capacitor. Can be reduced in size and weight. Moreover, since the problem of the lifetime peculiar to an electrolytic capacitor can be avoided, the reliability of an apparatus can be improved.

  Furthermore, according to the inverter circuit IVT according to the present embodiment, the excitation of the transformer TR1 and the release of its energy may be performed once during one switching cycle, so that the effective value of the excitation current flowing through the transformer TR1 is reduced. can do. Thereby, power loss in circuit elements such as transistors and diodes can be reduced.

Moreover, since the switching operation of the n-type MOS transistors Q1, Q2, and Q3 based on the control of the control unit 200 and the switching operation of the n-type MOS transistors Q4 and Q5 based on the control of the control unit 300 are independent of each other, The switching frequency can be set independently. The switching frequency of the control unit 200 is desirably high to some extent in order to improve the follow-up controllability of alternating current, but there is no problem with the switching frequency of the control unit 300 even if the amplitude of the ripple component of the capacitor Cs is slightly increased. The control unit 200 can be lower.
Therefore, the loss of the converter circuit can be reduced by lowering the switching frequency of the control unit 300. As a result, the increase in power loss due to the converter circuit can be kept smaller than the reduction in power loss due to the decrease in the effective value of the excitation current, improving the overall efficiency of the inverter circuit. Can be achieved.

  Further, since the connection node between the winding W1 and the switch SW1 is connected to the capacitor Cs through the diode D4, the surge voltage generated in the switch SW1 is the voltage Vi of the capacitor Cs and the voltage Vi of the terminals T1-T2. To the combined voltage (Vcs + Vi). Therefore, the stress of the switch SW1 due to the surge voltage can be reduced.

  So far, various preferred embodiments of the present invention have been described. However, the present invention is not limited to these embodiments, and various modifications can be made.

  For example, at least a part of the inductor L1 in the main circuit 100 shown in FIG. 2 may be realized by using a winding of a transformer as shown in FIG.

FIG. 9 is a diagram illustrating an example in which a winding of a transformer is used as the inductor L1 of the converter circuit. In the figure, the DC side circuit of the transformer is extracted from the main circuit of the inverter circuit, and the illustration of the AC side circuit is omitted.
The main circuit shown in FIG. 9 replaces the three-winding transformer TR1 in the main circuit 100 described above with a transformer TR2, uses one of the windings instead of the inductor L1, and detects the current in the winding W1. The part 6A is inserted on the connection wiring between the switch SW1 and the node N2. The sequence control unit 25 (FIG. 3) inputs the current detection signal Si1A of the current detection unit 6A instead of the current detection signal Si1.

The transformer TR2 has a winding W3 in addition to the windings W1, W21, W22 of the transformer TR1. A second terminal of winding W3 is connected to a first terminal of winding W1, and a first terminal of winding W3 is connected to a connection node N5 between switches SW4 and SW5.
With such a configuration, the core of the primary inductor (L1) and the transformer (TR1), which were independent in the example of FIG. Miniaturization can be achieved.

  The switches used in the present embodiment are not limited to n-type MOS transistors, and other various semiconductor switches (for example, IGBTs and thyristors) may be used.

  Moreover, the primary side converter circuit (circuit comprised by switch SW4 and SW5 and inductor (L1, W3)) shown in FIG.2 and FIG.9 is an example, and this invention is not limited to this. Any other converter circuit having such a function can be applied to this as long as it is possible to transmit power in both directions between the capacitor Cs and the DC side terminals TN1-TN2. You may do it.

  Furthermore, although the example which controls a converter circuit so that the input current of DC side terminal TN1-TN2 is kept constant is shown in embodiment mentioned above, it is not restricted to this, For example, DC side terminal TN1-TN2 The converter circuit may be controlled so that the average voltage inputted and outputted at is constant. In the case of the inverter circuit shown in FIGS. 2 and 9, for example, the voltage of the DC side terminals TN1-TN2 whose switching components are smoothed by the capacitor Ci may be detected, and the converter circuit may be controlled so as to be constant.

It is a schematic block diagram which shows the structural example of the photovoltaic device which concerns on this embodiment. It is a figure which shows the structural example of the main circuit of the inverter circuit which concerns on embodiment of this invention. It is the figure which showed an example of the structure of the 1st control part which concerns on embodiment of this invention. It is a figure which shows an example of a structure of the 2nd control part which concerns on embodiment of this invention. It is a figure which shows an example of the switching sequence of the inverter circuit which concerns on this embodiment. It is a figure which shows an example of the signal waveform and operation state of each part of an inverter circuit in case an alternating voltage polarity is "positive". It is a figure for demonstrating the waveform and operation state of each part of a converter circuit. It is a figure which shows the example of a waveform of the instantaneous electric power in each part of the inverter circuit which concerns on this embodiment. It is a figure which shows an example which uses the coil | winding of a transformer as an inductor of a converter circuit.

Explanation of symbols

MD1-MDn ... photovoltaic module, PV ... photovoltaic cell, IVT ... inverter circuit, TR1, TR2 ... transformer, W1-W3 ... winding, TP ... tap, SW1-SW5 ... switch, Q1-Q5 ... n-type MOS Transistors, D1 to D4 ... Diodes, Ci, Cs, Co ... Capacitors, L1, Lo ... Inductors, TN1, TN2 ... DC side terminals, TN3, TN4 ... AC side terminals, 1-5 ... Drive circuits, 6, 8 ... Current Detection unit, 7 ... Voltage detection unit, 200, 300 ... Control unit, 201 ... AC command value generation unit, 202 ... Polarity determination unit, 203 ... Sequence control unit, 301 ... Error amplification unit, 302 ... PTM signal generation unit, 303 ... Control signal output section

Claims (15)

An inverter circuit that converts a direct current voltage input to a first node pair into an alternating current and outputs the alternating current from the second node pair,
A transformer including a first winding and a second winding with a tap;
A first switch connected in series to the first winding;
A capacitor;
A converter circuit capable of transmitting power bidirectionally between the capacitor and the first node pair;
A series circuit of a second switch and a third switch connected in parallel to the second winding;
A first control circuit for controlling on and off of each of the first switch, the second switch, and the third switch;
A second control circuit for controlling transmission of power in the converter circuit so that an average voltage or current input in the first node pair is constant;
Have
A series circuit of the first winding and the first switch is connected between the first node pair,
The connection node between the second switch and the third switch is connected to one node of the second node pair, and the tap of the second winding is connected to the other node of the second node pair. Each connected,
In the first mode, the first control circuit turns on the first switch, turns off the second switch and the third switch, and continues to the second mode following the first mode. The first switch is turned off and either the second switch or the third switch selected in accordance with the polarity of the voltage on the AC side applied to the second node pair is turned on. And periodically repeating the control from the first mode to the second mode,
Inverter circuit. The capacitor has one terminal connected to one node of the first node pair,
The converter circuit is
A fourth switch connected between the other terminal of the capacitor not connected to the first node pair and the other node of the first node pair not connected to the capacitor; A series circuit with 5 switches;
An inductor connected between a connection node of the fourth switch and the fifth switch and one terminal of the capacitor connected to the first node pair;
Including
The second control circuit controls on and off of the fourth switch and the fifth switch so that an average voltage or current input in the first node pair is constant. ,
The inverter circuit according to claim 1. A clamp circuit that clamps a surge voltage generated in the first switch to a combined voltage of the voltage of the first node pair and the voltage of the capacitor;
The inverter circuit according to claim 2. The inductor includes a third winding of the transformer;
The inverter circuit according to claim 2 or 3. The second switch and the third switch change from on to off when the on-current flowing from the second winding in the second mode ceases,
The first control circuit shifts from the second mode to the first mode in a state where the on-current flowing from the second winding to the second switch or the third switch is cut off. ,
The inverter circuit as described in any one of Claims 1 thru | or 4. The second switch and the third switch each include a diode and a semiconductor switch connected in series, and the second node pair is connected from the second winding via the second switch. The conduction directions of the diodes are set so that the current flowing through the second winding and the current flowing from the second winding through the third switch to the second node pair have opposite polarities. ,
The inverter circuit according to claim 5. The first control circuit always turns off the semiconductor switch in one of the second switch and the third switch selected according to the polarity of the alternating current, and the semiconductor switch in the other switch At least in the second mode,
The inverter circuit according to claim 6. A current detection circuit for detecting a current flowing through the first winding;
In the first mode, the first control circuit starts from the first mode when the detection value of the current detection circuit reaches a command value of an alternating current flowing through the second mode pair. Transition to mode 2
The inverter circuit as described in any one of Claims 1 thru | or 7. The first switch includes a diode and a semiconductor switch connected in series.
The inverter circuit as described in any one of Claims 1 thru | or 8. A photovoltaic device having at least one photovoltaic cell, and an inverter circuit that inputs a voltage generated in the photovoltaic cell, converts the voltage into an alternating current, and outputs the alternating current to a system line,
The inverter circuit is
A transformer including a first winding and a second winding with a tap;
A first switch connected in series to the first winding;
A capacitor;
A converter circuit capable of transmitting power bidirectionally between the capacitor and the first node pair to which the power generation voltage of the photovoltaic cell is input;
A series circuit of a second switch and a third switch connected in parallel to the second winding;
A first control circuit for controlling on and off of each of the first switch, the second switch, and the third switch;
A second control circuit for controlling transmission of power in the converter circuit so that an average voltage or current input in the first node pair is constant;
Have
A series circuit of the first winding and the first switch is connected between the first node pair,
A connection node between the second switch and the third switch is connected to one node of the second node pair that outputs the alternating current, and a tap of the second winding is connected to the second node pair. Each connected to the other node of
In the first mode, the first control circuit turns on the first switch, turns off the second switch and the third switch, and continues to the second mode following the first mode. The first switch is turned off and either the second switch or the third switch selected in accordance with the polarity of the voltage on the AC side applied to the second node pair is turned on. And periodically repeating the control from the first mode to the second mode,
Photovoltaic generator. The capacitor has one terminal connected to one node of the first node pair,
The converter circuit is
A fourth switch connected between the other terminal of the capacitor not connected to the first node pair and the other node of the first node pair not connected to the capacitor; A series circuit with 5 switches;
An inductor connected between a connection node of the fourth switch and the fifth switch and one terminal of the capacitor connected to the first node pair;
Including
The second control circuit controls on and off of the fourth switch and the fifth switch so that an average voltage or current input in the first node pair is constant. ,
The photovoltaic device of Claim 10. A clamp circuit that clamps a surge voltage generated in the first switch to a combined voltage of the voltage of the first node pair and the voltage of the capacitor;
The photovoltaic device according to claim 11. The inductor includes a third winding of the transformer;
The photovoltaic device of Claim 11 or 12. The second switch and the third switch change from on to off when the on-current flowing from the second winding in the second mode ceases,
The first control circuit shifts from the second mode to the first mode in a state where the on-current flowing from the second winding to the second switch or the third switch is cut off. ,
The photovoltaic device according to any one of claims 10 to 13. A current detection circuit for detecting a current flowing through the first winding;
In the first mode, the first control circuit starts from the first mode when the detection value of the current detection circuit reaches a command value of an alternating current flowing through the second mode pair. Transition to mode 2
The photovoltaic device as described in any one of Claims 10 thru | or 14.

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