JPS6223146A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6223146A JPS6223146A JP60161938A JP16193885A JPS6223146A JP S6223146 A JPS6223146 A JP S6223146A JP 60161938 A JP60161938 A JP 60161938A JP 16193885 A JP16193885 A JP 16193885A JP S6223146 A JPS6223146 A JP S6223146A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- integrated circuits
- integrated circuit
- integration
- appearance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置、特に、面付実装型のメモリ用半導
体装置に適用して効果のある半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device that is effective when applied to a surface-mounted memory semiconductor device.
半導体装置の高集積化に対する１つの対策として、２つ
の半導体装置を重ね合わせ、各半導体装置のリードを互
いに接続した、いわゆるピギーバフタ方式の半導体装置
が提案されている。As one measure to increase the degree of integration of semiconductor devices, a so-called piggy-bafter type semiconductor device has been proposed in which two semiconductor devices are stacked one on top of the other and the leads of each semiconductor device are connected to each other.
ところが、この型式の半導体装置は一度パッケージ封止
を終了した２つの半導体装置を後工程において重ね合わ
せてそれぞれのリードを相互に接続するという面倒な作
業工程が要求される上に、その後でさらに特別な選別検
査を行う必要がある。However, this type of semiconductor device requires the laborious work process of stacking the two semiconductor devices once they have been packaged and connecting their leads to each other in the post-process. It is necessary to carry out a thorough screening test.
また、２つの半導体装置どうしを重ね合わせる構造のた
め、重ね方向の寸法がかなり大きくなり、外観も必ずし
も良くないという問題があることを本発明者は見い出し
た。In addition, the inventors have found that because of the structure in which two semiconductor devices are stacked one on top of the other, the dimensions in the stacking direction are quite large, and the appearance is not necessarily good.
また、最近では、多ピン化および小型化等を目的として
、いわゆるプラスチック・リーデツド・チップ・キャリ
ア（Ｐ Ｌ ＣＣ）型の半導体装置が提案されている。Furthermore, recently, a so-called plastic leaded chip carrier (PLCC) type semiconductor device has been proposed for the purpose of increasing the number of pins and downsizing the device.
ところが、通常のＰＬＣＣ型半導体装置は１個の半導体
素子しか搭載しておらず、さらに高集積化が要求されて
いる実状には不十分なものであることを本発明者は見い
出した。However, the inventors have discovered that a typical PLCC type semiconductor device is equipped with only one semiconductor element, and is insufficient for the actual situation where higher integration is required.
なお、とギーバソタ方式およびＰＬＣＣ型半導体装置に
ついては、日経マグロウヒル社、１９８４年６月１１日
発行の「マイクロデバイセズ」日経エレクトロニクス別
冊Ｎａ２、Ｐ１２１〜Ｐ１２８およびＰ１４８〜Ｐ１５
３に説明されている。Regarding the Giba Sota type and PLCC type semiconductor devices, please refer to "Micro Devices" Nikkei Electronics Special Issue Na2, published by Nikkei McGraw-Hill, June 11, 1984, P121-P128 and P148-P15.
It is explained in 3.
本発明の目的は、外観や寸法を変える必要な（高集積化
を実現することのできる半導体装置を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that requires changes in appearance and dimensions (and can achieve high integration).
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、１個の半導体装置内に互いに同じ構成の複数
個の集積回路が設けられることにより、複数倍の集積度
を得ることができ、パンケージの外観および寸法を変え
る必要なく高集積化を実現することができるものである
。In other words, by providing a plurality of integrated circuits with the same configuration in one semiconductor device, it is possible to obtain multiple times the degree of integration, and high integration can be achieved without changing the appearance and dimensions of the pancage. It is something that can be done.
〔実施例１〕
第１図は本発明の一実施例である半導体装置の素子およ
びビン配置を示す底面図、第２図は本発明を適用できる
一例としてのＰＬＣＣ型半導体装置の正面図である。[Example 1] Fig. 1 is a bottom view showing the arrangement of elements and bottles of a semiconductor device according to an embodiment of the present invention, and Fig. 2 is a front view of a PLCC type semiconductor device as an example to which the present invention can be applied. .
本実施例において、半導体装置１のパフケージ２内には
、それぞれ独立なメモリチップとして分離可能な互いに
同じ回路構成の２個の集積回路Ａ。In this embodiment, in the puff cage 2 of the semiconductor device 1, there are two integrated circuits A having the same circuit configuration, which can be separated as independent memory chips.
Ｂが並設され、かつ内部配線（図示せず）により互いに
電気的に接続されて封止されている。B are arranged in parallel, electrically connected to each other by internal wiring (not shown), and sealed.
集積回路ＡおよびＢは、良（知られた半導体集積回路技
術によって形成される。集積回路ＡおよびＢは、上記の
ように互いに同じ構成であり、互いに独立のチップを構
成してもよい、しかしながら、この実施例においては、
特に制限されないが半導体ウェハを分割して複数のチッ
プを得る場合、実質的に１つのチップとして得られもの
から構成される。特に制限されないが、各集積回路はア
ドレスマルチ方式のダイナミック型ＭＯＳメモリからな
る。集積回路ＡおよびＢに設けられる各端子は、後で説
明するように共通にされる。端子の共通化のために、集
積回路ＡおよびＢ上にアルミニウムからなるような配線
層が設けられる。Integrated circuits A and B are formed by well-known semiconductor integrated circuit technology. Integrated circuits A and B have the same configuration as described above, and may constitute mutually independent chips; however, , in this example:
Although not particularly limited, when a semiconductor wafer is divided to obtain a plurality of chips, the semiconductor wafer is substantially composed of the chips obtained as one chip. Although not particularly limited, each integrated circuit is composed of a multi-address dynamic MOS memory. Each terminal provided on integrated circuits A and B is made common as will be explained later. In order to share terminals, a wiring layer made of aluminum is provided on integrated circuits A and B.
各集積回路Ａ、Ｂは内部配線により、実質的にチップ選
択用のビンを構成するロー・アドレス・ストローブ（Ｒ
ｏｗ Ａｄｄｒｅｓｓ ５ｔｒｏｂｅ）用のピンＲＡＳ
ＡとＲＡＳＢにそれぞれ電気的に接続されている。Each integrated circuit A, B has a row address strobe (R
ow Address 5trobe) pin RAS
A and RASB are electrically connected to each other.
この半導体装置１における外部ビンとしては前記の２本
の他に、データ入力用のピンＤｉｎ、データ出力用のビ
ンＤｏｕｔ 、コラム・アドレス・ストローブ（Ｃｏｌ
ｕｍｎ Ａｄｄｒｅｓｓ ５ｔｒｏｂｅ ）用のピンＣ
ＡＳ１電源ピンＶＣＣ％グラウンド用のピンＶｓａ、ア
ドレス入力用の８本のビンＡｏ −Ａ＋ 、Ａ！ 、Ａ
ｓ、Ａ４、Ａｓ、Ａｉ、Ａｔ、さらには２本の非接続（
ノンコネクト）のピンＮＧ、ライト・イネーブル（Ｗｒ
ｉｔｅ Ｅｎａｂｌｅ）用のピンＷＥが用意されている
。In addition to the above two external bins in this semiconductor device 1, there is a pin Din for data input, a bin Dout for data output, and a column address strobe (Col).
Pin C for umn Address 5trobe)
AS1 power supply pin VCC% Pin Vsa for ground, 8 bins for address input Ao -A+, A! ,A
s, A4, As, Ai, At, and even two unconnected (
Non-connect) pin NG, write enable (Wr
ite Enable) pin WE is provided.
集積回路Ａ、Ｂの図示しない端子もしくはポンディング
パッドのうち、前記したピンに対応されるもののうち、
ビンＲＡＳＡ、、ＲＡＳＢ以外のビンに対応されるもの
はそれぞれ相当機能のビンにそれぞれ共通に接続されて
いる。Of the terminals or bonding pads (not shown) of integrated circuits A and B, which correspond to the above-mentioned pins,
Those corresponding to bins other than bins RASA, , RASB are commonly connected to bins of corresponding functions.
本実施例においては、２つの集積回路Ａ、Ｂはそれぞれ
ピンＲＡＳＡ、ＲＡＳ、Ｂで個別的にコントロールする
ことができるので、集積回路ＡまたはＢ単独搭載の場合
に比べて２倍のメモリ容量すなわち２倍の集積度を得る
ことができる。しかも、このような２倍の高集積化にも
かかわらず、半導体装置ｌのパフケージ２による封止後
の外形寸法や外観は通常のＩベレットのものと同じであ
り、内部配線も実質的に画集積回路Ａ、 Ｂを相互に接
続するためのアルミニウム配線層を追加するだけで足り
るので、通常の製造プロセスとほとんど同様のプロセス
で製造できる。In this embodiment, the two integrated circuits A and B can be individually controlled by pins RASA, RAS, and B, respectively, so the memory capacity is twice that of the case where integrated circuit A or B is mounted alone. Twice the degree of integration can be obtained. Moreover, despite the doubling of the integration, the external dimensions and appearance of the semiconductor device 1 after being sealed with the puff cage 2 are the same as those of a normal I pellet, and the internal wiring is also virtually identical. Since it is sufficient to add an aluminum wiring layer for interconnecting integrated circuits A and B, it can be manufactured using almost the same process as a normal manufacturing process.
〔実施例２〕
第３図は本発明の他の実施例である半導体装置の素子お
よびピン配置を示す底面図、第４図は本発明を通用でき
る他の例としてのｓｏｐ ＜スモール・アウトライン・
パッケージｉｓｍａｌｌ ＯｕｔｌｉｎｅＰａｃｋａｇ
ｅ ）型半導体装置の正面図である。[Embodiment 2] FIG. 3 is a bottom view showing the elements and pin arrangement of a semiconductor device according to another embodiment of the present invention, and FIG. 4 is a bottom view of a semiconductor device according to another embodiment of the present invention.
Package ismall OutlinePackag
It is a front view of an e) type semiconductor device.
本実施例２の場合、２個の集積回路Ａ、Ｂは互いに独立
に機能するものとして構成されている。In the case of the second embodiment, the two integrated circuits A and B are configured to function independently of each other.
そのため、ピンＲＡＳＡ、ＲＡＳＢの他に、データ入力
用のピンおよびデータ出力用のピンもそれぞれ集積回路
Ａ、Ｂ毎に別〃に別離し、各々にピンＤｉｎＡ、、Ｄｏ
ｕｔＡおよびＤｉｎＢ、ＤｏｕｔＢ、として別々に配線
されている。Therefore, in addition to pins RASA and RASB, data input pins and data output pins are also separated for each integrated circuit A and B, and pins DinA, Do
They are separately wired as utA, DinB, and DoutB.
したがって、本実施例２においては、各集積回路Ａ、
Ｂはそれぞれについて入出力ならびにコントロールが
別々になされるので、各集積回路Ａ。Therefore, in the second embodiment, each integrated circuit A,
B has input/output and control for each integrated circuit A separately.
Ｂがそれぞれ１ビツトを出力でき、合計２ピントのビッ
ト容量を同時に得ることができることになる。B can output 1 bit each, and a total bit capacity of 2 pins can be obtained at the same time.
（１１，１Ｊ［数個の集積回路を搭載し、かつ１つのパ
ンケージ内に封止してなることにより、半導体装置の外
観や寸法を変える必要なく高集積化を実現することがで
きる。(11,1J [By mounting several integrated circuits and sealing them in one pancake, high integration can be achieved without changing the appearance or dimensions of the semiconductor device.
（２）、各集積回路の入出力を共用して各回路をコント
ロールすることにより、複数倍のメモリ容量を得ること
ができる。(2) By sharing the input and output of each integrated circuit and controlling each circuit, it is possible to obtain multiple times the memory capacity.
（３）、各集積回路の入出力が各素子毎に互いに分離さ
れ、各回路が別々にコントロールされることにより、ピ
ント数を複数倍にすることができる。(3) By separating the input and output of each integrated circuit for each element and controlling each circuit separately, the number of points of focus can be multiplied.
（４）、前記（１１，（２１，＋３１において、各回路
相互の配線等は通常のものとほとんど変える必要がなく
、製造プロセスも容易である。(4) In the above-mentioned (11, (21, +31), there is almost no need to change the wiring between each circuit from the usual one, and the manufacturing process is easy.
（５）、後工程として特別な工程を必要とせず、検査、
選別等も容易である。(5) No special process is required as a post-process, inspection,
Sorting etc. is also easy.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.
たとえば、半導体装置の型式やビン数、ピン配列等につ
いて他のものを用いることは任意である。For example, it is optional to use other types of semiconductor devices, number of bins, pin arrangement, etc.
各集積回路は、製造工程の若干の複雑化がゆるされるな
ら、それぞれ独立の半導体ベレットから構成されてもよ
い。Each integrated circuit may be constructed from a separate semiconductor bullet, provided that some complication in the manufacturing process is tolerated.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるメモリ用のＤＲＡＭ
型半導体装置に適用した場合について説明したが、それ
に限定されるものではなく、たとえば、ＳＲＡＭ、ＥＦ
ＲＯＭ、Ｅ” ＰＲＯＭ等についても広く適用できる。The above explanation will mainly focus on the invention made by the present inventor in DRAM for memory, which is the field of application that formed the background of the invention.
Although the case where it is applied to a type semiconductor device has been described, it is not limited thereto; for example, SRAM, EF
It can also be widely applied to ROM, E"PROM, etc.
第１図は本発明の一実施例である半導体装置の素子およ
びビン配置を示す底面図、
第２図は本発明を適用できる一例としてのＰＬＣＣ型半
導体装置の正面図、
第３図は本発明の他の実施例である半導体装置の素子お
よびビン配置を示す底面図、
第４図は本発明を適用できる他の例としてのＳＯＰ型半
導体装置の正面図である。
１・・・半導体装置、２・・・パッケージ、Ａ。
Ｂ・・・集積回路。
第 １ 図
第 ３ 図FIG. 1 is a bottom view showing the arrangement of elements and bottles of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a front view of a PLCC type semiconductor device as an example to which the present invention can be applied, and FIG. 3 is a front view of a semiconductor device according to the present invention. FIG. 4 is a bottom view showing the arrangement of elements and bottles of a semiconductor device according to another embodiment. FIG. 4 is a front view of an SOP type semiconductor device as another example to which the present invention can be applied. 1... Semiconductor device, 2... Package, A. B...Integrated circuit. Figure 1 Figure 3
Claims (1)
互いに共通に結合される端子を持つ複数の集積回路が封
止されてなる半導体装置。 ２、各集積回路の入出力が共用されることを特徴とする
特許請求の範囲第１項記載の半導体装置。 ３、各集積回路の入出力が素子毎に互いに分離されてい
ることを特徴とする特許請求の範囲第１項記載の半導体
装置。 ４、上記各集積回路が、アドレス入力端子、データ端子
およびチップ選択端子を持つ記憶回路からなり、上記各
集積回路の少なくとも上記アドレス入出力端子が互いに
共通にされていることを特徴とする特許請求の範囲第１
項記載の半導体装置。 ５、面付実装型のメモリ用半導体装置であることを特徴
とする特許請求の範囲第１項記載の半導体装置。[Claims] 1. A semiconductor device in which a plurality of integrated circuits having the same configuration and having terminals commonly connected to each other are sealed in one package. 2. The semiconductor device according to claim 1, wherein the input and output of each integrated circuit is shared. 3. The semiconductor device according to claim 1, wherein input and output of each integrated circuit are separated from each other for each element. 4. A patent claim characterized in that each of the integrated circuits comprises a memory circuit having an address input terminal, a data terminal, and a chip selection terminal, and at least the address input/output terminals of each of the integrated circuits are common to each other. range 1
1. Semiconductor device described in Section 1. 5. The semiconductor device according to claim 1, which is a surface-mounted memory semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60161938A JPS6223146A (en) | 1985-07-24 | 1985-07-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60161938A JPS6223146A (en) | 1985-07-24 | 1985-07-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6223146A true JPS6223146A (en) | 1987-01-31 |
Family
ID=15744890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60161938A Pending JPS6223146A (en) | 1985-07-24 | 1985-07-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6223146A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998021752A1 (en) * | 1996-11-12 | 1998-05-22 | T.I.F. Co., Ltd. | Memory module |
| WO1998044559A1 (en) * | 1997-04-01 | 1998-10-08 | T.I.F. Co., Ltd. | Memory module |
-
1985
- 1985-07-24 JP JP60161938A patent/JPS6223146A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998021752A1 (en) * | 1996-11-12 | 1998-05-22 | T.I.F. Co., Ltd. | Memory module |
| WO1998044559A1 (en) * | 1997-04-01 | 1998-10-08 | T.I.F. Co., Ltd. | Memory module |
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