JPH03203259A - Semiconductor module - Google Patents

Abstract

PURPOSE:To execute a repair by a method wherein this module is packaged by using a bendable material, terminals are arranged so as to be gathered in one part and a plurality of packages are piled up by changing their angles alternately. CONSTITUTION:A semiconductor module is constituted by using a plurality of packages 10 to 13 each of which is composed of the following: a semiconductor chip 3 which is provided with a bendable substrate and with a plurality of pads 7 arranged on it; outer leads 6 arranged so as to be gathered in one part on the substrate; and inner leads 5 used to connect the pads 7 to the outer leads 6. Consequently, when the packages 10 to 13 to be replaced for a repair are taken out, a part situated at the upper position of each package to be repaired can be lifted because the package is constituted of the bendable substrate. Since the outer leads of each package are arranged so as to be gathered in one part and the packages are piled up in such a way that connecting positions of the outer leads are different, a component can be replaced while the package at the upper position has been attached. Thereby, the repair can be executed easily.

Description

[Detailed description of the invention] Industrial applications The present invention relates to high-density packaging of semiconductors.

BACKGROUND OF THE INVENTION In recent years, semiconductor technology has made remarkable progress, and along with this, technological innovations have been rapid, such as increasing the capacity of these memories and shortening read/write times. In order to make these memories easier to use, modularization in which multiple memories are mounted on a printed circuit board is progressing. personal·
In the field of computers, expansion memory is being standardized under the name of single inline memory module (hereinafter referred to as SIMM). Standardize the dimensions of the P board, the connection method with the connector, the number of pins, etc.
For example, eight megabit dynamic random access memories (hereinafter referred to as DRAMs) are implemented and standardized under the name megabyte SIMM. Or
There is also a movement to standardize the memory card by mounting multiple memories on a printed circuit board about the size of a business card, covering the surrounding area with a case, and making it approximately 3 to 5 mm in diameter. On the other hand, information processing devices such as personal computers are becoming smaller from desktop to laptop types, and at the same time, the number of bits that can be handled by the central processing unit (hereinafter referred to as CPU) installed in these devices has increased from 8 bits to 8 bits. The functionality has been increased to 32 bits, and faster processing and larger memory capacity are being promoted. Therefore, it is strongly desired that the memory module described above be made smaller and have a larger capacity. Furthermore, in this field, in addition to memory modules, multiple semiconductors are mounted to make specific functions easier to use, smaller, and highly functional.

The trend is toward high performance and modularization.

The memory and module will be explained according to FIGS. 4 and 9.

FIG. 4 shows the functions of the memory and module, and FIG. 9 is a circuit diagram of this memory module. In FIG. 9, 1 is a memory, and this memory has 4-bit address input pins AO, AlA2, . As, data input/output pins Do and DI.

D2. D3 and control input pins WE and OE.

It is assumed that it is composed of C8. WE is for write control, OE is for read control, and C8 is for selecting this memory. When C8 and OE are activated and an address is specified using address pin AO-A3, data pin Do-
At D3, the data stored in the memory at the address indicated by AO-A3 can be read. With C8 and WE active, address pins AO to A
3 specifies the address 1/s and inputs the data to be written into the data bins DO to D3, the contents of DO to D3 are written to the address indicated by AO-A3. Therefore, it is assumed that the memory 1 shown in this figure has a capacity of 16x4=64 bits. Using this memory, in FIG. 4, 31 is a memory module a o ”
a s is an address input pin for the memory module, and d○ to A15 are data input/output pins. It has T, M and M as control pins. MA is the write control pin and MA is the read control bin. T is a selection control pin that controls whether to select this memory module. With e and 0 active, a0 to a
If you specify the address with 5, do~d15, a O”
"The data at the address indicated by a5 can be read. Set e and W to the active state and read the data from aO to a5.
When an address is specified and data to be written is input to d O""' d I5, the data is written to the addresses indicated by aO to a5. Therefore, this memory module has a capacity of 64×16=1024 bits. Note that Vcc+Vss indicates a power supply pin. In FIG. 5, VCC and VSS also indicate power supply pins. FIG. 9 shows a method for realizing the memory module of FIG. 4 using the already explained 64-bit memory. In FIG. 9, there are 16 memories 1,
On the other hand, ao to a3 and W and 0 are connected to AO to A3 and WE and OE of the 16 memories 1.

dO to d3 are connected to Do to D4 of the four memories 1. d4-d7. The same applies to ds~dlllld12~(1+5. a, ~a5 and e are the decoders 18
connected to. This decoder outputs four selection signals, which are respectively connected vertically to four memories 1, as shown in FIG. Only when e is active, only the main one of the four selection signals output from the decoder becomes active. Which of the four is activated is determined by the inputs of A4 and A5. With such a connection, a memory module 31 can be realized from 16 memories 1.

Note that the memory 1 and the memory module 31 have their respective capacities and signal bins determined for the sake of explanation. There are various capacities of actual memory, and the capacities are much larger than the capacity of the memory 1 described above. The same applies to memory modules.

Problems to be Solved by the Invention The problems of the conventional technology will be explained with reference to FIGS. 4 and 9. Conventionally, 16 memories 1 were mounted in one stage on one or both sides of a printed circuit board.

Therefore, the implementation is planar, and the physical size of the memory 1 limits the physical size of the memory module 17. In other words, when 16 memories 1 are mounted on one side of a printed circuit board, even if you try to make the memory module 31 smaller, the area of the memory module will be the area of the package of memory 1 multiplied by the number 16. It was put away. When the memory 1 is mounted on both the front and back surfaces of a printed circuit board, the area of the memory module is half of the above value.

Therefore, even if a smaller, larger capacity memory module was desired, it could not be realized. Generally, memory is
It is placed in a package called a small outline jebend (hereinafter referred to as SOJ) or a plastic leadless chip carrier (hereinafter referred to as PLCC), and has a larger volume than a silicon chip.

Therefore, also from this point of view, it has not been possible to realize a small-sized, large-capacity memory module.

As a solution to this problem, mounting the memory three-dimensionally (three-dimensionally) has been considered for some time, but this has not been realized due to problems with repair methods. That is, if the memory arranged at the bottom row is defective, it is difficult to repair because the memory is stacked on top of each other, and in order to remove this memory, all the memories above must be removed.

The present invention provides a means for stacking memories together using a new package to realize a smaller and larger capacity memory module, and also to solve the above-mentioned problems.

Means for Solving the Problems The present invention provides a semiconductor chip having a bendable substrate and a plurality of pads arranged on the substrate, outer leads arranged in a group on a part of the substrate, the pads and the outer leads. A semiconductor module is constructed using a plurality of packages each having an inner lead for connection with the semiconductor module.

With the structure described above, when taking out the package to be replaced for repair, the package is constructed with a bendable board, so the parts above the package to be repaired can be lifted up, and the outer leads of the package can be lifted up. The parts are arranged in one area, and the outer leads are stacked in different connection positions, so parts can be replaced while the upper package is still attached. Another repair method is to disconnect only the wiring of the package to be repaired and add a new package on top.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 8. FIG. 1 shows an example of the packaging method of the present invention, and FIG.

Figure 3 shows how to mount this package on a printed circuit board, etc. Figures 4 and 5 explain the functions of the memory module and the wiring method, and Figures 6 to 8 This explains the repair method. In addition, in this embodiment, a case of four-stage stacking will be explained.

First, referring to FIG. 1, an example of a package used as a component of a semiconductor module according to an embodiment of the present invention will be described. Figure 1 (al is an electrical block diagram of the memory 1, which has the same functions as a general memory. Figure 1 (bl is a plan view of the packaged memory 1, FIG. 1(C) is a sectional view thereof.

6 is an outer 0 lead which is a terminal for connecting to a board such as a printed circuit board. Each outer lead is assigned a signal name shown in FIG. 1(a). 3 is a memory chip, 7
are a plurality of pads provided on the chip 3, through which signals are exchanged and data are read and written to the memory elements inside the chip 3. Power is also supplied via this pad 7. These pads 7 are connected to the inner leads 5 via the bumps 4. The inner lead 5 is a conductor made of a bendable material and formed on the film 2 made of an insulator. These inner leads 5 are shown by dotted lines in FIG. 1(b). These are connected to the outer lead 6. inner lead 5
The outer leads 6 and 6 are made of the same material, but the outer leads 6 are for connection to a printed circuit board, and the inner leads 5 are for connection to pads 7 provided on the silicon chip 3. , the plating process, etc. is different in order to make the connection easier. The inner lead 5 and the pad 7 are connected by means such as thermocompression bonding using bumps made of gold or the like. These have a coating 8 applied around them for protection. In this way, signal terminals, power supply terminals, etc. can be arranged in one direction, and the package can be folded. In addition, among the contents explained here, details regarding the method of connecting the pad 7 and the inner lead 5, or the method of forming the inner lead 5 and the outer lead 6 on the film 2, etc. It is described on pages 27-49 of the proceedings of ``Key Technologies for Implementation'' (Industrial Research Association).

A method of stacking the packages described in FIG. 1 will be explained according to FIGS. 2 and 3.

FIG. 2 is a cross-sectional view of the case where they are stacked one on top of the other, and FIG. 3 is a view of this as seen from above. 10,11°12.18 is
These are packages made by the method shown in FIG. 1, and each has built-in memory A, memory B, memory C, and memory D. Package 13 is placed on the bottom of substrate 9, package 12 is placed on top of package 13, package 11 is placed on top of package 12, and package 10 is placed on top of package 11. As shown in FIG. 3, these are rotated 90 degrees and stacked on top of each other, and the outer leads 14. of the memory A are stacked together. Memory B outer lead 15. Memory C outer lead 16. The outer leads 17 of the memory D are oriented as shown in the figure.

Therefore, the outer leads of the four packages are arranged in four directions, thereby connecting the outer leads of each memory to the lands 30 formed on the substrate 9 as shown in FIG.
can be connected with. The lands 30 are made of a conductor and are formed on the substrate 9 which is an insulator. These lands 30 are wired according to the circuit shown in FIG.
In the figure, the memories in the blocks enclosed by dotted lines are stacked. That is, in FIG. 5, 10a is memory A stacked on top, 11a is memory B placed below it, 12a is memory C placed further below it, and 13a is: Memory D is located at the bottom. Similarly, 10b to 13b are 10b and ll from the top.
b, 12b, and 13b are stacked in this order. 10c~1
The same applies to 3c and 10d to 13d.

By doing so, the memory module 31 shown in FIG. 4 can be manufactured, and the total area of the memory module 31 can be significantly reduced. In other words, since they are stacked in four layers, the area of the memory module can be reduced to 1/4 if the size is the same as that of a conventional package.

There is also the method shown in Figure 9 for dividing blocks into stacks. The block division in Figure 5 divides the data lines connected to each memory into blocks, and in Figure 9, the blocks connect the same C8 signal to each memory. This is what I did. Therefore, in the case of Figure 9, the four stacked memories are driven at the same time, but in the case of Figure 5, only one of the four stacked memories is driven. do. Therefore, regarding the generation of heat, in the case of Figure 9, the stacked 4
In contrast, in the case of Fig. 5,
Since only one of the four generates heat, the method shown in FIG. 5 is more advantageous in terms of heat, and this method can solve the heat problem. Heat from the chip is generally dissipated through two paths. one,
From the surface of the chip silicon to the outside through the package,
The other method is to radiate heat through the wiring pattern on the printed circuit board via the terminals of the wiring board and the package. Therefore, if you choose a material with good thermal conductivity for the coating 8, divide it into blocks as shown in Figure 5, and wire it so that only one of the stacked memories is driven, The heat radiation problem can be solved by adding the heat radiation effect through the wiring pattern.

Furthermore, in FIG. 5, the group of memories that generate heat at the same time is (10a, 13b, 12c, 1id).

(lla, 10b, 13c, 12d), (12a.

11b, 10c, 13d), (13a, 12b.

11c, 10d), either the topmost memory (that is, the memory that mainly dissipates heat from the surface of the package) generates heat simultaneously, or the bottom memory (memory that dissipates heat mainly through the printed circuit board) generates heat simultaneously. The top memory, second memory, third memory, and bottom memory each generate heat one at a time, so heat is dissipated from the surface of the package and through the printed circuit board. In combination, heat can be dissipated more efficiently.

Furthermore, a repair method will be explained according to FIGS. 6 to 8. In the case of the present invention, since the package itself is made of a bendable film-like material, it is possible to fix the connection points between the substrate and the outer leads and lift up the stacked memories. This results in
The lower memory can be removed. First, disconnect the outer leads of the defective memory from the board, then lift the defective memory slightly, and then lift the memory placed on top of the defective memory slightly to create a gap above and below, and remove the defective memory. By pulling horizontally, you can easily remove the defective memory. Leave the gap as it is, and then insert a good memory into the gap and connect the outer leads to the board. After all four memories were confirmed to be good, the sixth
Apply the external coating shown in Figure 19. FIG. 7 is a top view of the coated state. As shown, an outer coating 19 is provided, thereby completely fixing it to the substrate. This method makes it possible to perform repairs that have been a problem in the past. After the memory chips are placed in a package as shown in Figure 1, a memory test is carried out, and then only non-defective chips are assembled into four 3D stacks to form a memory module, as shown in Figure 2. .

After that, a burn-in test will be conducted. A burn-in test is a test in which a temperature higher or lower than the operating temperature or a voltage higher than the operating voltage is applied to the memory module to extract parts that are beginning to fail, and is generally performed to improve quality. Therefore, installation defects caused during stacking and defects caused by burn-in tests can be completely repaired using this method.

FIG. 8 shows another repair method. This figure shows a case where the second memory from the bottom is defective. Since the terminals of each memory are arranged independently on the board in each of the four directions, and packaging using the method shown in Figure 1 can be made thinner than conventional packaging, the repair method shown in Figure 8 is possible. become. Disconnect the outer leads of the defective memory from the board, cut off the unnecessary part of the film, leave the defective memory as it is, and stack an extra one on top of the top memory.
This outer lead is connected to the board. In this method, the height and weight of the memory module will be slightly larger, but 6. Compared to FIG. 7, it is possible to repair defects that occur at the time of shipment from the factory. Even after applying the external coating 19 and fixing the memory to the board, by stacking it on top of it, the 4
There is no need to remove all the stacked memories.

The case where four packages are stacked together has been described above, but the case where eight packages using the present invention are stacked together will be explained according to FIGS. ) shows the shape of the package, (al shows a plan view of 8 of these stacked together. 3 is a chip, 6 is an outer lead, the shape of the film 21 is as shown in the figure, and on this Form inner leads as shown in Figure 1.In this way, the chips are packaged and stacked.2.
2 is the top package A, 23 is the package B below it, 24 is the package C below 23,
25 is package D below 24, 26 is package E below 25, 27 is package F below 26, 28
is the package G below 27, and 29 is the package H below 28. By doing this, eight packages can be stacked and the board and each outer lead can be connected. Therefore, according to the present invention, eight or more can be used.

Although the memory module has been described above, the same effect can be obtained with a similar configuration for modules other than memory.

Effects of the invention (1) Three-dimensional arrangement is possible by packaging with a bendable material, arranging the terminals in one area, and stacking multiple packages at different angles, making the module more compact. becomes possible.

(2) By mounting the chip on a thin film, the package itself can be made thinner, and even when stacked, the height can be lowered, increasing the capacity of the module,
It becomes possible to make it thinner.

(3) For packaging made of bendable materials,
It is possible to lift stacked packages with the board and outer leads fixed, which makes repair possible.

(4) Because the packaging itself is thin, and
Since the connection between the outer lead and the land provided on the board can be disconnected, it is also possible to stack packages on top of each other for repair.

(5) The problem of heat dissipation can be solved by wiring the stacked packages so that they do not operate at the same time.

[Brief explanation of drawings]

FIG. 1(a) is a wiring diagram of terminals of a package used in a semiconductor module according to an embodiment of the present invention.
is a plan view of the same package, FIG. 1(C) is a sectional view of the same package, FIG. 2 is a sectional view of the semiconductor module of the above embodiment, FIG. 3 is a plan view of the same, and FIG. 4 is a general memory. A wiring diagram of the module, FIG. 5 is an internal circuit diagram of the memory module of the above embodiment, FIG. 6 is a sectional view of another embodiment of the memory module with a coating layer covering the outer surface, and FIG. 8 is a sectional view of the memory module shown in FIG. 6 after repair, FIG. 9 is an internal circuit diagram of a general memory module, and FIG. 10 is a plan view of a semiconductor module according to another embodiment. It is a diagram. 1...Memory, 2...Film, 3.
...chip, 4...bump, 5...
...Inner lead, 6...Outer lead,
7...Pad, 10,11°12.13...
...Package, 14.15.16゜17...
・Outer lead, 21...film.

Claims (3)

[Claims] (1) A package consisting of a semiconductor chip having a plurality of pads, outer leads arranged in one part, inner leads connecting the pads and the outer leads, and a bendable substrate on which the chip is arranged. A semiconductor module comprising a plurality of semiconductor modules stacked one on top of the other with the outer leads of the respective packages oriented in different directions. (2) A bendable first substrate on which the chip is placed, including a semiconductor chip having a plurality of pads, outer leads arranged in one part, and inner leads connecting the pads and the outer leads. A semiconductor module in which a plurality of packages are divided into groups such that the number of packages that generate heat at the same time in each group is l or less, and each group is stacked and arranged on a second substrate. Note that l is the maximum number of packages that generate heat at the same time, and m
When the number of groups is n, it is a natural number that satisfies l≧m/n>l−1. (3) The semiconductor module according to claim 1 or 2, further comprising a coding layer that covers the outer surface of the laminate in which each package is stacked and wired.