JPS622308A - Dc constant-voltage power source - Google Patents

Dc constant-voltage power source

Info

Publication number
JPS622308A
JPS622308A JP14108785A JP14108785A JPS622308A JP S622308 A JPS622308 A JP S622308A JP 14108785 A JP14108785 A JP 14108785A JP 14108785 A JP14108785 A JP 14108785A JP S622308 A JPS622308 A JP S622308A
Authority
JP
Japan
Prior art keywords
voltage
output voltage
decreases
output
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14108785A
Other languages
Japanese (ja)
Inventor
Takeshi Kawahara
川原 竹志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP14108785A priority Critical patent/JPS622308A/en
Publication of JPS622308A publication Critical patent/JPS622308A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To execute a stable operation even if any input smoothing circuit is used, by using a voltage controlled type transistor, and setting a current required for applying a bias voltage to said transistor, so as to be smaller than an idling current of an error amplifying means. CONSTITUTION:When an output voltage between output terminals 13, 14 rises, a part of an output voltage which has been detected by output voltage detecting resistances 5, 6 is compared with a voltage of a Zener diode 7 for reference voltage, and in accordance with its difference, a bias voltage applied between the base and the emitter of a driving transistor 10 decreases. As a result, a collector current I2 decreases and a voltage across a resistance 21 decreases, therefore, a bias volage impressed between the gate and the source of an FET 20 decreases and the impedance between the drain and the source becomes high, a voltage drop increases and an output power drops by its portion, and it is stabilized to a set output voltage. On the contrary, when the output voltage has dropped, the impedance between the drain and the source of the FET 20 becomes low, the voltage drop decreases and the output voltage increases by its portion, and it is stabilized to the set output voltage.

Description

【発明の詳細な説明】 技術分野 本発明は直流定電圧電源に関し、特に低損失直流定電圧
電源に関する。
DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a DC constant voltage power supply, and more particularly to a low loss DC constant voltage power supply.

従来技術 従来の低損失直流安定化電源は第3図の如き構成となっ
ている。図において、1は低損失直流安定化電源に一力
を供給する一次電源、2は入力平滑回路、3は直列制御
トランジスタ、4は出力平滑回路、5,6は出力電圧検
出用抵抗、7は基準電圧用ツェナーダイオード、8は基
準電圧用ツエナータ゛イオード7に流れる電流を制限す
る抵抗、9は出力′α圧検出用抵抗5及び6によって得
られた出力電圧の一部と基準電圧用ツェナーダイオード
7の電圧とを比較してその差を増幅する誤差増幅器、l
Oは直列制御トランジスタ3のベースに電流を供給する
駆動トランジスタ、llは駆動トランジスタ100ベー
ス鑞流を制限する抵抗、12は直列制御トランジスタ3
のペース電流を制限する抵抗、13 、14は出力端子
である。
Prior Art A conventional low-loss DC stabilized power supply has a configuration as shown in FIG. In the figure, 1 is a primary power supply that supplies one power to a low-loss stabilized DC power supply, 2 is an input smoothing circuit, 3 is a series control transistor, 4 is an output smoothing circuit, 5 and 6 are resistors for output voltage detection, and 7 is a A reference voltage Zener diode; 8 is a resistor that limits the current flowing to the reference voltage Zener diode 7; 9 is a part of the output voltage obtained by the output 'α pressure detection resistors 5 and 6 and the reference voltage Zener diode 7; An error amplifier, l, which compares the voltage of
0 is a drive transistor that supplies current to the base of the series control transistor 3; 11 is a resistor that limits the flow of current to the base of the drive transistor 100; 12 is a series control transistor 3;
Resistors 13 and 14 are output terminals for limiting the pace current.

以下にその勧降を説明する。出力端子13 、14間の
出力電圧が上昇すると、出力電圧検出用抵抗5及び6に
よって分割された出力電圧と基準電圧用ツェナーダイオ
ード7の電圧との差電圧が増幅され翫駆動トランジスタ
lOのノ(イアスミ圧が減少して駆動トランジスタ10
のコレクタ電流即ち直列制御トランジスタ3のペース電
流工1が減少する。
The solicitation will be explained below. When the output voltage between the output terminals 13 and 14 increases, the voltage difference between the output voltage divided by the output voltage detection resistors 5 and 6 and the voltage of the reference voltage Zener diode 7 is amplified, and The drive transistor 10 decreases due to the decrease in Iasumi pressure.
, that is, the pace current 1 of the series control transistor 3 decreases.

その結果直列制御トランジスタ3のコレクタ・エミッタ
間のインピーダンスが高くなることにより電圧降下が増
加し、その変動゛電圧分だけ出力電圧が低下して、設定
された出力′電圧に安定化される。
As a result, the impedance between the collector and emitter of the series control transistor 3 increases, increasing the voltage drop, and the output voltage decreases by the amount of the fluctuation, and is stabilized at the set output voltage.

逆に出力電圧が低下すると、直列制御トランジスタ3の
インピーダンスが低くな#)電圧降下も減少し、その変
動邂圧分だけ出力電圧が増加して設定された出力電圧に
安定化される。
Conversely, when the output voltage decreases, the impedance of the series control transistor 3 is low and the voltage drop also decreases, and the output voltage increases by the amount of the fluctuation voltage and is stabilized at the set output voltage.

次に1次電源の磁圧1を減少させたとき、設定された出
力電圧を維持する最少の1次電源1の電圧V I Nr
n I nは次式で表わすことができる。
Next, when the magnetic pressure 1 of the primary power source is decreased, the minimum voltage of the primary power source 1 that maintains the set output voltage V I Nr
n I n can be expressed by the following formula.

VINmtn=Vo+Vcg(mat)   ………(
1)ここで、voは出力端子13及び14間の出力′電
圧、V CE (m a t )は直列制御トランジス
タ3の飽和状態におけるコレクタ・エミッタ間の電圧を
示している。
VINmtn=Vo+Vcg(mat) ......(
1) Here, vo represents the output voltage between the output terminals 13 and 14, and V CE (m a t ) represents the voltage between the collector and emitter of the series control transistor 3 in the saturated state.

通常、Vary(sat)カ0.5 V@flF)直列
WIJel トラ7ジスタは容易に入手できるので、(
1)式の如く1次電源1の電圧を減少させても設定され
た出力電圧よシ0.5 V程度高くするだけで設定され
た出力電圧に制御することができ、直列制御トランジス
タ3にて消費される電力損失も減らすことができる。
Normally, Vary (sat) 0.5 V@flF) series WIJel 7 transistors are easily available, so (
1) Even if the voltage of the primary power supply 1 is decreased as shown in the formula, the set output voltage can be controlled by only increasing the set output voltage by about 0.5 V, and the series control transistor 3 Power loss can also be reduced.

しかしながら、1次電源1の電圧を第4図の如く増加さ
せていくとき、出力電圧が設定された出力電圧に達する
直前の入力電流IINIは、直列制御トランジスタ3及
び駆動トランジスタ10はいずれも飽和状態になってい
るため、下記の式で表わすことができる。
However, when the voltage of the primary power supply 1 is increased as shown in FIG. Therefore, it can be expressed by the following formula.

x、、、 do+(VIN−VBE −VCg(@at
))/1141. +KVIN・・・・・・・・・・・
・0) ここで、Ioは出力電流、VINは1次電源1の電圧、
VBEは直列制御トランジスタ30ベース・エミッタ間
の電圧、Ruは制御抵抗12の抵抗値、KVINは入力
端子に依存する誤差増幅器9のアイドリンク電流を示し
ている。
x,,, do+(VIN-VBE-VCg(@at
))/1141. +KVIN・・・・・・・・・・・・
・0) Here, Io is the output current, VIN is the voltage of the primary power supply 1,
VBE indicates the voltage between the base and emitter of the series control transistor 30, Ru indicates the resistance value of the control resistor 12, and KVIN indicates the idle link current of the error amplifier 9 depending on the input terminal.

次に、出力(社)圧が設定された出力電圧に達した後の
入力底流IINmは次式で表わすことができる。
Next, the input undercurrent IINm after the output pressure reaches the set output voltage can be expressed by the following equation.

I IN、 = Io + IO/hrg3) + K
VXH・・・−・−・−(3)ここでhpg(3)は直
列制御トランジスタ0)の電流増幅率でるる。また、V
cg(sat)時の直流増幅率hpE(5at)  と
hrz(3)の間には一役的に次式が成立する。
I IN, = Io + IO/hrg3) + K
VXH...----(3) Here, hpg(3) is the current amplification factor of the series control transistor 0). Also, V
The following equation holds true between the DC amplification factor hpE(5at) at cg(sat) and hrz(3).

hFE(,5at)(hrp(3)        −
−・−−−−−、、、、(4)(2)弐において(VT
:r −VBE−VcE(sat))/i、 fd、 
3の直列制御トランジスタの飽和状態に訃けるベースペ
ース電流(工りを表わしてンリ、I TN、とIINI
 の間には次式が1戊立する。
hFE(,5at)(hrp(3) −
-・------,,,, (4) (2) In the second (VT
:r −VBE−VcE(sat))/i, fd,
The base space currents of the three series controlled transistors reach saturation (indicated by NRI, ITN, and IINI).
The following equation stands between .

II殉〉■IN2       ’°”甲゛°°°°゛
°°(5)以上説明したごとく1,1次電源1の電圧が
MINmln付近で入力平滑回路2側よシ直列制御トラ
ンジスタ3側を見たインピーダンスが角性抵抗を示す領
域があ夛、入力平滑回路2のインピーダンスによって、
第3図の従来の直流定電圧を源が発振して、正常な鳴能
を保てなくなるという欠点があった。
II Marty〉■IN2 '°"K゛°°°°゛°° (5) As explained above, when the voltage of the primary power supply 1 is around MINmln, the input smoothing circuit 2 side looks at the side of the series control transistor 3 side. There are many regions where the impedance shows square resistance, and depending on the impedance of the input smoothing circuit 2,
The conventional constant DC voltage source shown in FIG. 3 has a drawback in that the source oscillates, making it impossible to maintain normal sound performance.

本発明は入力平滑回路のインピーダンスにか\わらず安
定な動作が可能な直流定電圧鑞源を提供することである
SUMMARY OF THE INVENTION The present invention provides a DC constant voltage power source that can operate stably regardless of the impedance of the input smoothing circuit.

発明の構成 本発明による直流定電圧電源は、入力電圧と出力電圧と
の差電圧を分担すべく入出力間に直列に挿入された直列
制御素子と、当該出力電圧と基準電圧との誤差を検出し
てこの誤差に応じた制御信号を発生する誤差増幅手段と
を有し、この制御信号により直列制御素子の導通状態を
制御するようKした直流定電圧′4源であって、その特
徴とするところは、直列制御素子として電圧制御型トラ
ンジスタを用い、このトランジスタへバイアス電圧を与
えるために必要な電流を誤差増幅手段のアイドリング電
流よりも小に設定してなることにある。
Structure of the Invention The DC constant voltage power supply according to the present invention includes a series control element inserted in series between input and output to share the voltage difference between the input voltage and the output voltage, and detects an error between the output voltage and a reference voltage. and an error amplifying means for generating a control signal according to this error, and the DC constant voltage source is characterized in that the conduction state of the series control element is controlled by this control signal. The problem is that a voltage controlled transistor is used as the series control element, and the current required to apply a bias voltage to this transistor is set to be smaller than the idling current of the error amplification means.

実施例 以下、図面を用いて本発明の詳細な説明する。Example Hereinafter, the present invention will be explained in detail using the drawings.

第1図は本発明の実施例の回路図であシ、20は電圧側
脚型のトランジスタ(FETと略す)、21はFET2
0にバイアス電圧を与えるための抵抗、nはF E T
 20のゲート・ソース間に印加されるバイアス電圧を
制限しかつゲート・ソース間の耐圧以下におさえるたi
hのツェナーダイオードである。
FIG. 1 is a circuit diagram of an embodiment of the present invention, in which 20 is a voltage side leg type transistor (abbreviated as FET), and 21 is an FET2.
Resistance for applying bias voltage to 0, n is FET
In order to limit the bias voltage applied between the gate and source of 20 and keep it below the withstand voltage between the gate and source.
h Zener diode.

他の構成は43図の列と同等であり、その説明は省略す
る。
The other configurations are the same as those shown in FIG. 43, and their explanation will be omitted.

以下に動作を説明する。出力端+EIn3及び14間の
出力電圧が上昇すると、出力電圧検出用抵抗5゜6で侵
出された出力電圧の一部と基準′a圧用ツェナーダイオ
ード7の′ば圧とが比較され、その差に応じて駆動トラ
ンジスタ10のペース・エミッタ間に印加されるバイア
ス電圧が減少する。その結果、駆動トランジスタ10の
コレクタ電流工2が減少して抵抗21の両端に発生する
底圧が減少するため、F E T 20のゲート・ソー
スに印加されるバイアス電圧が減少してF E T 2
0のドレイン・ノース間のインピーダンスが高くなシ、
電圧降下が増加してその電圧変動分だけ出カキ圧が低下
し、設定された出力電圧に安定化される。
The operation will be explained below. When the output voltage between the output terminals +EIn3 and 14 rises, a part of the output voltage leaked out by the output voltage detection resistor 5゜6 is compared with the voltage of the Zener diode 7 for the reference voltage a, and the difference is detected. Accordingly, the bias voltage applied between the pace emitter of the drive transistor 10 decreases. As a result, the collector current 2 of the drive transistor 10 decreases and the bottom pressure generated across the resistor 21 decreases, so the bias voltage applied to the gate and source of the FET 20 decreases and the FET 2
The impedance between the drain and north of 0 is high,
As the voltage drop increases, the output pressure decreases by the amount of voltage variation, and is stabilized at the set output voltage.

逆に、出、力電圧が低下した場合、FET20のバイア
ス電圧が増加17てドレイン・ソース間のインピーダン
スが低くなり、電圧降下が減少1.てその電圧変動分だ
け出力電圧が増加し、設定された出力電圧に安定化され
るのである、 次に1次電源1を、−窩2図に示す如く増加させていく
とき、入力電流IIに3は下記の式で示すことができる
Conversely, when the output voltage decreases, the bias voltage of the FET 20 increases17, the impedance between the drain and the source decreases, and the voltage drop decreases1. The output voltage increases by the amount of the voltage fluctuation, and is stabilized at the set output voltage.Next, when the primary power supply 1 is increased as shown in Figure 2, the input current II 3 can be expressed by the following formula.

I IN3 =I o+へ十KvxN   ・・・・・
・・・・・・・・・・(6)ここで、■、けF E T
 20を、駆動するために必要な電流である。また、工
1は1次電源1の電圧の増加に従って減少12、K′v
INは逆に増加する。従って、1次電源1の少くともV
T:!:r+In近傍の電圧値における工、とKVIN
の関係を下式の如く設定する。
I IN3 = 10 KvxN to I o+...
・・・・・・・・・・・・(6) Here, ■, KE F E T
This is the current required to drive 20. Also, as the voltage of primary power source 1 increases, K'v decreases by 12, K'v
On the contrary, IN increases. Therefore, at least V of the primary power supply 1
T:! : at a voltage value near r+In, and KVIN
Set the relationship as shown below.

I、 (KVrw        ・・・・・・・・・
・・・(7)こうすることによって、(6)式において
IrN5は1次電源1の電圧の増加に従って単調に増加
することになる。この(7)式の設定は増幅器9の内部
回路定数や抵抗21の値等により可能である。1次電源
電圧の変化に対する入出力電流の様子が第2図に示され
ており、図から判るようにVrNml!1 付近で負性
抵抗領域金呈することがなくなるものである。
I, (KVrw ・・・・・・・・・
(7) By doing this, IrN5 monotonically increases as the voltage of the primary power supply 1 increases in equation (6). This equation (7) can be set by adjusting the internal circuit constants of the amplifier 9, the value of the resistor 21, etc. Figure 2 shows how the input/output current changes with respect to changes in the primary power supply voltage, and as can be seen from the figure, VrNml! This means that the negative resistance region does not appear near 1.

発明の詳細 な説明したように、本発明によれば、1次′α源10−
圧の増減に対して入力電流が単調な変化で増減するため
、どのような入力平滑回路を接続しても安定に動を賞す
る。よって、入力平滑回路のインピーダンス値を考慮す
ることなく回路動作のみを考慮して設計すれば良いとい
う効果がある。
DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the primary α source 10-
Since the input current increases and decreases in a monotonous manner as the voltage increases and decreases, stable operation is achieved no matter what type of input smoothing circuit is connected. Therefore, it is possible to design the input smoothing circuit by considering only the circuit operation without considering the impedance value of the input smoothing circuit.

又、設電された出力電圧に安定化される1次電源の′電
圧が、使用する直列制御用の素子の物性を考慮丁れば、
非′gに低くなるという効果がある。
In addition, if the voltage of the primary power supply stabilized to the installed output voltage takes into account the physical properties of the series control elements used,
It has the effect of being extremely low.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例の回路図、第2図は第1図の回
路特性を示す図、第3図riK来の直流定電圧電源の回
路例を示す図、稟41は第3図の回路の特性を示す図で
ある。 王女部分の符号の説明 1−1次′lll1c源 7・・・基準電圧用ツェナーダイオード9・・・誤差増
幅器    20・・・FET第1図 1法電う原の電圧
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a diagram showing the circuit characteristics of Fig. 1, Fig. 3 is a diagram showing a circuit example of a DC constant voltage power supply since RIK, FIG. 2 is a diagram showing the characteristics of the circuit. Explanation of the symbols of the princess part 1-1st order 'llll1c source 7... Zener diode for reference voltage 9... Error amplifier 20... FET Fig. 1 Voltage of source voltage

Claims (1)

【特許請求の範囲】[Claims] 入力電圧と出力電圧との差電圧を分担すべく入出力間に
直列に挿入された直列制御素子と、前記出力電圧と基準
電圧との誤差を検出してこの誤差に応じた制御信号を発
生する誤差増幅手段とを有し、この制御信号により前記
直列制御素子の導通状態を制御するようにした直流定電
圧電源であって、前記直列制御素子として電圧制御型ト
ランジスタを用い、このトランジスタへバイアス電圧を
与えるために必要な電流を前記誤差増幅手段のアイドリ
ング電流よりも小に設定してなることを特徴とする直流
定電圧電源。
A series control element is inserted in series between input and output to share the difference voltage between the input voltage and the output voltage, and detects an error between the output voltage and a reference voltage and generates a control signal according to this error. The DC constant voltage power supply has an error amplification means, and controls the conduction state of the series control element using the control signal, wherein a voltage control transistor is used as the series control element, and a bias voltage is applied to the transistor. A DC constant voltage power supply characterized in that the current required to provide the error amplification means is set to be smaller than the idling current of the error amplification means.
JP14108785A 1985-06-27 1985-06-27 Dc constant-voltage power source Pending JPS622308A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14108785A JPS622308A (en) 1985-06-27 1985-06-27 Dc constant-voltage power source

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14108785A JPS622308A (en) 1985-06-27 1985-06-27 Dc constant-voltage power source

Publications (1)

Publication Number Publication Date
JPS622308A true JPS622308A (en) 1987-01-08

Family

ID=15283899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14108785A Pending JPS622308A (en) 1985-06-27 1985-06-27 Dc constant-voltage power source

Country Status (1)

Country Link
JP (1) JPS622308A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03226227A (en) * 1990-01-31 1991-10-07 Nagano Japan Radio Co Power source protecting circuit
CN104122919A (en) * 2013-04-27 2014-10-29 海洋王(东莞)照明科技有限公司 Direct-current voltage stabilizing circuit
CN106796437A (en) * 2014-09-16 2017-05-31 日立汽车系统株式会社 Sensor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03226227A (en) * 1990-01-31 1991-10-07 Nagano Japan Radio Co Power source protecting circuit
CN104122919A (en) * 2013-04-27 2014-10-29 海洋王(东莞)照明科技有限公司 Direct-current voltage stabilizing circuit
CN106796437A (en) * 2014-09-16 2017-05-31 日立汽车系统株式会社 Sensor device
CN106796437B (en) * 2014-09-16 2018-09-11 日立汽车系统株式会社 Sensor device
US10444031B2 (en) 2014-09-16 2019-10-15 Hitachi Automotive Systems, Ltd. Sensor device

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