JPS622266B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a field effect transistor type chemically sensitive element.

A chemically selective membrane containing an ion exchange substance, an enzyme, etc. is formed on the gate of an insulated gate field effect transistor, and is used to detect the ionic activity in the electrolyte and the presence of specific substances on which the enzyme acts. Such chemically sensitive elements have been known for a long time. For example, JP-A-52-26292, 53-25385,
Publication No. 53-139289 contains descriptions regarding these matters.
When these chemically sensitive elements are actually used, they are often immersed in a solution to be measured. Therefore, sufficient care must be taken to ensure that the entire element, at least the portion immersed in the solution to be measured, is not undesirably affected by the solution to be measured. However, none of the conventional proposals could be said to be sufficient in this respect. FIG. 1 is a sectional view diagrammatically showing the structure of a field effect transistor type chemically sensitive element described in Japanese Patent Application Laid-Open No. 139289/1989. A source diffusion surface region 2 and a drain diffusion surface region 3 are formed at a distance from each other on the surface of a p-type silicon semiconductor substrate 1, and this substrate surface is covered with an insulating layer 4 of silicon dioxide (SiO ₂ ). Conductors 5 and 6 are connected to the source region 2 and drain region 3 through holes made in the insulating layer 4 to serve as source and drain lead wires, respectively. These conductors 5, 6 are further coated with an insulating layer 7, and a chemoselective film 9 is deposited on the part of the insulating layer 7 that is above the channel region 8; The portion other than the membrane 9 is covered with a solution-impermeable membrane 10. When using a sensing element with such a structure, the chemically selective membrane 9 is brought into contact with the sample liquid;
At this time, the SiO ₂ layer 4 is hydrated through this membrane, and certain cations, such as H ⁺ and Na ⁺ , enter this layer 4, causing gate leakage, which is critical to the stability and reproducibility of measurements. cause trouble. Further, the solution-impermeable membrane 10 is described as being made of epoxy resin, but in this case, the epoxy resin swells over time, which again has an adverse effect on the stability of the device. Figure 2 shows the structure of a field effect transistor type chemically sensitive element described in JP-A No. 52-26292. Figure 2a is a plan view and b is a cross-sectional view. , for example, on the surface of the p-type silicon semiconductor substrate 11, spaced apart from each other.
shaped surface regions 12 and 13 are formed, for example by diffusion, with these surface regions serving as a source and a drain, respectively, with a channel region 1 between them.
4 was formed. A SiO ₂ layer 15 is formed on the surface of the semiconductor substrate 11 as an insulating layer, and this SiO ₂
Conductors 16 and 17 are deposited over layer 15 and are electrically connected through holes drilled in SiO ₂ layer 15 to source and drain surface regions 12 and 13, respectively. above channel 14
A silicon nitride (Si ₃ N ₄ ) layer 18 and an ion sensitive layer 19 are further deposited in sequence on the SiO ₂ layer 15 to form a gate portion. An insulating resin layer 20 is applied to the outer surface other than the sensitive portion. In this example
Since the Si ₃ N ₄ layer 18 is formed on the SiO ₂ layer gate film 15, stability is maintained in this part, but the insulating resin layer 20 covering the surface other than the sensitive part is It is difficult to form the insulating resin layer 20 thinly without it, and furthermore, since the insulating resin layer 20 gradually swells in the sample liquid, there are problems with stability and durability.
FIGS. 3a and 3b are cross-sectional views in two directions of a chemical sensing element described in Japanese Patent Application Laid-Open No. 53-25385.
The ion-sensing portion is provided at the tapered tip, and forms a U-shaped source region 22 and a drain region 23 surrounded by the U-shaped source region 22 on the silicon substrate 21. The fact that a SiO ₂ layer, a Si ₃ N ₄ layer, and an ion-sensitive layer are sequentially formed thereon is substantially the same as the example shown in FIG. 2, so they are omitted from the drawing. Further, contact portions 24 and 25 connected to the source region 22 and drain region 23 are formed in the thicker portion of the element, and lead wires are connected to these contact portions 24 and 25. contact part 24,
Reference numeral 25 consists of n ⁺ diffusion regions 26, 27 diffused into the drain region 23 and source region 22, and aluminum electrodes 28, 29 deposited thereon.
Furthermore, in areas other than the ion sensitive part, the drain region 23,
A p ⁺ diffusion channel stopper region 30 is formed between the source regions 22 so as not to form a channel region. In this example, the above-described structure is previously formed on the silicon substrate 21 and then cut into thin pieces by etching to form the shape shown in FIG. Therefore, in the cut cross section, the silicon substrate 21 is exposed, and the back surface of the silicon substrate is also exposed. However, when using this element, it is necessary to immerse at least the ion-sensing part, that is, the tapered tip shown in FIG. 3, into the liquid to be measured. Therefore, the silicon substrate surface must be coated.
Therefore, the above-mentioned cross section, that is, the side surfaces and the back surface of the device are subjected to thermal oxidation treatment so as to be covered with a silicon dioxide layer 31. However, if this is done alone, the silicon dioxide layer 31 becomes hydrated after long-term use, and ions such as H ⁺ and Na ⁺ enter therein, causing instability in measurement.

Therefore, in Japanese Patent Application Laid-Open No. 55-24603, the applicant proposed a chemical sensitive element and a method for manufacturing the same that solves the above-mentioned problems of the conventional chemical sensitive element and can be used stably for a long period of time. did. The entire surface of this chemically sensitive element, which is immersed in the substance to be measured (in most cases, a solution), is covered with a solution-impermeable film, which improves the stability and durability of the element. It is something. However, such a chemically sensitive element is
It has been found that when manufactured according to the manufacturing method proposed in Publication No. 24603, an element with poor moving point drift, poor S/N ratio, and poor durability is often obtained. As a result of examining these causes, we found that elements that cause such instability phenomena have a considerably rough etched side that is immersed in the substance to be measured, that is, an etched surface that has been selectively etched for the purpose of element separation, and that the etched surface is rough. During this process, it was discovered that various regions of the FET that had already been formed were damaged or altered. Possible causes of such problems are as follows.

(1) Since the etching patterns on both sides are formed independently using alignment marks provided on both sides of the silicon substrate, the patterns on both sides are misaligned and the etching end points do not match.

(2) Because the end points of etching do not coincide, the silicon substrate, which has become thinner due to etching, may partially crack due to the water pressure caused by stirring the etching solution just before the end of etching.

As a result of (1) and (2) above, crystal planes other than the (111) plane appear on the etched surface. These crystal planes include crystal planes with a high etching rate, so the etching on these planes with a high etching rate progresses from near the side edges to the front and back sides of the silicon substrate, thereby roughening the side surfaces. At the same time, the area of the FET that has already been formed may be damaged or deteriorated, resulting in a defective product at the final stage.Also, even if the FET is not defective, the sides of the device may be rough, resulting in damage to the ionic impurities formed in the subsequent process. Pinholes exist in the surface stabilizing film made of a transparent material or the like, which results in poor durability. Such a problem also occurs in Japanese Patent Application Laid-Open No. 53-25385.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a method for manufacturing a chemically sensitive element having excellent durability and stable characteristics.

In simultaneously manufacturing a plurality of field-effect transistor type chemically sensitive elements from a single semiconductor substrate, the present invention is directed to a portion of a semiconductor substrate of one conductivity type that includes a sensitive part formation region of each element, that is, at least during co-measurement. The parts that come into contact with the substance to be measured are selectively etched so that adjacent elements are separated from each other, and the parts other than the part that includes the sensitive part formation area are etched so that adjacent elements are connected without being separated from each other. a gate oxidation step of selectively etching to form a scribe line, then forming a source region, a drain region, a channel region and a channel stopper region in each element of the semiconductor substrate, and subsequently forming a gate film; At least a step of forming a film impermeable to the substance with which this surface comes into contact on the entire surface that comes into contact with the substance to be measured, a step of forming drain and source contact portions, and a step of forming the gate as necessary. The method is characterized in that a step of forming a sensitive film on the impermeable film in the region is performed, and then each element is separated from each other along the scribe line.

The invention will be explained in detail below with reference to the drawings.

FIG. 4 is a diagram for explaining the manufacturing process according to the present invention in which a large number of sensing elements are simultaneously formed on one semiconductor substrate 41. In the manufacturing process according to the present invention, each chemically sensitive element 42 that is formed at the same time is first separated near the sensitive part of each element from the adjacent element, and then scribed so that the adjacent elements are connected to each other in the part other than the sensitive part. It is characterized by forming a line. For this purpose, the front part 43 containing the sensitive part of the element 42 is made thin, the rear part 44 of the element is made wide, and the adjacent parts of the rear parts 44, that is, the parts 45 with cross hatches, are finally scribed without being separated. Only the scribe line for cutting is formed, and only the hatched portion 46 is completely removed. Part 4 below
6 will be called the removed portion. By doing this, the side surface of the element front portion 43 is also exposed at this stage, so the process is continued in this state, including the surface treatment of this side surface.

First, I will briefly describe the entire process. A semiconductor substrate, in this example, a p-type silicon substrate 41 whose surface is the (100) plane, is oxidized on both sides to a thickness of 0.5 to 1 μm.
After forming the SiO ₂ layer, photoetching is performed to remove parts other than the parts where the element will be formed (the parts marked with hatches and cross hatches in Fig. 4), that is, the scribe line 45 in Fig. 4 and the removed parts. The SiO ₂ layer 46 is removed, a shallow groove is formed in the scribe line 45, and the silicon substrate in the removed portion 46 is completely removed. This method will be described later. In this state, the front portions 43 of each element are separated from each other and their side surfaces are exposed. Next, after removing the SiO ₂ layer in the part where the element will be formed (the part not marked with hatches and crosshatches in Figure 4) by photo-etching, the known MOS type FET is removed.
The source region, drain region,
Form a channel stopper area, etc. After that, the gate oxidation process and the surface are coated with Si ₃ N ₄ or
After performing a step of covering with SiO ₂ to form a sensitive part and also covering the side surfaces of the sensitive part and completing parts such as the drain terminal and source contact, each element is separated along the scribe line 45, Finally, the separated side surfaces are coated with epoxy resin or the like to obtain a chemically sensitive element.

Next, while forming a scribe line 45,
Selective etching to completely remove the silicon substrate 41 in the removed portion 46 and separate the front portions 43 of each device from each other will now be described. Solutions for selectively etching in the surface (100) direction of the silicon substrate 41 include potassium hydroxide-based solutions and water-amine-based solutions.
ml), ethylenediamine (17 ml), and pyrocatechol (3 gr) at 110°C. This is discussed in “A Water-Amine-Complexing Agent” by RMFinne and DLKlein.
System for Etching Silicon”J.Electrochem.
Soc.Solid State Science, pp.965-970,
Stated in September 1967. Hereinafter, this etching will be referred to as APW etching. this
In order to remove the silicon substrate 41 in the removed portion 46 and separate the adjacent elements 42 from each other by APW etching, a method as shown in FIGS. 5a to 5d can be adopted.

FIG.
APW etching is performed to separate the front portions 43 of each element from each other. In this case, after accurately aligning the masks on both the front and back sides, the silicon substrate 41 on which _two SiO layers and a photoresist layer are sequentially formed on both sides,
It is possible to form an APW etching pattern using two SiO ₂ layers by exposing both sides between the two masks, and then perform APW etching from both sides simultaneously. The sequential process of mask alignment is shown in Figure 6a.
Shown in ~d. That is, the upper mask 47A and the lower mask 47B, which have a desired pattern formed on a photographic plate, are placed between the upper holding frame 48A and the lower holding frame 48B after accurately aligning the patterns with a microscope (Fig. 6). a). Upper and lower holding frames 48A,
48B are movably mounted along suitable guide rods 49 extending therethrough, and each holding frame is formed with a suitable opening 50 connected to a vacuum pump (not shown), thereby allowing the upper mask 4
7A to the upper holding frame 48A, and the lower mask 47B to the lower holding frame 48B, respectively. After accurately aligning the upper and lower masks 47A and 47B,
They are held by suction on the lower holding frames 48A and 48B and separated from each other (FIG. 6b). Then _SiO2 on both sides
A silicon substrate 41 on which a layer 51 and a photoresist 52 are sequentially formed is inserted between an upper mask 47A and a lower mask 47B (FIG. 6c), and this silicon substrate 41 is connected to an upper holding frame 49A and a lower side. It is inserted between the holding frames 49B and exposed from both sides (FIG. 6d). In this way, the silicon substrate 41
After forming an etching pattern using the SiO ₂ layer 51 on both sides, APW etching is performed from both sides at the same time.

In this way, if the removed portion 46 and the scribe line 45 are selectively etched first, alignment of the silicon substrate 41 with respect to the pattern is not necessary, and after the patterns on both sides are accurately aligned, silicon substrate 4
Accurate etching without pattern deviation can be performed by simply pinching the etching plate 1, so a smooth etched surface can be easily obtained. That is, when mask alignment is performed independently on the front and back surfaces of the silicon substrate 41 using respective mask alignment marks as landmarks, some misalignment actually occurs. If there is such a misalignment, when etching is performed from both sides, the end points of the etching will not match as described above, and this will cause the silicon, which has become thinner due to etching, to be exposed to the water pressure of the etching solution just before the end of etching. Some parts may crack due to twisting. As a result, crystal planes other than the (111) plane appear on the etched surface. These crystal planes include crystal planes with a high etching rate, so the etching of these planes with a high etching rate progresses from near the side edges toward the front and back sides of the silicon substrate, resulting in a smooth etching process. It will ruin the finished side. Photo A shows an SEM (scanning electron microscope) image of the front part 43 of the element from which the silicon substrate 41 of the removed portion 46 (see FIG. 4) has been removed by such etching.
(Magnification x 50) and an enlarged view of the side part in Photo B
(Magnification x 200). If the side surfaces of the device are rough in this manner, it becomes difficult to form a uniform film without pinholes when a surface stabilizing film is formed using an ion-impermeable material or the like in a subsequent step.

In the present invention, selective etching is performed before forming the FET, so if APW etching is performed with mask alignment as shown in FIG. In another embodiment of the invention, after the APW etching is completed, finishing etching is further performed using an isotropic nitric-fluoric acid-based etching solution. In this way, by etching with an isotropic etching solution after anisotropic APW etching, even if slight roughness occurs on the side surface due to APW etching, it can be smoothed out and a smooth etched surface can be obtained. The SEM image of the front part 43 of the element thus obtained is shown in Photo C (magnification x 50), and the enlarged side view is shown in Photo D.
(Magnification x 200). In addition, as a nitric acid-based etching solution, nitric acid:hydrofluoric acid is 4:1~
A composition of 8:1 with a trace amount of acetic acid added was used.

FIG. 5b shows a silicon substrate 4 similar to FIG. 5a.
APW etching is performed simultaneously from both sides of 1, but this APW etching stops just before the end,
Silicon bridge 53 left unetched
is removed using a nitric acid-based etching solution. As a result, even if some misalignment of the mask occurs, no trace thereof will appear on the etched surface, making it possible to form a smooth side surface.

Figure 5c is different from Figures a and b,
APW etching is performed only from one side of the silicon substrate 41. In this case, there is no necessity for misalignment of the mask, so there is almost no roughness on the side surface. Furthermore, after this APW etching is completed, SiO ₂ on the other surface of the silicon substrate 41 is removed.
By removing the layer 51 and further lightly etching it with a nitric-fluoric acid-based etching solution, the side edges can be rounded, and the surface stabilizing film coating can be more stably formed in the subsequent process.

FIG. 5d shows that a selective etching pattern is formed on one side of the silicon substrate 41, while the SiO ₂ layer is removed on the other side, and etching is performed from both sides simultaneously.
This is for performing APW etching. In this method, etching progresses over the entire surface of the other side, so that the silicon substrate 41 at the end of etching is
The thickness will be half of the thickness at the start of etching.
With this method, there is no fear of misalignment of the mask as in the case of FIG. Furthermore, if the surface is further etched with a nitric-fluoric acid-based etching solution after the APW etching is completed, the surface stabilizing film can be coated more stably in the subsequent process, similar to the case shown in Figure 5c. .

On the other hand, by APW etching, a scribe line 45 is also formed at the same time as the removal of the silicon substrate 41 in the removed portion 46 in FIG.
is thinner (0.8 mm) than the rear part 44, so the width of the removed part 46 is relatively wide, and since the rear part 44 of the element is wide (1 mm), the part 45 that becomes the scribe line
width is narrow. Therefore, the grooves formed in portion 45 by selective etching as described above are shallow. Note that the groove formed in the portion 45 at this time is used as a scribe line for separating each element later as described above, so the depth is 50 μm when the thickness of the silicon substrate 41 is, for example, 200 μm.
It is better to set it as a degree. Further, the scribe line 45 may be formed only on one side or both sides of the base.

As described above, the scribe line 45 is formed and the silicon substrate 4 of the removed portion 46 is
1 is removed and the element front portions 43 are separated from each other, a MOS type FET is formed in the portion that remains unetched in FIG. 4 (the portion without the hatches and crosshatches).

The FET formation process will be explained in detail below. 7th
The figure is a diagram showing the planar configuration of one element 42, and FIGS. 8 to 12 are A-A′ and B in FIG. 7.
-B', ..., EE' are cross-sectional views taken along each line. Furthermore, FIGS. 13a to 13e are plan views for explaining each process. In the following explanation, the base 41 has a specific resistance of about 10 Ωcm and a thickness of 150 μm.
P-type silicon having a (100) plane of about m is used, and the etching of the removed portion 46 (see FIG. 4) was carried out by the method shown in FIG. 5a or b.

(1) After APW etching, _two SiO layers 51 on both sides
(See Fig. 5) is removed with an HF solution, and the entire surface of the silicon substrate is further cleaned with a nitric-fluoric acid-based etching solution, and then the entire surface is oxidized and covered with _two layers of SiO.

(2) Remove the SiO ₂ layer in the hatched area in Figure 13a by photo-etching.

(3) Next, add 10 ¹⁸ phosphorus to the area where the SiO ₂ layer was removed to form source and drain regions.
Diffuses to a density of cm ^-3 . The depth of this diffusion is several μ
The distance between the source region and the drain region is 10 to 50 μm. Of course, these values can be changed as appropriate depending on the size of the entire element. FIGS. 8a to 12a each show the state after the above steps have been completed. A SiO ₂ layer 60 on the front side of the substrate 41, a SiO ₂ layer 61 on the back side of the substrate, a drain diffusion region 62, and a source diffusion region 63 are shown, respectively.

(4) Remove the SiO ₂ layer in the area indicated by hatching in FIG. 13b, and diffuse boron into this area to form a p ⁺ channel stopper area 64. 8th
FIGS. b to 12b each show this state. The channel stopper region 64 is for preventing a channel from being formed between the drain region 62 and the sorting region 63 except in the sensitive part at the tip of the element, that is, in the vicinity of A-A' in FIG. shall be 0.1 to 3 μm. As a result, the crosshatch portion 65 in FIG. 13b
A channel will be formed only in this case. Hereinafter, this channel area will be represented by the reference numeral 65. In this embodiment, the channel region 65 has a "U" shape. This is the transfer conductance gm which means the gain of the field effect transistor
This is to increase the channel width W since it is proportional to W/L when the length of the channel 65 is L and the width is W. Therefore, the shape of the channel 65 is not limited to the "U-shaped"shape;
It can be of any suitable shape, such as a "V" shape or a "W" shape. As described above, in this embodiment, the channel length L is 10 to 50 μm.

(5) SiO ₂ in the area indicated by the hatch in Figure 13c
The layer is removed by photoetching and phosphorus is diffused into this area to form the contact n ⁺ region 6.
6,67 is formed. Each of FIGS. 8c to 12c shows a cross section of each part at this time.

(6) The SiO ₂ layer above the device sensitive region 69, drain contact region 66, and source contact region 67, shown by hatching in FIG. 13d, is removed by photoetching.

(7) Next, dry oxidation is performed at 1150° C. for 30 minutes to form a SiO ₂ layer 70 with a thickness of several hundred to several thousand Å, for example, 1000 Å. As a result, gate oxide film 71 is formed above channel region 65. Excellent interfacial properties can be obtained between the silicon substrate 41 and this SiO ₂ insulating layer. Reducing the surface states at this interface is important in improving the electrical characteristics of the device. Note that at this time, a SiO ₂ film is also formed on the contact portions 66 and 67. Each of FIGS. 8d to 12d shows a cross section of each part in this state.

(8) Immediately after this, in order to stabilize the element surface, the front side of the element is covered with an insulating material that has excellent water resistance, density, and ion impermeability. Such materials include silicon nitride (Si ₃ N ₄ ), alumina (Al ₂ O ₃ ),
Tantalum pentoxide (Ta ₂ O ₅ ), tantalum nitride (TaN), silicon oxynitride (SiO _x N _y : however, 1>y/x+y0.2), aluminum oxynitride (AlO _x N _y ), and tantalum There are oxynitrides, etc.
The insulating layer is deposited by a method such as CVD (Chemical Vapor Deposition), sputtering, or electron beam evaporation to form an insulating layer with a thickness of several hundred Å to 1 μm, typically 500 to 1500 Å. For example, in the case of Si ₃ N ₄ film, it is H ₂ -SiH ₄ -NH ₃ system, and in the case of Al ₂ O ₃ film, it is H ₂ -
A good insulating layer can be formed by performing CVD using a CO ₂ -AlCl ₃ system at a high temperature of 900 to 1000°C. In this example, the Si ₃ N ₄ layer is 1000Å thick.
It was formed using the CVD method to a thickness of . Next, Si ₃ N ₄ on the back side
The layers are applied so that the entire surface of the element, especially the side surfaces of the front part 43, is completely covered with the Si ₃ N ₄ layer. This state is shown in each of FIG. 8e to FIG. 12e, and the reference numeral 72 indicates the insulating layer, in this case.
It has ₄ layers of Si ₃ N. In addition, according to the etching described in FIG. 5, since the side surface of the element front part 43 is smooth, the surface stabilizing film can be uniformly formed. In another embodiment, an additional SiO ₂ layer may be formed on the Si ₃ N ₄ layer 72. At this time, for example, after forming ₄ Si ₃ N layers on the element surface by CVD method, ₄ Si ₃ N layers and ₂ SiO layers are sequentially formed on the back side.
After that, a SiO ₂ layer may be formed again on the front side. Note that the thickness of this SiO ₂ layer is 1000 Å or less. Further, in this example, the growth temperature of the Si ₃ N ₄ layer was 950°C.

After this, the formation of the source and drain terminals and the gate part (sensing part) is proceeded.

(9) First, when the SiO ₂ layer is formed on the Si ₃ N ₄ layer 72, the contact parts 66 and 67 (13th
The SiO ₂ layer on top of figure d) is removed by etching. At this time, the back side and the front part 43 of the element are covered with wax.

(10) Next, the Si ₃ N ₄ layer 72 of the contact parts 66 and 67
is removed by etching. A hot phosphoric acid solution is used as the etching solution. instead _{of Si3N4}
Hot phosphoric acid solution is used as the etching solution even when Al ₂ O ₃ is used, and hot phosphoric acid solution is used as the etching solution when Ta ₂ O ₅ and TaN are used.
Use a NaOH-H ₂ O _2- based etching solution.

(11) Contact areas 66 and 67 are formed in the gate oxidation step (7).
The SiO ₂ film formed on the surface is also removed by etching. In addition, in step (8), the Si ₃ N ₄ layer 72
If a SiO ₂ layer is formed on top of the
Make sure to also remove the _SiO2 layer.

Through the above steps (9) to (11), the surfaces of contact diffusion regions 66 and 67 are exposed.

(12) Next, using a 50 μm thick Mo plate vapor deposition mask, apply Al to the area shown by the hatch in Figure 13 e.
, and the drain contact 73 and the source contact 7
form 4.

The sensitive part, that is, the gate part of the element formed above is formed by the gate film as shown in FIG. 8f.
SiO ₂ layer 71 and Si ₃ N ₄ , Al ₂ O ₃ , Ta ₂ O ₅ , TaN,
It is formed by an ion-impermeable film ((surface stabilizing film) 72 made of any one of SiO _x O _y , AlO _x N _y and tantalum oxynide, and at the same time the Si ₃ N ₄ layer or Al ₂ The _O3 layer or _{the Ta2O5} layer acts as an impermeable membrane and is sensitive to H ⁺ ions, so it can be used as a PH sensor.That is, the process of forming an impermeable membrane and the process of forming a sensitive membrane are combined. would have been carried out at the same time.

(13) Next, scribe line 45 shown in Fig. 4
The elements are separated along the lines, and the side surfaces of the separated rear parts 44 of the elements exposed are coated with epoxy resin 75 or the like to complete the entire process. Each cross section in this state is shown in FIGS. 8f to 12f, but coating with epoxy resin 75 or the like is not always necessary depending on the intended use of the element.

For applications other than PH sensors, when detecting various ions, etc., for example, after step (11) above, form a chemically sensitive layer according to the purpose, and then form contact areas and other chemically sensitive layers. However, after that, the sensitive layer in the contact area and other areas that do not require a chemically sensitive layer may be removed before proceeding to the step (12) for forming the drain and source contact areas. FIGS. 14a and 14b show examples in which the chemically sensitive layer 81 is formed at the tip of the element in this way, and FIGS. 7A-A' and B-
FIG. 3 is a cross-sectional view taken along line B'. Note that the step of forming the chemically sensitive layer can also be performed after step (13).

The types of chemically sensitive layers will be explained below.

As an ion activity and concentration detection device, that is, an ion sensor, for example, silicon nitride (Si ₃ ^N ₄ ), alumina (Al ₂ O ₃ ),
Tantalum pentoxide (Ta ₂ O ₅ ) membranes are available. In fact, when a silicon nitride film or alumina (Al ₂ O ₃ ) film with a thickness of about 1000 Å is used as a sensitive part, the pH range is 1 to 13, which is almost the same as a conventional glass electrode53
An interfacial potential of ~56 mV/PH is obtained. In addition to this, 6% is known as conventional glass electrode glass.
Soda lime silicate glass with the composition of CaO, 72% SiO ₂ , 22% Na ₂ O (% is molar ratio), 68%
_SiO2 , 25% _Li2O , 7% CaO or 67%
Lithium glass having a composition of SiO ₂ , 25% Li ₂ O, 8% BaO, etc. can also be used as a material constituting the sensitive part. These inorganic layers can be formed by a CVD method, a sputtering method, an electron beam evaporation method, an alkoxide solution coating method, or the like. Also, as a sodium (Na ⁺ ) sensor, aluminosilicate glass (SiO ₂ - Al ₂ O ₃ - Na ₂ O), especially 71% SiO ₂ , 18
% Al ₂ O ₃ , 11% Na ₂ O and borosilicate glass (SiO ₂ -B ₂ O ₃ ) are available. Furthermore, as a potassium (K ⁺ ) sensor, aluminosilicate glasses, especially 69% SiO ₂ , 4% Al ₂ O ₃ , 27
% Na ₂ O and borosilicate glass can be effectively used. These glass layers can also be formed by a CVD method, a sputtering method, an electron beam evaporation method, or an alkoxide solution coating method.

Instead of inorganic materials as mentioned above, the sensitive part of some ion sensors consists of ion exchange materials, antibiotics, etc. maintained in polyvinyl chloride, polyurethane, silicone rubber or other neutral hydrophobic matrices. You can also. For example, antibiotics such as valinomycin and crown ether are suitable for potassium ions (K ⁺ ), nigirisin and other antibiotics are suitable for sodium ions (Na ⁺ ), and calcium didodecyl phosphate and other antibiotics are suitable for calcium ions (Ca ²⁺ ). Ion exchange materials can be used. Although the structure of the typical cation-sensitive portion has been described above, such a chemical sensing element also functions satisfactorily for anions. For example, if the sensitive part is made of a silver sulfide/silver iodide mixture, it can be used as a sensor for CN ^- .

As a sensitive element for various gases, that is, a sensitive part of a gas sensor, a metal film or an organic polymer film formed by vapor deposition, sputtering, etc., a special ion exchange film, etc. can be used. For example, for hydrogen gas (H ₂ ), a palladium vapor-deposited film is used, for oxygen gas (O ₂ ), a gold vapor-deposited film or polyethylene film is used, and for water vapor (H ₂ O), it is obtained by sputtering. ZnO film is effective. Furthermore, for carbon dioxide gas (CO ₂ ), an ion exchange membrane containing HCO ₃ ^- can be used. In the above-described ion sensor or gas sensor, target ions or gases are selectively adsorbed to the sensitive part, causing a change in interfacial potential.

When measuring antigen or antibody concentration, the antibody or antigen is covalently bonded to the surface of a membrane made of a hydrophobic polymer such as polyvinyl chloride, polystyrene, polyethylene, polypropylene, silicone, polyurethane, polycarbonate, or PlEF. can be configured. When a sensor with such a membrane comes into contact with a solution containing an antigen complexed with an antibody bound to the surface of the membrane (or an antibody complexed with an antigen bound to the surface of the membrane), an immunochemical reaction occurs. As a result, the surface potential of the membrane changes. For example, an insulin sensor using an antibody immobilized on a polyvinyl chloride membrane can be considered.

FIG. 15 shows another embodiment of the drain electrode section, and is a sectional view taken along line CC' in FIG. In the above-mentioned embodiment, the source and drain electrodes are formed by vapor depositing Al in the contact area, and in actual use, the source and drain lead wires are attached to these Al electrodes by ultrasonic bonding. I will do it. In the embodiment shown in FIG. 15, a 500-3000 Å thick aluminum (Al) layer 82 is deposited to make contact, then heat treated in nitrogen at 550°C for 10 minutes, and then a 100-1000 Å chromium (Cr) layer is placed on top. 83, 1000～
6000 Å chromium-copper (Cr-Cu) layer 84 and 2000 Å
A copper (Cu) layer 85 of ~1 μm is sequentially formed, and a solder coating 86 is applied thereon. This provides electrically and mechanically satisfactory contact. Note that each of the metal layers described above is formed by vacuum deposition, sputtering, or the like. Further, although the drain electrode has been described here, it goes without saying that a similar configuration can be adopted for the source electrode.

Next, the operating principle of the chemically sensitive element will be briefly described with reference to FIG. 8f.

In the sensing element having the above-described configuration, when the gate portion is positively biased with respect to the source region 63,
Holes existing at the interface between the silicon substrate 41 and the SiO ₂ insulating layer 71 are driven into the substrate, and conversely, electrons are attracted to the interface, forming a conduction channel in the region 65 between the source region 63 and the drain region 62. is formed. Therefore, when a potential difference is applied between the source region 63 and the drain region 62, a current flows between the source and the drain through the channel region 65. At this time, the conductance of the channel, that is, the magnitude of the current, depends on the amount of charge existing at the interface between the base body 41 and the gate film 71, that is, the potential difference between the gate portion and the source region 63. In other words, the gate voltage controls the current in the channel region 65, and the magnitude of the channel current is a measure of the gate voltage. That is, when the sensitive part 81 provided above the gate insulating layers 71 and 72 interacts with a substance in contact with it and an electrochemical potential is generated in the sensitive part 81, this causes a channel current, that is, a drain current I _D is modulated. Therefore, by detecting this channel current, it is possible to quantify the substance that is in contact with the sensitive part 81 and its characteristics.

As described above, according to the present invention, first, that is, before forming each region of the FET, the front part of the element where the sensitive part is formed is completely separated from the adjacent elements by selective etching. , each region of the FET can be stably formed in subsequent steps. Therefore, a chemically sensitive element with excellent drift and S/N can be obtained. Furthermore, even when selective etching is performed from both sides, there is no need to align the semiconductor substrate with respect to the pattern, and mask alignment can therefore be performed easily and accurately, making it possible to form a smooth etched surface. . Therefore, since the impermeable film (surface stabilizing film) can be formed uniformly without pinholes, a chemically sensitive element with excellent durability can be obtained. Furthermore, it is possible to produce various sensing elements in small size and at low cost, which can be manufactured in large quantities using integrated circuit technology, and can be applied to various substances because the material and structure of the chemically sensitive part can be easily controlled. I can do it.

[Brief explanation of the drawing]

Figure 1 is a diagrammatic cross-sectional view showing the structure of a conventional field effect transistor type chemical sensing element, Figure 2a,
b is a diagrammatic plan view and a sectional view showing another conventional example;
FIGS. 3a and 3b are diagrammatic cross-sectional views showing the structure of another conventional example, and FIG. 4 is a plan view showing how a large number of chemically sensitive elements are formed on one wafer according to the present invention. Figures 5a-d are diagrams for explaining four methods of selective etching; Figure 6a;
~d are diagrams for explaining the sequential steps when performing selective etching according to FIGS. 5a and b; FIG. 7 is a diagram showing the planar configuration of one element; Figure 12 a to f are Figure 6 A-A', B-
B', ..., Diagrams showing the progress of the process in the cross section along E-E', Figures 13a to 13e are plan views showing the parts to be processed in each process, Figure 1
4a and 4b are diagrams showing another embodiment of the present invention, and FIG. 15 is a diagram showing the structure of the drain terminal portion of still another embodiment of the invention. 41...Silicon base, 42...Element, 43...
...Element front part, 44...Element rear part, 45...Scribe line, 46...Removed part, 60, 61...
SiO ₂ layer, 62...Drain diffusion region, 63...
Source diffusion region, 64... Channel stopper region, 65... Channel region, 66, 67...
Contact region, 68...SiO ₂ layer, 70...
SiO ₂ layer, 71... gate film, 72... Si ₃ N ₄ layer,
73... Al vapor deposited layer for drain terminal, 74... Al vapor deposited layer for source terminal, 75... Epoxy resin.

Claims (1)

[Claims] 1. When simultaneously manufacturing a plurality of field-effect transistor type chemically sensitive devices from a single semiconductor substrate, the portion of the semiconductor substrate of one conductivity type that includes the sensitive part formation region of each device, that is, a small The parts that come into contact with the substance to be measured during co-measurement are selectively etched so that adjacent elements are separated from each other, and the parts other than the part that includes this sensitive part formation area are not separated from each other. A source region, a drain region, a channel region, and a channel stopper region are formed in each element of the semiconductor substrate, and then a gate film is formed. an oxidation step, a step of forming a film impermeable to the substance with which this surface comes into contact on the entire surface that comes into contact with the substance to be measured, a step of forming drain and source contact portions, and further steps as necessary. A method of manufacturing a chemically sensitive element, comprising the steps of forming a sensitive film on the impermeable film in the gate region, and then separating the elements from each other along the scribe line. 2. Etching is selectively and simultaneously performed on both sides of the semiconductor substrate to separate adjacent elements from each other in a portion including a sensitive portion formation region of each element, that is, a portion that comes into contact with a substance to be measured during joint measurement. A method for manufacturing a chemically sensitive element according to claim 1. 3. Etching is performed selectively and simultaneously on both sides of the semiconductor substrate using an anisotropic etching liquid, so that adjacent areas including the sensitive part formation region of each element, that is, at least the area that comes into contact with the substance to be measured during co-measurement, are etched with an anisotropic etching solution. The chemical sensitization method according to claim 1, characterized in that after the elements to be separated are separated from each other, etching is performed using an isotropic nitric-fluoric acid-based etching solution to smooth the sides of each separated element. Method of manufacturing elements. 4. Etching both sides of the semiconductor substrate selectively and simultaneously with an anisotropic etching solution, and immediately before the end of this etching, change the etching solution to an isotropic nitric-fluoric acid-based etching solution and perform the remaining etching. The chemical sensing element according to claim 1, wherein adjacent elements are separated from each other at a portion of each element that includes a sensitive part formation region, that is, at least a portion that comes into contact with a substance to be measured during co-measurement. Production method. 5. Etching is selectively performed only from one side of the semiconductor substrate, so that adjacent elements are separated from each other in a portion including a sensitive part formation region of each element, that is, a portion that comes into contact with a substance to be measured during co-measurement. 2. The method for manufacturing a chemically sensitive element according to claim 1, wherein the chemically sensitive element is separated. 6. Etching selectively one surface of the semiconductor substrate and etching the entire surface of the other surface simultaneously,
1. The method according to claim 1, wherein the semiconductor substrate is made thin so that adjacent devices are separated from each other in a portion including a sensitive portion forming region of each device, that is, a portion that comes into contact with a substance to be measured during joint measurement. A method for manufacturing a chemically sensitive element.