JPS62223859A - Data recording method and data recording and reproducing method for vtr - Google Patents

Abstract

PURPOSE:To prevent the occurrence of malfunction by recording the data of the same contents repeatedly with plural types of data as the signal format where the data are arranged between adjoining two headers of a fixed pattern together with an identifying signal to show the type of the data or individually. CONSTITUTION:Pulses (c) and (d) are supplied respectively through a recording control circuit 31, a driving amplifier 32 and a switch circuit 33 to a control head 34 and causes a recording electric current (e) to flow to the control head 34. The recording electric current (e) flows in the normal direction at the high level period of the pulse (c), flows in the negative direction at the high level period of the pulse (d) and does not flow at the period when the pulses (c) and (d) are both low levels and at the low level period of a pulse (b) when the switch circuit 33 is off. As such a result, the reference pulse of a reproducing control pulse (a) is kept as it is, a negative polarity pulse is erased by the positive or negative recording electric current (e), the recording electric current (e) is changed from the positive direction to the negative direction, then, the negative polarity pulse is newly recorded. The action is repeated until the record ing of all bits of recording data is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a data recording method and a data recording/reproducing method for a VTR, and particularly to a magnetic tape on which video signals and audio signals are recorded and reproduced by a VTR (magnetic recording/reproducing device). The present invention relates to a method of recording data regarding position information, arbitrary comment information, etc. on a magnetic tape, and a method of recording and reproducing the same.

Prior Art The inventor of the present invention has filed a patent application (invention title: rVTR data recording and reproducing device) dated the same date as the present application for home VTR.
The duty cycle of the control pulse is varied based on the position information of the magnetic tape used in the system, arbitrary comment information, etc., and is recorded on the control track, which can be played back and displayed, and can be accessed randomly. We proposed a data recording and reproducing device for VTR.

According to this proposed VTR data recording and reproducing device,
Since multiple types of data are appropriately selected and recorded and reproduced on the control track, it can be constructed at a lower cost than a VTR that records and reproduces SMPTE time code, and it is also less expensive than the conventional VTR described in Japanese Utility Model Publication No. 57-34633. V
Compared to TR, it has excellent features such as being able to freely record any information with extremely simple operations, allowing random access, and being able to be used in a wide variety of ways.

Problems to be Solved by the Invention However, the control pulse has a period of one frame (1/1).
Normally, the data transmission bit rate is extremely low at 30 bits/second, and it is difficult to select multiple types of data. In the above-mentioned proposed device which records data on the control track, random information data having no continuity is recorded on the control track. For this reason, when playing, Drotsubua
If there is a dropout, there is usually no correlation with previously read data, so the dropout cannot be corrected and malfunction occurs. In particular, in the case of fast forwarding or rewinding a VTR, tape running is unstable, so dropouts are likely to occur, and there is a high risk of malfunction.

Therefore, the present invention provides VT
It is an object of the present invention to provide a data recording method and a recording/reproducing method for a VTR that can effectively record R data and prevent malfunction even if dropout occurs.

Means for Solving the Problems The VTR data recording method of the present invention appropriately selects a plurality of types of data such as magnetic tape position information and comments on the recorded information content, and records data at a fixed period according to the value of the selected data. A method for recording on a control track by varying the duty cycle of a control pulse, the method comprising: recording data on a control track by varying the duty cycle of a control pulse, wherein multiple types of data are recorded between two adjacent headers of a fixed pattern, together with an identification signal indicating the data type, or alone; This is a signal format in which data is arranged on a control track, and data of the same content is repeatedly recorded three or more times on a control track.

Further, the data recording and reproducing method for a VTR of the present invention detects and reproduces the data recorded on the control track as described above from the duty cycle of the reproduction control pulse, and among the data, the data recorded on the control track is reproduced. It is configured to compare the values of data that are successively reproduced the same number of times as the number of times the data is repeatedly recorded, and reproduce and output two or more data values that are the same as the true data value. .

Effect: The plurality of types of data are appropriately selected and input, and a signal format is placed between fixed pattern headers together with an identification signal indicating the type of data, or alone, and a signal of that signal format is formed. (variably modulates the duty cycle of the control pulse)
, the control pulses obtained thereby are recorded on the control track. Furthermore, the above data is sequentially recorded with the same content repeated three or more times.

On the other hand, during reproduction, the values of two or more data that are subsequently reproduced among the reproduced data are compared, and the values of the two or more data that are not the same are output as the true data values.

Embodiment FIG. 1 shows an embodiment of the signal format of each data recorded and reproduced by the method of the present invention. The present invention is a method for appropriately selecting a plurality of types of data, recording it on a control track on a magnetic tape, and reproducing it by varying the duty cycle of a control pulse having a constant period according to the value of the selected data. Figure 1 (A) to (C)
shows three types of data signal formats.

FIG. 1(A) shows a signal format of one embodiment of address data. In the figure, 1-1 to 1-4 are 11-bit headers, for example, the most significant bit (MSB) and the least significant bit (LSB) have a value of "0", and the remaining second
This is a fixed pattern signal in which the value of each of the 9 bits from the 1st bit to the 10th bit is [1]. Header 1-
After 1 to 1-3, 4 bits x 4 digits address information data 2
-1 to 2-3 are arranged.

Each of the address information data 2-1 to 2-3 is a BCD in which each digit of "1000", [100 J, r+J, and "-" has a 4-bit numerical value.
It is a total of 16 bits of data expressed in code. Of these, the 4 bits of the most significant "thousand" digit are header 1.
It is placed in the 4 bits immediately after -1 to 1-3, and its value can be any value from "0" to "9", with 10
"10" to r15J in hexadecimal (i.e. rA in hexadecimal)
J to "F"). It is detected that the value of these 4 bits immediately after the header indicated by 1-1 to 1-3 etc. is neither the hexadecimal value rAJ nor "B" of the identification signal described later. In a reproduction system, which will be described later, it is possible to identify that the reproduced data is address information data.

This address information data is an arbitrary address entered from the keyboard, for example, I'0100J, r0175J, r021.
0J, r1500J, r2000J,! :Even if it is random data, there is certain address information that determines continuity from the beginning of the tape (for example, rooloJ, ro020
J, ro030J,...) may be used.

In this way, the address data is recorded and reproduced in 27-bit units consisting of an 11-bit header and 16-bit address information data in a time-series manner.

Next, FIG. 1(B) shows a signal format of one embodiment of character (comment) data. In the same figure, 3-1 and 3-
2 are headers each having an 11-bit fixed pattern, the values of which are the same as those of headers 1-1 to 1-4 shown in FIG. 1(A). The 4 bits immediately before and 4 bits immediately after the header 3-2 each have a hexadecimal value of "
The identification signals 4-2 and 4-3 selected as "Δ" are arranged (the same applies to the header of the head 3-1 etc.). This identification signal allows a reproduction system, which will be described later, to identify that the reproduced data is character data.

The 4 bits immediately after the header 3-1 contain the above identification signal 4-1.
1 is arranged, and after that, a total of ten 6-bit character information data Do to D9 and a 4-bit identification signal 4 are arranged.
-2 are arranged sequentially.

The above character information data D. Each of ~D9 is a part of the ASCII code (e.g. from space SP to uppercase 7)
By using only 59 characters (up to 59 characters), the 8-bit ASCII code is compressed to 6-bit, and the bit rate is lower than that of the existing ASCII code.

The identification signal is placed not only immediately after the headers 3-1 to 3-2, etc., but also in the immediately preceding 4 bits as shown in 4-2.
Since this character data has a higher bit rate than the other two types of data, this is to ensure that the reproduction system can immediately identify it as character data not only during fast forwarding but also during rewinding.

In this way, character data consists of an 11-bit header, two 4-bit identification signals, and 60 bits (=6 bits x 10).
The information is recorded and reproduced in 79-bit units, which are composed of character information data, in chronological order.

Next, FIG. 1(C) shows a signal format of one embodiment of special function data. In the figure, headers 5-1 to 5-4 are headers 1-1 to 1-3 shown in FIG. 1 (Δ) and (B).
．． ．． 3-1 and 3-2, respectively, are selected to be the same value, 1
This is a 1-bit fixed pattern signal. Header 5-1~5
The 4 bits immediately after -4 contain a 4-bit identification signal 6-1 whose hexadecimal value is selected as rBJ, as shown by B+, respectively.
~6-4 are arranged. The next 12 bits of the identification signals 6-1 to 6-3 are arranged with special function information data 7-1 to 7-3 consisting of three digits of four bits of the BCD code.

The identification signals 6-1 to 6-4 allow the reproduction system to identify that this data is special function data.

In this way, the special function data consists of an 11-bit header and a 4-bit header.
The 27-bit unit consisting of a 12-bit identification signal and 12-bit special function information data is recorded and played back in chronological order. An example of the values in decimal numbers and the contents of the corresponding special functions are summarized in the following table.

In the table above, skip is a mode that automatically fast-forwards the recording section from the start point to the end point and does not play it back. Used when you want to skip the playback.

The above three types of data can be selected and recorded arbitrarily by the user of the VTR, but the present invention is characterized in that the same data is repeatedly recorded three or more set times.

FIGS. 2A and 2B show recording patterns of an embodiment of a control track recorded by the method of the present invention.

FIG. 2(A) shows a pattern in which address data 8 is repeatedly recorded with the same content three times on the control track, and then special function data 9 is repeatedly recorded with the same content three times.

Further, FIG. 2(B) shows a pattern in which character data 10 is repeatedly recorded with the same content three times on the control track. In FIGS. 2(A) and 2(B), the hatched portion indicates a header, and the symbol ■ indicates the identification signal whose hexadecimal values are rAJ and rBJ, respectively.

Next, to explain a recording and reproducing apparatus that implements the method of the present invention, FIG. 3 shows an overall configuration diagram of an example of a data recording and reproducing apparatus. In the figure, the VTR 11 includes a 1-chip microcomputer 12. Read/write circuit 13. It has a built-in character generator 14, etc., and in addition to the display section 15 similar to a normal VTR, a data recording/playback operation section 16 and a character output on/off switch 17 are added to the display panel surface. The configuration is such that a keyboard 18 is connected. Also,
The VTR 11 is equipped with a lid 19 that opens and closes when a tape cassette is inserted or removed, like a normal VTR.

Further, the VTR 11 outputs its reproduced output video signal and audio signal, as well as data to be recorded and reproduced, to a monitor television 21 via a cable 19.

The comment on-screen switch 28 in the data recording/playback operation section 16 is a switch for switching the display on the screen 29 of the monitor television 21, and is set to on (ON> and off (OF)).
It is connected to one of the three switch switching positions of F> and SCROLL>,
When it is in the [ON] position, the words rKEY INj and “
In addition to displaying the characters TAPE 0UTJ, a 10-character key manual display is displayed on the right side of the same line as the rKEY INJ character display, and a 10-character comment played from the control]-roll track is displayed on the right side of the rKEY INJ character display. The characters 0UTJ are displayed on the right side of the same line (this display mode is hereinafter referred to as "two-line display mode").

Also, the comment on-screen switch 28 is turned OFF.
When in position J, no characters are displayed, and rsc
The sword at the ROLLJ position is 10 per line within the range 22 surrounded by the two-dot chain line on the screen 29 of the monitor television 21.
A total of nine lines of characters are displayed (this display mode is hereinafter referred to as "scroll display mode"). In this scroll display mode, display in two-line display mode is not performed.

Next, the configuration and operation of the main parts of the VTR 11 will be explained in the fourth section.
This will be explained together with one block system member shown in the figure.

In FIG. 4, the same components as those in FIG. 3 are given the same reference numerals. In this embodiment, there are four types of data that can be recorded, and the switch SW + is configured to select only one of the negative ones.
rAl) DRESSJ, rcOMENTJ and rlND
When a low level signal is applied to the input port indicated by EXJ, the recording mode for the special function data, address data, character data, and index signal is entered. Here, the index signal is a signal in which a certain value is repeated a certain number of times, and is used for relative cue playback.

In the recording mode, the microcomputer 12 determines the data to be recorded based on the signal from the switch SW1, and according to the data to be recorded from the keyboard 18 etc., as shown in FIG. 1(A).
- Generate and output data in a predetermined format as shown in (C).

Note that if the microcomputer 12 determines that the signal to be recorded is an index signal, it immediately records the address, or if it determines that the signal to be recorded is an address code, it inputs the numerical address from the keyboard 18 or the character key in the masterpiece section 16. After storing the code in the data memory (RAM), V T
When it is determined that R is in the reproduction mode, it is determined whether or not the comment rewrite key 27 has been pressed. This comment rewrite key 27 is pressed by the user when the user puts the VTR in playback mode and detects the beginning position of the place where data is to be recorded by monitoring the playback image on the monitor television 21.

When the microcomputer 12 detects that the comment rewrite key 27 has been pressed, it synchronizes the phase with the reference pulse of subsequent reproduction control pulses and varies the duty cycle of the control pulse bit by bit according to the format of the recorded data. The read/write circuit 13 performs the operation U' and continues in that state until the recorded data is completed.

Next, the data recording operation in this reproduction mode will be explained with reference to FIGS. 4 and 5A to 5F.

The recorded magnetic tape on which data is to be recorded is stored in a tape cassette and loaded into the VTR 11.
During normal playback, the magnetic tape is pulled out from the cassette and loaded onto a prescribed tape bus (loading state) where it is wound diagonally over a prescribed angle range around a rotating body to which a rotating head is attached. The fourth
The control pulse reproduced by the control head 37f shown in the figure is used as a reference signal for the phase control system of the head servo circuit to keep the rotational phase of the rotating head constant, or as a cab stanza to keep the rotational phase of the kill buskun constant. It is well known that the signal is used as a comparison signal for the phase control system of the control circuit.

Here, while the control pulse during recording is a square wave, the playback control pulse is differentiated according to the differential characteristics of the head, and becomes a positive pulse at the rising edge of the recording square wave, and a negative polarity pulse at the falling edge of the recording square wave. is reproduced with a waveform as shown by a in FIG. Pulses are not used in servo circuits.

In this case, the recording current magnetic tape is reproduced and the positive polarity control pulse (hereinafter referred to as "reference pulse") used for the servo circuit is normally supplied to ensure normal servo operation. Because it is necessary to perform recording while changing the duty cycle of the control pulse according to the recording data, re-recording (erasing) is prohibited during the reproduction period of the reference pulse and some period before and after it, and In order to erase the section between adjacent reference pulses and re-record (rewrite) a signal such that the reproduction control pulse has negative polarity, the microcomputer 12 performs the steps shown in FIG.
) is applied to the switch circuit 33 as a switching pulse, and is turned on only during its high level period.

Also, at the same time, the microcomputer 12 outputs its output port R.
As shown in FIG. 5(C), the signal from the ECCNT 1 to the recording control circuit 31 rises at the rising edge of pulse b, and
A period according to the value of each bit of data to be recorded (however, this period is smaller than the high level period of pulse b)
It generates and outputs a pulse C that falls at the falling edge of the pulse C, and outputs it from its output port RECCNT2 to the recording control circuit 31.As shown in FIG. A pulse d which falls immediately before the falling edge of pulse b is generated and output so that the negative polarity pulse of pulse a can be erased.

Pulses C and d are supplied to the recording control circuit 31. Drive amplifier 3
2. The signals are supplied to the control head 34 through the switch circuits 33, respectively, and the signals shown in FIG.
) A recording current e as shown in FIG. Recording current e is pulse C
It flows in the positive direction during the high level period of pulse d, and flows in the negative direction during the high level period of pulse d, but does not flow during the period when both pulses C and d are at low level and during the low level period of pulse b when the switch circuit 33 is off.

As a result, the reference pulse of the reproduction control pulse a remains unchanged, the negative polarity pulse is erased by the positive or negative recording current e, and the negative polarity pulse is erased at the time when the recording current e changes from the positive direction to the negative direction. A new record will be created. This operation is repeated until recording of all bits of recording data is completed. When the recorded magnetic tape recorded in this manner is subsequently reproduced, the reproduction control pulse waveform becomes as shown in FIG. 5(F).

This reproduction control pulse has a period of one frame,
Moreover, the reference pulse position is the same as before, but the duty cycle is such that 1 bit of the recorded data is "1".
This becomes the first value, and 1 bit of the recorded data is "0".
, it becomes the second value, and if no further data is recorded, 3'' becomes the third value between them.Also, when the same data value is repeated three times in a predetermined signal format, recorded.

Note that when a low level signal is applied to the input capo-r-INDEX by the data select switch SW This is recorded and becomes the index signal.

Note that data recording can also be performed in the VTR recording mode. In this case, the pulse width of the recording control pulse, which is a square wave with a period of one frame, for example, is modulated according to recording data and recorded. In addition, even in this recording mode, wait until the comment rewrite key 27 is pressed before starting VF.
It is also possible to record R data easily by changing the software of the microcomputer 12.

Next, the cueing operation based on the data written as described above will be explained. Cueing can be performed in either the loading state (playback, forward/reverse search) or unloading state (fast forward 9 rewinds).
It is necessary to detect whether rO is in the “ON” switch position.
When the NJ switch is in the n position, the switch circuit 28a in FIG. The internal memory (
RAM).

The output signal of this character generator 14 is
11 from the recorded magnetic tape and input to the input terminal 44 shown in FIG. The display can be done within.

Thereafter, the microcomputer 12 places the VTR 11 in fast forward or rewind mode, reads the recorded data from the duty cycle of the control pulses played from the control track during that mode, and compares it with the input data stored in memory. However, when the two values match twice or more, the VTR is put into playback mode and then enters the desired playback mode.J:Una control is performed.

Here, to explain the reading of recorded data, in the above-mentioned fast forward or rewind mode, the recorded magnetic tape is run at high speed while stored in the tape cassette, so the control head 34 uses a control pulse. cannot be played. However, during this female forwarding or rewinding mode, the MR head 39 is arranged to slide on the back side of the recorded magnetic tape stored in the tape cassette and on the back side of the control track. Therefore, the control pulse is regenerated by the MR head 25 and sent to the Schmitt trigger circuit 4 through the amplifier 40 shown in FIG.
1.

The Schmitt trigger circuit 41 generates a pulse h as shown in FIG. 6(B), which rises when a positive polarity pulse of the reproduction control pulse q as shown in FIG. 6(A) arrives and falls when a negative polarity pulse arrives. This pulse h is output to the microcomputer 12 through the switch circuit 37 connected to the terminal UNLOAD side by a switching signal from the terminal 38 during the fast forward and rewind modes. On the other hand, the timing generator 42 rises at the timing of the duty cycle between the maximum duty cycle and the minimum duty cycle of the reproduction control pulse q, and at the timing of the reference pulse, as shown in FIG. 6(C). A timing pulse i that is set to fall is generated.

The microcomputer 12 latches the pulse h at the rising edge of the timing pulse i, as shown in FIG. 6(D).
After capturing the detected data as shown in the figure below, format it with hardware or software, read out the written data, and if the same value occurs two or more times in a row as described later, it will be recognized as the true value by the main 11 lactation generator. 14° addition circuit 43. It is output through the output terminal 45 and displayed on the Nita television 21. Substantially the same operation is performed in the scroll display mode (at this time, the switch circuit 28b in FIG. 4 is on).

Next, the circuit configuration and operation which are the main parts of the reproduction system of the present invention will be explained with reference to FIG. In the figure, the same components as in FIG. 4 are given the same reference numerals.

In FIG. 4, the microcomputer 12 makes a decision as to whether or not the three pieces of data that are successively reproduced have the same value, but in FIG. 7, this is implemented using hardware. terminal 50
The incoming reproduction control pulse is supplied to the timing generator 42 while being applied to the data input terminal of the D flip-flop 51, where the pulse 1 from the timing generator 42 as shown in FIG. It is latched at the rising edge of . As a result, reproduced data as shown in FIG. 6(D) is serially taken out from the Q output terminal of the D flip-flop 51, and serially input to the 15-bit shift register 52 and the 64-bit shift register 53. As the shift clock CK of the shift registers 52 and 53, a clock from the timing generator 42 whose phase is synchronized with the reference pulse is used.

When the upper 11 bits of the 15-bit data temporarily stored in the 15-bit shift register 52 become the above-mentioned header, the header detection circuit 54 detects a known 11-bit fixed pattern header, and from this the header is detected. The detection signal is passed through the AND circuit 56 and sent to the latch circuit 57.
58 and 59 as latch pulses, respectively. In addition, 1 temporarily stored in the 15-bit shift register 52
Of the 5 bits of data, the lower 4 bits of data are supplied to the identification signal detection circuit 55. Identification signal detection circuit 5
5 outputs a high level signal only when the value of the input signal 4 bits is rAJ in hexadecimal notation, and otherwise outputs a low level signal.

Since the latch circuit 57 latches the output signal of the identification signal detection circuit 55 when the header detection circuit 54 detects the header, the latch circuit 57 latches the 4-bit identification signal or data placed immediately after the header. Become. Therefore, a high level signal is taken out from the latch circuit 57 when the reproduced data is the aforementioned character data, and a low level signal is taken out when the reproduced data is address data or special function data, and this output signal is Output terminal 78
while being output as a flag to the data selector 64.
65, 71, 72 and 75 as select signals.

On the other hand, the 64-bit data output in parallel from the 64-bit shift register 53 is supplied to the latch circuit 58, its lower 16 bits are supplied in parallel to comparators 60 and 62, respectively, and the upper 48 bits are The signals are supplied in parallel to comparators 61 and 63, respectively. As described above, the latch circuit 58 is supplied with a latch pulse synchronized with the clock immediately after the header detection time, so that the 64-bit data that is inputted immediately before the header detection time by the header detection circuit 54 is transferred to the latch circuit 58. It will be latched when the latch pulse arrives.

Further, the latch circuit 59 is supplied with 64-bit parallel output data from the latch circuit 58 and wraps when the latch pulse from the AND circuit 56 is input.

Therefore, when the header detection circuit 54 detects the first header, the 64-bit shift 1 to register 53 temporarily store the 64-bit data immediately before the detected first header, and the latch circuit 58 temporarily stores the 64-bit data immediately before the detected first header. The 64-bit data immediately before the second header that entered before (in the past) the first header is temporarily stored, and the latch circuit 5
9 is in a state where the 64-bit data format immediately before the third header that entered two times before the first header (in the past) is temporarily stored, and from that state, it is immediately stored in synchronization with the clock GK. The stored contents of the 64-bit shift register 53 are transferred to the latch circuit 58, and the stored contents of the latch circuit 58 are transferred to the latch circuit 59.

On the other hand, the output J signals from comparators 60 and 62 are supplied to comparators 61 and 63. Therefore, the comparators 60 and 61 detect the 16-bit and 64-bit data immediately before the second header detected one step earlier than the first header detected by the header detection circuit 54, and the parallel data of the 64-bit shift register 53. It detects whether the lower 16 bits of the output 64-bit data match the total 64-bit data, and comparators 62 and 63
is the 16-bit and 64-bit data immediately before the third header detected two positions before the first header, and the 64-bit data immediately before the third header detected two times before the first header.
This means that it is detected whether the lower 16 bits of the parallel output 64-bit data of the bit shift register 53 match the data of all 64 bits.

When the values of both input data match, the comparators 60 to 63 output, for example, a high-level match signal. The data selector 64 is supplied with the output signals of the comparators 62 and 63, respectively, and selectively outputs the output signal of the comparator 63 when the select signal from the latch circuit 57 is at a high level, and outputs the output signal of the comparator 62 when the select signal is at a low level. Select and output. Further, the data selector 65 selects the output signal of the comparator 61 when the select signal is at a high level, and selectively outputs the output signal of the comparator 60 when the select signal is at a low level.

That is, when reproducing address data or special function data, the output signals of comparators 60 and 62 indicating whether the 16-bit data immediately before the header match/mismatch are selectively output, while when reproducing character data, the 64-bit data immediately before the header are selectively output. The respective output signals of the comparators 61 and 63 indicating the match or mismatch between the data and the identification signal are outputted.

The exclusive OR circuit 66 is supplied with the respective output signals of the data selectors 64 and 65, and when all three pieces of data to be reproduced subsequently are equal (the comparators 64 and 65
A low level signal is selected and output in both cases (when matching signals are extracted from both) and when they are not equal, and a high level signal is output when two of the three subsequently reproduced data are equal. Outputs a level signal. J
The output signal of the exclusive OR circuit 66 is supplied to the J terminal of the flip-flop 67, the signal from the data selector 72 is supplied to the other terminal of the flip-flop 67, and the AND circuit 73. A signal is output to the load terminal of the counter 68 and the clear terminals of the counters 69 and 70. J-
From the Q output terminal of flip-flop 67 to JG
One clock pulse CK comes in immediately after the a signal becomes high level, and a pulse that becomes high level is taken out from the IC time point.

Counters 68 to 70 do not operate when the output signal of exclusive OR circuit 66 is at low level, but count clock pulses CK when it is at high level. counter 68
supplies the current signal to the data selector 71 and the counter 69 every time the clock pulse CK is counted six times. Further, the counter 69 supplies a signal at a predetermined level to the data selector 72 every time the clock pulse CK is counted nine times.

Further, the counter 70 outputs signals at a predetermined level to the data selectors 71 and 72, respectively, every time the clock pulse CK is applied seven times.

Based on the output signal of the latch circuit 57, the data selectors 71 and 72 selectively output the output signals of the counters 68 and 769 when reproducing character data, and selectively output the output signal of the counter 70 when reproducing special function data or address data. The output signal of the data selector 71 is logically ANDed with the Q output signal of the flip-flop 67 in an AND circuit 73, and then outputted to an output dryer 77 through an OR circuit 74. As a result, the read clock CKO is outputted to the output terminal 77 at a rate of once every six shifts from shift register 52 to 53 in the shift register 52, 53 when reproducing character data, and eight times when reproducing special function data or address data. A read clock is taken out once every time a shift is performed.

On the other hand, the data selector 75 is set to 64 when reproducing character data.
Among the output signals of the bit shift register 53, the data of 6 bits 1 to 1 of the data from the 64th bit (higher 1st bit) stored in the past to the 59th bit is outputted to the output terminals 761 to 766, On the other hand, when reproducing special feature data or address data, the 8-bit data portion, which is half of the 16-bit data from the 16th bit to the 9th bit, of the output signal of the 64-bit shift register 53 is sent to the output terminal 761.
~ Output to 768.

As described above, in this embodiment, when the first two of the three pieces of data to be reproduced are equal, a match signal is taken out from the data selector 65, and when the first and third data are equal, the match signal is taken out from the data selector 64. A matching signal is extracted from the output terminal 77, and in either case, a lead clock signal is output from the output terminal 77. On the other hand, when all three pieces of data are equal or when all three pieces of data are not equal, no read clock is output. If all three pieces of data match, this is because the read clock has already been output before that. In this way, even if there is a dropout, the effect of the dropout can be significantly reduced and correct data output can be achieved.

Next, the playback data output from the output terminals 761 to 768 and the read clock from the output terminals 77 and 78,
An example of the operation of the microcomputer to which the flag pulse is supplied will be explained with reference to the flowchart shown in FIG. 8th
The flowchart shown in the figure shows the processing operation when playing special function data, in which the microcomputer takes in the data obtained as described above (step S1), and separates the header and data of the input special function data (step S2). , separates the 4-bit data immediately after the header and detects whether the first bit is rBJ in hexadecimal notation (steps 83 and 8a).
).

As mentioned above, if the value of the identification signal is special function data,
Since the value is "B", the next time the microcontroller detects the value r13J, the value of the next 16 bits of the header is rBOOlJ.
or rBOO2J <Steps Ss, Ss
). When rBOOlJ, as shown in the table above,
Since it is indicating "start of skip", the microcontroller is VT
R's 81 Another microcontroller for lateral control (called a mechanical controller)
Then, a control signal is sent to the VTR for FF search (high-speed fast forward search) (step Ss). On the other hand, “B
O02'' indicates ``end of skip'', so a control signal is sent to the mechanical controller to set the VTR to play mode (step Sa).

Note that the present invention is not limited to the above-described embodiments, and the number of times the same data is repeatedly recorded may be four or more times, and the number of pieces of data for which matching of the same data is detected may be three or more.

Effects of the Invention As described above, according to the present invention, arbitrary comment (character) information can be processed even though the bit rate is low.

Address information and special function information can be effectively recorded.
Even with playback control pulse dropouts,
Malfunctions caused by this can be significantly reduced, and even if data is erased by mistake when rewriting data, this can be detected by determining the signal between the headers and malfunctions can be prevented, and character information can be replaced with address information. Although the number of bits used is larger than that for special function information, since identification signals are provided before and after the header, it is possible to immediately detect character information not only when fast forwarding but also when rewinding. The detection circuit etc. can be easily configured, and since multiple types of data are selectively recorded on the control track instead of the video signal track, it has many features such as being able to turn on and off the on-screen extremely easily. It is something that you have.

[Brief explanation of drawings]

FIG. 1 is a diagram showing each embodiment of the signal format of data recorded and reproduced by the method of the present invention, FIG. 2 is a diagram showing an embodiment of the recording pattern of a control track recorded according to the present invention, and FIG. The figure is an overall configuration diagram of an example of a recording/playback/playback device that can realize the present invention, FIG. 4 is a block system diagram of an example of the main parts in FIG. 3, and FIGS.
A signal waveform diagram for explaining the operation of the illustrated block system, FIG. 7 is a circuit system diagram showing an embodiment of the main part of the reproduction system of the present invention, and FIG. 8 is an implementation of the processing operation during data reproduction of the present invention. 3 is a flowchart showing an example. 1-1~1-3.3-1~3-2.5-1~5-4...
... Header, 2-1 to 2-3... Address information data, 4-1 to 4-3. 6-1 to 6-4... Identification signal, 7
-1 to 7-3...Special function information data, 11...V
TR112...1 chip microcomputer (microcomputer), 13...read/write circuit, 14...character generator, 16...operation unit for data recording and playback,
18...Keyboard, 21...Monitor TV, 34
...Control head, 50...Reproduction control pulse input terminal, 52.53...Shift register,
57-59... Latch circuit, 60-63... Comparator, 761-768... Playback data output terminal. Patent Applicant: Japan Victor Co., Ltd. Figure 6 - Haruma Proceedings February 3, 1986 Commissioner of the Patent Office Kuro 1) Akio Tono 1゜ Incident Display VTR Data Recording Method and Data Recording Reproduction Method 3; Relationship with person making the amendment f1 Patent applicant address 3-12 Moriya-cho, Kanayō-ku, Yokohama, Kanagawa 221 Name (432) Victor Japan Co., Ltd. Representative Director and President Kunio Kakiki 4, Agent address 〒 102 5-7 Kojimachi, Chiyoda-ku, Tokyo Telephone 03 (2G3> To No. 3271 (Representative) - '6, Detailed description of the invention in the specification subject to amendment. 7. Contents of amendment (1) In the specification , change "19" in line 12 of page 14 to "20"
” he corrected. (rcN of 2, page 19, line 18 and page 20, line 4)
Correct TJ with rcTLJ. ■ Same, page 21, lines 9 to 15 [This playback...
bawl. ] is corrected as follows. [This reproduction control pulse has a period of one frame, and its reference pulse position is the same as the original reproduction position before recording the data, but its duty cycle is such that 1 bit of the recorded data is "1".] The first value (for example, the value where the pulse interval between the positive polarity pulse and the negative polarity pulse is 21.5% of one frame) is obtained, and when 1 bit of the recorded data is "Ol", the second value (for example, When the pulse interval becomes 60% of one frame) and no data is recorded, recording and reproduction are performed so that the duty cycle of the control pulse becomes the second value, which is the same as before.

Claims (2)

[Claims] (1) Appropriately select multiple types of data such as position information on the magnetic tape on which video signals are recorded and played back by the VTR and comments on the recorded information content, and adjust the duty of control pulses at a constant period according to the selected data value. A recording method for a VTR in which data is recorded on a control track of the magnetic tape with a variable cycle, the method comprising: recording the data on the control track of the magnetic tape with a variable cycle, the method comprising: recording data between two adjacent headers of a fixed pattern together with or alone with an identification signal indicating the plurality of types of data; A data recording method for a VTR, characterized in that data of the same content is sequentially recorded on the control track three or more times as a signal format in which the data is arranged. (2) Appropriately select multiple types of data such as position information on the magnetic tape on which video signals are recorded and played back by the VTR and comments on the recorded information content, and adjust the duty of the control pulse at a constant period according to the value of the selected data. A data recording and reproducing method for a VTR in which the data is recorded on a control track of the magnetic tape with a variable cycle, and during reproduction, the data is detected and reproduced from the duty cycle of a reproduction control pulse of the control track, the method comprising: The data is a signal format in which the data is arranged between two adjacent headers of a fixed pattern, together with an identification signal indicating the type of data, or by repeating the same data three or more times as described above. The data is sequentially recorded on the control track, and during playback, the values of the data detected and played back from the playback control pulse are compared, and the values of the data that are successively played back the same number of times as the number of repeated recordings of the same content data are compared, and the same 1. A data recording and reproducing method for a VTR, characterized in that it is configured to reproduce and output two or more data values that have become true data values.