JPS6222257A - Capstan servo circuit of vtr - Google Patents

Abstract

PURPOSE:To keep the continuity of a track phase before and after the editing point by selecting each output of a phase servo circuit and a speed deviation compensating circuit and adding the result to a speed control voltage of the speed servo circuit so as to current the motor speed. CONSTITUTION:The deviation of a pulse number count of an output of a frequency generator fitted to the shaft of a capstan motor 1 within a prescribed period or the time count corresponding to a prescribed pulse number is detected and converted into a voltage by a speed deviation compensation circuit 7. Each output of the circuit 7 and a phase servo circuit 4 is selected by a changeover switch 6 and the result is added to the speed control voltage being an output of the speed servo circuit 2. Thus, the circuit 7 functions complementarily with the circuit 4 when the mode is switched from the reproduction into the recording mode at the editing point at assembly edition so as to keep the continuity of the track phase before and after the edition point.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a capstan servo circuit for a VTR.

[Summary of the invention]

A circuit is added to detect and correct relatively long-period speed drift and constant variations of the capstan motor, and the output of the phase servo circuit operates by referring to the playback signal of the control signal recorded in the longitudinal direction of the tape. This makes it possible to maintain a constant track pitch even when switching from play mode to record mode at an edit point during assembly editing.

[Conventional technology]

FIG. 4 shows a conventionally known capstan servo circuit for a VTR, which has been devised with particular consideration to assembly editing (see the specification of Japanese Patent Publication No. 18805/1983).

In Fig. 4, two-phase (90° phase difference) speed signals FG (A) and FG (B) at 450 Hz, for example, are obtained from a frequency generator attached to the shaft of the capstan motor 1, and the frequency/voltage It is applied to a well-known speed servo circuit 2 having a converter f/v, and the output speed control voltage is supplied as input a to the capstan motor 1 through an summing amplifier 3 to obtain a constant tape speed by loop control.

On the other hand, during playback, the playback signal PB-CTL, which is a control signal (30Hz) recorded in the longitudinal direction of the tape, and the 30Hz reference signal REF, which is also used as a rotation reference for the drum motor, are connected to a phase comparator having a phase comparator φ. Servo circuit 4
The phase error output is added to the speed control voltage from the b input of the summing amplifier 3, and the rotational phase of the capstan motor 1 is controlled so that PB-CTL and REF match.

An FG counter 5 is provided to count the speed signals FG (A) and FC (B), and during recording, a 30 Hz divided output is sent to the phase servo circuit 4 via a changeover switch 6 instead of the playback control signal PB-CTLO. supplying.

When performing assembly editing ASS or splicing, the tape is rewound a little from the editing point, the tape is first put into playback mode, and after the editing point, the tape is switched to recording mode. During playback mode,
When the FC counter 5 is reset (forced synchronization) with the playback control signal PB-CTL, the output of the FG counter 5, which self-resets (self-runs) after the edit point, becomes PB-CTL.
maintains phase information. Therefore, the track pitch is not disturbed discontinuously before and after the editing point.

[Problem that the invention seeks to solve]

The servo circuit in FIG. 4 includes speed signals FG (A), PC;
It is assumed that the frequency of (B) is an integral multiple of PB-CTL (30Hz). Non-integer multiple (with fractions)
In this case, when the FG counter 5 is switched from forced reset by PB-CTL to free running, the 30 Hz output changes to, for example, 31 Hz, making it impossible to maintain track continuity before and after the editing point. This means that the accuracy of the mechanical system included in the servo loop, especially the diameter of the capstan, must be strictly controlled. For example, if the capstan diameter is thicker than the standard, the FG frequency when the tape is running at the standard speed will be smaller, and therefore the divided output from the FG counter 5 will also be smaller than 30 Hz. Similarly, the frequency generator must be highly accurate.

Furthermore, since the phase servo system does not work in the recording mode or assemble mode, there is a problem that the tape speed deviates from the reference value due to variations in capstan diameter, temperature characteristics of the speed servo circuit 2, and changes over time.

In view of this problem, it is an object of the present invention to provide a capstan servo circuit that is compatible with assembly editing and does not require high accuracy in the mechanical system.

Means for Solving Problem c] As shown in FIG.
The speed deviation compensation circuit 7 detects the amount of deviation from a reference value for the pulse number measurement value or the time measurement value corresponding to a predetermined number of pulses and converts it into a voltage. The outputs of the phase servo circuit 4 and the speed deviation compensation circuit 7 are selected by a changeover switch 6 and added to the speed control voltage of the output of the speed servo circuit 2.

[For production]

Corrects long-term drift in motor speed, variations between devices, etc. During assembly editing, when switching from playback to recording at an edit point, the speed deviation compensation circuit functions complementary to the phase servo circuit to maintain continuity of track phases before and after the edit point.

〔Example〕

FIG. 1 shows a capstan servo circuit to which the present invention is applied. In addition to the speed servo circuit 2 and the phase servo circuit 4, a speed deviation compensation circuit 7 is added. This compensation circuit 7 operates during recording, and the speed signal F is output at a relatively long period (several seconds).
The number of pulses of C is counted, and the deviation between the counted value and the reference value is derived as a voltage.

The speed signals FC(A) and FG(B) are multiplied by two by EX-OR8 and counted by FG counter 9.

For example, the counting (gate) section of Karatan 9 is every 2 seconds,
Each time a gate signal is applied to the enable input, a count value is derived to the comparator 10 (or subtracter),
It is compared with the reference value from the reference FG count value generation circuit 11. The error in the comparison result is converted into a voltage value by the D/A converter 12, and after an appropriate offset value is added by the offset circuit 13, it is applied to the summing amplifier 3 as the b input via the REC side of the changeover switch 6. Note that the offset circuit 13 includes a variable resistor VR, functions also as an attenuator, and is also used to adjust the gain of the loop including the deviation compensation circuit 7.

The speed deviation compensation circuit 7 does not have the ability to correct speed fluctuations that are shorter than the rotation period of the capstan, but it does not have the ability to correct speed fluctuations that are shorter than the rotation period of the capstan. It works to compensate for variations and converge to a constant value.

For example, if the FC frequency is 900Hz (2FG),
Since the FG counter 9 counts 1800 pulses in 2 seconds, the 11-bit counter (2048 base) is transferred to the FC counter 9.
used for Deviation detection accuracy is 1/1800 per pulse =
Since it is 0.055%, the speed deviation can generally be kept within ±0.1%.

Note that since the output of the comparator 10 is only the deviation,
The number of bits of the D/A converter 12 may be 5 bits or less.

At the time of assembly editing, as described above, the tape is moved back a little from the editing point, and the selector switch 6 is set to the PB side to temporarily enter the playback mode. Assuming that only the speed servo circuit 2 is functioning in this regeneration mode, the capstan motor 1 will rotate at a constant speed, but depending on variations in the capstan diameter, temperature drift of the speed servo target value, changes over time, etc. The reproduction control signal PB-CTL is deviated from the standard 30Hz. When the phase servo circuit 4 is operated here, the motor speed and rotational phase are adjusted so that the reproduction control signal PB-CTL of 30 Hz can be obtained in phase synchronization with the reference signal REF. By using the servo with reference to this PB-CTL, the tape speed exactly the same as that during recording is reproduced during reproduction.

It should be noted that during recording, tape speed control is performed with the speed deviation compensation circuit 7 functioning, and a control signal is recorded on the side edge of the tape based on the reference signal 30) 1z. In other words, in the playback mode, the phase servo circuit 4 can be considered to be acting as a substitute for the speed deviation compensation circuit 7. On the other hand, in the state where the phase servo is applied, the FG counter 9 of the speed deviation compensation circuit 7 generates, for example, 1800 pulses. It can be considered that the count is equivalent to the standard value with no deviation of /2 seconds. Therefore, even if the changeover switch 6 is switched from the PB side to the REC+ASS side at the assembly editing point, the voltage applied to the capstan motor 1 hardly changes. The inertia of the motor maintains the continuity of the track phase and CTL interval before and after the editing point. After the editing point, the speed deviation compensation circuit 7 functions in place of the phase servo circuit 4 to stabilize the motor speed at a constant value.

As described above, the present invention does not employ the phase synchronization method of forcibly resetting the FG counter 5 with PB-CTL as shown in Fig. 4, so the FC frequency does not need to be a whole number multiple of 30Hz. . Therefore, the degree of freedom in designing the capstan diameter increases, and even small and large variations in diameter can be tolerated. Furthermore, even if the target value of the speed servo system including the speed servo circuit 2 changes due to temperature drift, changes over time, or variations from device to device, these are corrected and a stable tape speed can be obtained.

Note that the microcomputer 15 as shown in FIG.
A C counter + comparator function 16 may be added. This microcomputer 15 is provided with an instant start function 17 that quickly locks the motor speed to a reference value when the capstan motor l starts up.
Functions 16 and 17 are selectively used by selector 18.

Further, as shown in FIG. 3, the FG counter 20
Counting a predetermined number of G pulses, measuring the predetermined number of time intervals using a time measuring circuit 21 based on a clock pulse CK, and comparing this measured value with a reference value from a reference value generating circuit 22 using a comparator 23; The error amount may be derived from the D/A converter 24 to the capstan motor 1 via the changeover switch 6.

Furthermore, in the configuration of FIG. 1, the standard count value of the FG counter 9, for example, 1 soo pulse/2 seconds, is set as the center value of the counter, and the deviation of the actual count value from the center value is determined from the lower digits of the counter. If available, the configuration may be such that it is derived to the D/A converter 12 via a decoder. This configuration eliminates the need for the comparator 10 and the reference FC count value generation circuit 11.

〔Effect of the invention〕

As described above, since the present invention is provided with a speed deviation compensation circuit,
It is possible to stabilize the rotational speed by absorbing relatively long-period drifts in the capstan motor speed, variations among devices, and the like. Further, during assemble editing, the output of the phase servo circuit and the output of the speed deviation compensation circuit can be switched and used to maintain the continuity of the trunk pitch before and after the editing point. Regarding this point, since the conventional counter synchronization type (Figure 4) is not used, the output frequency of the frequency generator does not need to be an integral multiple of the 30Hz regeneration control signal, and The permissible accuracy of the system may be low, and costs can be reduced while improving servo accuracy.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a capstan servo circuit of a VTR to which the present invention is applied, Fig. 2 is a conceptual diagram when the speed deviation compensation circuit of Fig. 1 is configured with a microcomputer, and Fig. 3
The figure is a block diagram showing a modified example of the speed deviation compensation circuit.
The figure is a block diagram of a conventional capstan servo circuit. In addition, in the symbols used in the drawings, 1. Servo circuit 3 - - - - - - - - - Adding amplifier 4 - - - - - - - - One-phase servo circuit 6 - - - --------------------Switch 7------------ One speed deviation compensation circuit.

Claims (1)

[Claims] A speed servo circuit that outputs a speed control voltage for keeping the rotational speed of a capstan motor constant based on the output of a frequency generator, and a constant voltage recorded in the longitudinal direction of the tape as a reference signal during playback. A phase servo circuit that outputs a phase control voltage so that the phase matches the period control signal, and a measured value of the number of pulses within a certain period of the output of the frequency generator or a measured value of time corresponding to a predetermined number of pulses, and a speed deviation compensation circuit that detects the amount of deviation from the reference and converts it into a voltage, and selects each output of the phase servo circuit and the speed deviation compensation circuit with a changeover switch to control the speed of the output of the speed servo circuit. A VTR capstan servo circuit configured to add to the voltage.