JPH0664797B2 - VTR capstan servo circuit - Google Patents

Description

The present invention relates to a capstan servo circuit of a VTR (magnetic recording / reproducing device).

[Outline of Invention]

The capstan servo circuit of the VTR of the present invention is provided with a speed deviation compensating circuit that corrects the tape feed speed by detecting a relatively long cycle speed drift of the capstan motor, a constant error, and the like. During the period in which the capstan motor rises from the stopped state to the constant speed rotation state, the number of samples of the speed information obtained from the speed deviation compensating circuit is controlled to be large, and the gain of the phase loop is set to be high. It is a thing. Therefore, the time to reach the constant speed servo state of the capstan is shortened, and the recording start time can be shortened.

[Conventional technology]

FIG. 3 is a block diagram of a VTR capstan servo circuit (Japanese Patent Application No. 60-162274) proposed by the applicant of the present invention, in which 1 is a capstan motor for controlling tape feeding, and 2 is a capstan motor. Is a frequency-voltage converter (f-V converter) for converting the frequencies of the two-phase pulse signals FG (A) and FG (B) output from the frequency generator detecting the rotation speed of the capstan motor into voltage. ) 3 is an operational amplifier for calculating the speed information of the capstan obtained from the fV converter and the phase information of the capstan, which will be described later, to form the speed control signal of the capstan motor 1. The CTL signal (PB-CTL) recorded on the tape and the reference signal (REF) are compared, and the phase detector 5 that forms phase information of the tape feed is EX-.
An OR circuit, 6 is a switch for switching the reproduction mode-recording mode (assembly recording), and 7 is a speed deviation compensating circuit for supplying phase information to the operational amplifier 3 in the recording mode.
An FG counter 7a that counts the FG signal, a reference count value generation circuit 7b in which a reference count value is set, a comparator 7c that compares the FG counter 7a and the data of the reference count value generation circuit 7b,
It is composed of a D / A converter 7d, an offset circuit 7e, and the like.

According to the servo circuit of the capstan motor configured as described above, the tape is formed by the speed information of the capstan motor 1 output from the fV converter 2 and the phase information output from the phase detector 4 during reproduction. And the tracking control is performed so that the rotary head accurately scans the recording track.

In this case, the speed deviation compensation circuit 7 receives the FG signal EX-
It is doubled by the OR circuit, and the frequency at constant speed is, for example, 9
Since the 00 Hz signal is input to the FG counter 7a and is counted by the gate signal G output every 2 seconds, for example, the count value is 1800.

Therefore, when the reference count value generation circuit 7b is set to 1800, the output of the comparator 7c is 0, which corresponds to a voltage that rotates at a constant speed, that is, an output signal of the phase detector 4 during reproduction. Is set so that such a voltage is output from the offset circuit 7e.

Therefore, even when the selector switch 6 is switched from this reproducing state to perform assembly editing or the like, the pitch of the recording tracks before and after the editing point is not disturbed by the inertia of the motor, and the track pitch during reproduction can be maintained.

Further, since the capstan servo circuit as described above uses a signal having a relatively long cycle as the gate signal G of the FG counter 7a, variations in the capstan diameter and rotation unevenness are corrected by the speed deviation compensating circuit 7. The recording track pitch is not disturbed even if the dimensional accuracy of the capstan is somewhat poor.

In the above-described embodiment, the FG output within a fixed time
Although the speed deviation value is detected based on the count value of the signal, it is also possible to compare the time for counting a predetermined value of the FG signal with the reference time and use the time measurement value as the speed deviation output as phase information.

[Problems to be solved by the invention]

However, the capstan servo circuit described above is FG
When the sample count value of the signal is set to be output at a relatively long interval (2 seconds) so as not to be affected by the rotation irregularity of the capstan, when the recording mode is changed directly from the stopped state of the capstan. Has a problem in that it takes a long time to rise until the constant-speed servo state is reached.

[Means for solving problems]

The present invention, in order to solve such problems, for example,
A circuit for detecting the rotation speed of the capstan is provided.When this detection circuit detects a speed less than a predetermined value, control is performed to increase the number of counting samples that detect the speed deviation, and phase servo is also performed. Increase the gain of the system servo loop to speed up the start-up until steady running.

[Action]

When recording, etc., when the rotation start has a large transient deviation with respect to the control target value, the count value of the FG signal serving as the speed deviation information or the number of samples of the measurement time value can be switched so as to increase. The phase margin of the servo loop used as information is increased, and the gain of the servo loop is set high. Therefore, the time required for the capstan to reach the steady rotation speed can be shortened.

〔Example〕

FIG. 1 is a block diagram for explaining the outline of a VTR capstan servo showing an embodiment of the present invention. 11 is a capstan motor, 12 is an fV converter, and 13 is velocity servo information and phase servo. An operational amplifier to which information is input, 14 is a phase detector that detects a phase difference by comparing a CTL signal and a reference signal (REF) during reproduction, and 15 is EX-O
R circuit, 16 is a switch for switching between reproduction mode and recording mode, 17 is the speed deviation compensation circuit described above, and FG
The counter 17a, the reference count value generating circuit 17b, the comparator 17c, and the D / A converter 17d are provided, and the offset signal can be supplied from the variable resistor VR.

Reference numeral 18 denotes an example of a transfer circuit for selecting the phase information from the phase comparator 14 at the time of reproduction and selecting the deviation signal of the speed deviation compensating circuit 17 at the time of recording and supplying it to the operational amplifier. differential amplifier 18b constituting the integrator circuitry _{(r 0 r 1 r 2,} c 1) the differential amplifier 18a and capacitor _{C 2} for phase lag compensation by the resistors _{r 4,} R 0, the _{R 1} and the time constant Etc.

Reference numeral 20 denotes a speed detector that detects the number of revolutions of the capstan. This speed detector 20 is a gain when the number of revolutions is a predetermined number or less in the recording mode (at the time of rising),
The gain of the transfer circuit 18 is increased by controlling the switch 18c that switches the integration constant, and the gate time and F
The G count value setting circuit 21 is controlled to increase the number of samples of the count value output from the FG counter 17a.

Since the capstan servo circuit of the VTR of the present invention is configured as described above, the speed information output from the fV converter 12 at the time of reproduction and the CTL as described above.
The output of the phase detector 14 which detects the phase difference between the signal and the reference signal (REF) is controlled by the phase compensation circuit of the transmission circuit 18, the PB contact of the switch 16 and the integrator to control the capstan motor 11 as phase information. It is output as a signal and acts to track the rotary head.

Also, in this reproducing state, the FG pulse counted by the FG counter 17a is compared with the reference FG count value, and the difference output is supplied from the D / A converter 17d to the NOR contact of the switch 18c as speed deviation information. There is.

Therefore, even when the selector switch 16 is set to the recording mode and assembly editing is performed as seen in the above-mentioned prior art, the recording track pitch before and after the edit switching point is not disturbed.

By the way, when the recording mode is changed from the state in which the magnetic tape is stopped, it is required that the rising time until the capstan motor 11 becomes a constant speed running is short, but in the capstan servo circuit of this system, Since the number of count data output from the FG counter 17a of the speed deviation compensating circuit 17 per time is small, the time constant of the integrator of the transmission circuit is set large. Therefore, the indental response of the capstan motor is poor, and it takes a long time to rise to the constant speed state.

However, in the case of the present invention, the switch 18c is used when the speed detector 20 which detects the number of revolutions of the capstan motor is counting, for example, the speed state below a predetermined value.
Switch and connect the contact to the ST side as shown in the figure,
The resistance value is switched to R ₀ to reduce the integration time constant and to increase the loop gain.

Further, the setting circuit 21 is switched by the output of the speed detector to increase the gate interval to, for example, about 30 Hz, and the count value at which the FG signal is counted at 30 Hz at a constant speed is loaded into the reference count value generating circuit 17b.

Therefore, during the period in which the capstan motor rises from the stopped state to the vicinity of the constant speed rotation speed, the speed deviation compensation circuit 17
Is controlled so that, for example, the speed deviation information is output at intervals of 1/30 seconds and the loop gain of the transmission circuit is also increased. It can be shortened more.

Needless to say, after the capstan motor 11 approaches the speed in the constant speed state, the detection signal of the speed detector 20 disappears and the original servo state is restored.

As shown in FIG. 2, the speed deviation compensating circuit 17 includes a counter 17e that counts a high-speed clock Φ and a frequency divider circuit 17f that divides the FG signal to reset the counter 17e. The time measurement value corresponding to the number of pulses is output, and the standard time measurement value at this time is input to the output of the reference time generation circuit 17g and the comparator 17
The speed deviation information may be obtained by comparing with c.

With such a circuit configuration, at the time of rising, it becomes possible to count the fast clock Φ for each FG pulse divided into 1 / N and measure the rotation speed of the capstan with high frequency. The number of velocity deviation samples can be easily increased.

As described in the prior art, the speed deviation compensating circuit 17 is a CPU that controls the system of the VTR.
Can be embodied by

Further, it goes without saying that the transmission circuit 18 is not limited to that shown in FIG. 1 and may have another circuit configuration as long as it can control the loop gain.

〔The invention's effect〕

As described above, the VTR capstan servo circuit of the present invention prevents the track pitch from being disturbed before and after the edit point in the assembly editing by using the speed compensating circuit as the phase servo system at the time of recording. It is possible to absorb variations in accuracy and drift in temperature characteristics of the circuit. Furthermore, when the capstan motor rises, the output interval of the count sample value output from the speed compensation circuit is controlled to be small,
Since the loop gain of the phase servo system is made high, there is an effect that the rise of the capstan to the constant speed rotation is shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of a VTR capstan servo circuit showing an embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of a speed compensation circuit, and FIG. 3 is a prior art of the present invention. It is a block diagram. In the figure, 11 is a capstan motor, 12 is a frequency voltage converter, 13 is an operational amplifier, 14 is a phase detector, and 15 is E.
X-OR circuit, 16 switch, 17 speed compensation circuit, 18 transmission circuit, 20 speed detector, 21
Indicates a setting circuit.

Claims (1)

[Claims] 1. A speed servo circuit for outputting a speed voltage for controlling the rotation speed of a capstan motor based on the output of a frequency generator, a reference signal at the time of reproduction, and a control signal of a constant cycle recorded in the longitudinal direction of the tape. Based on a phase servo circuit that outputs a phase control voltage such that the phases of the two coincide with each other, and a pulse count measurement value within a certain period of the output of the frequency generator, or a time measurement value corresponding to a predetermined pulse count, a reference value And a speed deviation compensating circuit for detecting the deviation from the voltage deviation and converting the voltage to a voltage, and selectively switching each output of the phase servo circuit and the speed deviation compensating circuit at the time of reproduction and at the time of recording to output the speed servo circuit. Configured to add to
In the TR capstan servo circuit, at the start of recording, the sampling cycle of the pulse number measurement value or the time measurement value generated in the speed deviation compensating circuit is shortened and the loop gain of the phase servo loop is increased. A VTR capstan servo circuit characterized in that