JPS62220398A - Integrated circuit card - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an IC card, such as EEPRO.
The present invention relates to a technology that is effective when applied to an IC card equipped with M (Electrically Erasable Programmable Read Only Memory) and a CPU (Central Processing Unit).

[Prior art]

Today, various cards for identifying personal information, such as ID cards, credit cards, and cash cards, are in widespread use. Applied handbook J
As described in P498 and P2O3, it consists of a magnetic card with a magnetic stripe that can store about 54 digits of data, and the information it can store is limited. Also,
Therefore, the PIN code was simple and there was a problem in terms of ensuring the security of personal information. Therefore, in order to increase storage capacity and enable complex password codes, a card made of resin or the like with a standardized shape is equipped with a storage circuit such as a rewritable read-only memory such as EEFROM and a control system that controls it. An IC (Integrated Circuit) card equipped with a CPU as a circuit was proposed.

Consideration is being given to replacing them with passbooks and health certificates.

[Problem that the invention seeks to solve]

When the present inventors studied an IC card equipped with a CPU and an EEPROM, the CPU and EEPROM
If a power supply voltage is supplied to the PROM from a common external power supply terminal at the same timing, the CPU may output an uncertain signal during the initialization reset period, and this uncertain signal may cause the EEPROM to enter data write mode. It has been found that this may cause the stored data to be erroneously rewritten.

An object of the present invention is to contribute to prevention of malfunction of a storage circuit due to an uncertain signal output from a control circuit.
The purpose is to provide C cards.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in the Icefields is as follows.

In other words, the EEPROM and the CPU that controls it.
An external power supply terminal for supplying power supply voltage to each of the two is separately provided.

[For production]

According to the above-mentioned means, in a circuit that receives and processes an IC card, it becomes possible to supply the power supply voltage to the EEPROM at the timing when the initialization reset of the CPU is completed, and thereby, the power supply voltage is output from the CPU. This prevents EEPROM from malfunctioning due to uncertain signals.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of an IC card according to the present invention.

Although the IC card shown in the figure is not particularly limited, an EEPROM chip 1 as a memory circuit and a CPU chip 2 as a control circuit for controlling it are mounted on a resin card board 3 with standardized dimensions. It is installed so that it can be buried in. EEPROM chip 1 and CPU chip 2
are interconnected by signal lines 4 for transmitting and receiving address signals, data signals, and control signals.

Although the EEPROM chip 1 is not shown in detail, it has a built-in booster circuit for obtaining a high voltage necessary for rewriting data, and can operate with the same power supply voltage as the CPU chip 2. .

In addition, the CPU chip 2 not only has a function as an arithmetic control device having an arithmetic circuit, a control circuit, a register, etc. (not shown), but also has a serial input/output interface (not shown) that enables input/output of serial data. , which has a configuration that can be replaced with a so-called microcomputer.

Normally, an IC card has eight external terminals that can be connected to a processing circuit that receives and processes the card, according to the International Standard (IS) of the International Organization for Standardization (ISO), but is not particularly limited. , in this example, C
A clock terminal CLK supplies a reference clock signal to the PU chip 2, a reset terminal RST supplies a reset signal to the CPU chip 2, and inputs/outputs necessary data with the serial input/output interface (not shown) of the CPU chip 2. It has a data input/output terminal I10, a ground terminal GRD that supplies the circuit ground potential to the EEPROM chip 1 and the CPU chip 2, respectively, and two reserve terminals RFU in preparation for future functional expansion. a first fft source terminal vcc1 that supplies
A second power supply terminal V that supplies power supply voltage to the ROM chip 1
Cc, and are individually provided.

A processing circuit (not shown) that receives and processes such an IC card has internal terminals that can be connected to the various external terminals of the IC card described above.
When the U chip 2 and the EEPROM chip 1 are each provided with power supply terminals vcc1 and Vcc2 individually, the power supply voltage is applied to the EEPROM chip 1 at the timing when the power supply voltage is applied to the CPU chip 2 and its initialization reset is completed. For example, as shown in FIG. 2, power supply voltage is supplied to the CPU chip 2 via the first power supply terminal vCC1 at time t1, and the CPU
At time t2 after the initialization reset in chip 2 is completed, the second i! ! ! A power supply voltage can be supplied to the EEPROM chip 1 through the source terminal vCC2. Therefore, during the initialization reset period of the CPU chip 2, an uncertain signal output from the same chip 2 to the EEPROM chip 1 causes the EEPROM chip 1 to be This reliably prevents malfunctions such as erroneously rewriting or erasing stored data. Regarding the operation of stopping the supply of the power supply voltage, as shown in FIG.
By making such control possible, the EEPROM chip 1 is prevented from malfunctioning due to the influence of uncertain signals output from the PU chip 2 when the ffi source is disconnected. .

According to the embodiment described above, the following effects can be obtained.

(1) C: Since the PU chip 2 and the EEPROM chip 1 are individually equipped with power supply terminals Vcc1 and Vcc, the processing circuit (not shown) that receives and processes the IC card is connected to the CPU chip. It becomes possible to control the power supply voltage to be supplied to the EEPROM chip 1 at the timing when the power supply voltage is supplied to the EEPROM chip 2 and the initialization reset is completed.
This makes it possible to control the EEPROM chip 1, thereby preventing the IC card from accidentally rewriting or erasing stored data in the EEPROM chip 1 due to an uncertain signal output from the CPU chip 2 to the EEPROM chip 1. This can contribute to preventing malfunctions such as

(2) The above effect can be obtained by a structure in which the power terminals of the CPU chip 2 and EEPROM chip 1 are separated from each other, so there is no need to increase the number of semiconductor chips to be mounted on the card board 3, and the structure can be made extremely simple. can be maintained. If a configuration is adopted in which a new sequential circuit is provided in which the power supply terminals of the CPU chip 2 and the EEPROM chip 1 are made common and the timing of supplying power supply voltage to each other is staggered, a new semiconductor forming the sequential circuit is used. Due to the nature of IC cards, which are mainly based on card substrates that require a chip, are used in a relatively poor operating environment in terms of mechanical stress, etc., and are limited in terms of shape and strength, such semiconductor chips are If a new IC card is needed, the reliability of the IC card itself will drop significantly.

(3) The external power supply terminal of the IC card includes two spare terminals according to international standards, and the EP card does not have an internal booster circuit.
ROM (Electrically Programmable Read
In the case of an IC card equipped with a memory (only memory), the terminal Vpp that supplies the power voltage to the EPROM is standardized separately from the terminal Vcc that supplies the power voltage to the CPU due to its nature. The second power supply terminal V in the example
If QC is provided at a position corresponding to the terminal Vpp or the spare terminal, there is no need to increase the total number of external terminals in the IC card, and the number of external terminals can be maintained within the current standard range.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. For example, the first
The types of external terminals other than the power supply terminal and the second power supply terminal are not limited to the above embodiments, and can be variously changed depending on the nature and purpose of the IC card.

The above explanation will mainly focus on the fields of application made by the present inventor, namely EEPROM and CP.
Although the case where it is applied to an IC card equipped with U is described, it is not limited thereto.
E P ROM memory cell transistor and MO8SR
NVRAM (
It can be applied to IC cards equipped with non-volatile memory including a booster circuit such as non-volatile random access memory (non-volatile random access memory).

The configuration using a combination of functionally separated independent chips such as the CPU chip and the EEPROM chip as in the embodiment makes it easy to change the internal data processing method and the storage capacity. From these points, it is easy to realize IC cards with various configurations. In this case, even if special additional parts are not installed in the IC card to prevent malfunction, the
Malfunctions of rewritable semi-volatile non-volatile memories such as EI'ROM can be prevented. However, the present invention is also applicable to cases where the CPU and semiconductor memory are formed on one semiconductor chip. In that case, the protection of the nonvolatile memory may be further strengthened by providing two power supply terminals as in the embodiment and further forming an appropriate protection circuit on the semiconductor chip. For example, a power switch consisting of a MOSFET connected in series to the power supply line of a semiconductor non-volatile memory, and a power switch that detects power-on to a CPU and waits until a predetermined period of time has elapsed from power-on or when it is in a normal operating state. It can be comprised of a power-on detection circuit or a power sequence control circuit that prohibits the power switch from being turned on until a time determined by the CPU. Together with or independently of the above, the CI'U
A gate circuit may be provided to force a control signal, such as a write control signal, supplied from the memory to the semiconductor nonvolatile memory to a non-write level for a predetermined period after power is turned on to the CPU.

The present invention is applicable to at least a device in which external power supply terminals for supplying power supply voltage to a control circuit and a memory circuit that can operate with the same power supply voltage are provided individually.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, since external power supply terminals for supplying power supply voltage to the CPU and EEPROM, which can operate with the same power supply voltage, are provided separately, the circuit that receives and processes the IC card is provided with separate external power supply terminals for supplying power supply voltage to the CPU and EEPROM, which can operate at the same power supply voltage.

It becomes possible to apply the power supply voltage to the EEPROM chip at the timing when the initialization reset of the CPU is completed, thereby contributing to the prevention of malfunction of the EEPROM due to an uncertain signal output from the CPU.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of an IC card according to the present invention, and FIG. 2 is a time chart showing the timing of turning on and cutting off the power supply voltage in the IC card of the embodiment. 1...EEPROM chip, 2...CPU chip,
3...Card board, Vccl...1st power supply terminal,
Vcc, . . . second power supply terminal. Figure 1 Figure 2 VCC2-87g&4P

Claims (3)

[Claims] 1. An IC card in which a nonvolatile memory circuit and a control circuit for controlling the nonvolatile memory circuit are mounted on the card, and external power terminals for supplying power supply voltage to the control circuit and the memory circuit are each provided individually. An IC card that is characterized by 2. 2. The IC card according to claim 1, wherein the memory circuit is a memory chip equipped with a booster circuit that boosts the power supply voltage. 3. 3. The IC card according to claim 1, wherein the control circuit is a CPU chip.