JPS62219389A - Recording and reproducing device - Google Patents

Abstract

PURPOSE:To perform the fast writing or reading operation of a memory without any absence of information by adding the 2nd storage element. CONSTITUTION:This recording and reproducing device consists of a field memory 9, a switch 8, a shift register (2nd storage element) 7, an address generating circuit 4, and a switch control circuit 12. Data DL+1, DL+2...DL+6 appear at a terminal 8a of a switch 8 at time points tn, tn+2...tn+10 and data DL-1, DL+2...LL+4 which are delayed by two clocks through the shift register appear at a terminal 8b of said switch 8; and two clocks are required to set a row address Rm, so the switch 8 is switched from the terminal 8a to the terminal 8b at time tn+4 to obtain input information shown in figure (h) at the information input terminal of a field memory 9. Thus, the input information is written in the field memory; 9 without any absence in the middle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a recording/reproducing device, and particularly to an improvement in recording and reproducing digital information using a memory.

[Conventional technology]

In conventional memories, dynamic memories, for example, have an operation called page mode as a method for executing write or read operations at high speed.

An example of this page mode is shown in FIG. In FIG. 3, (al) is a row address strobe signal that latches the address in the row direction, and (b) is the column address strobe signal C that latches the address in the column direction.
(C) of the same figure shows the address signal d of the memory.

In page mode operation, first, Rm of the row address
is set in the memory by the falling edge of the row address strobe signal, and then the value Cn + of the column address
C, l+l + Cn+z + ..., ca
By setting the value sk at the falling edge of the corresponding column address strobe signal, it is possible to write information to or read information from the memory. By repeatedly executing this page mode, memory can be used quickly.

[Problem that the invention seeks to solve]

However, since this page mode operates only within a certain period of time, for example, in order to process information for one horizontal period of a video signal, it is necessary to repeat the page mode continuously. In this case, since the storage operation is interrupted during the period when the row address is reset, there is a problem that information is lost.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a recording/reproducing device that can eliminate signal loss when a storage operation is interrupted by resetting an address.

[Means for solving problems]

The recording/reproducing device according to the present invention is provided with a second storage element in addition to the memory for storing digital information, and after the address resetting operation of the memory, information input or output from the memory is stored in the second storage element. This is obtained from the output of .

[Effect]

In the present invention, since the second storage element temporarily stores the information on the input or output of the memory after the address is reset, the omission of the information on the input or output of the memory is eliminated.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a recording/reproducing device according to an embodiment of the present invention,
Here, the memory for special reproduction that is built into the VTR is shown. In the figure, 1 (magnetic tape,
2 is a magnetic head, 3 is an amplifier, 4 is a video signal processing circuit, 5 is a switch, and 6 is an A/D converter. Analog image information read from the magnetic tape 1 via the magnetic head 2 is amplified by the amplifier 3. The amplified analog information is subjected to signal processing in a video signal processing circuit 4, and then to a switch 5 for switching between the output of the field memory and the information directly read from the head 1, and for sampling and quantization. The signals are sent to the A/D converter 6 to be executed. Also 7
8 is a shift register that delays digital information by a certain amount of time; 8 is a switch that sends either the output from the A/D converter 6 or the output of the shift register 7 to a subsequent stage; and 9 is a field memory that stores information for one screen. , 10 converts the output of the field memory 9 into analog image information 40
11 is an output terminal. or,
12 is a switch control circuit that generates a switching signal 13 for switching the switch 8; 14 is an address generation circuit that generates an address for the field memory 9; and 15 is an A
/D converter 6° shift register 7, field memory 9. D/A converter 10. Switch control circuit 12.
A control circuit 16 controls the address generation circuit 14, and an oscillator 16 generates a clock for operating the control circuit 15.

Note that the recording/reproducing device of this embodiment uses the field memory 9 described above.
．． Switch 8. Shift register (second note 4g element) 7
．． Address generation circuit 14. It is composed of a switch control circuit 12.

FIG. 2 explains the write operation of the circuit of FIG. 1, which is an embodiment of the present invention. In Figure 2,
Figure 1 (a) shows a clock a that operates the control circuit in Figure 1.
This clock causes switching signal 1 in FIG.
3 and other control signals are generated. 2(b) shows a row address strobe signal for latching the address in the row direction of the field memory 9, and FIG. 2(C) shows a column address strobe signal for latching the address in the column direction of the field memory 9. C, and FIG. 3(d) show the address d of the field memory 9, Cn is the column address of the value n, and Rm is the row address of the value m.

1(e) shows the information e at the terminal 8a of the switch 8 in FIG. 1, and FIG. 1(f) shows the information f at the terminal 8b of the switch 8 in FIG. 1, that is, the output of the shift register 7. 2(e) and (f) are the switching signal 1.
When 3 is at low level, switch 8 is connected to terminal 8a side,
Conversely, when the switching signal 13 is at a high level, the switch 8 is switched to the terminal 8b.
The data shows the case when it is connected to the side. However, in this embodiment, it is assumed that the shift register 7 is composed of two stages (2 bits) of flip-flops. Also, D! shall represent the first input information. FIG. 1(g) shows the switching signal 13 of the switch 8 in FIG. Further, in the same figure (hl indicates information at the input end of the field memory 9, and (1) in the same figure indicates information written to the latch of the field memory 9.

Next, the operation will be explained. At time t2, address strobe signal C rises in synchronization with the rise of clock a, and in synchronization with the fall of strobe signal C at time jn-1, column address Cn is set in the memory, and data is stored at this address. Di is latched.

Next, at time tn, the row address strobe (i %
b stands up and time is up. , 2, when the row address strobe signal S falls, the next page mode is started, and the row address Rm is first set in the memory. And time t7゜S + tn*”r + t+, +
9 +tia. 4. Column address CIl+l +
Cn+2 +C1143* Cn+41...
are set in memory sequentially.

During this time, time tn+Ell-2+...,
At jr+*lo, data DLOI I DL + 12 + D 2 + DL + 41 D S, DL + 6 appears at the terminal 8 a of the switch 8, and data Dt-t delayed by 2 clocks and 7 clocks by the shift register appears at the terminal 8 b of the same switch 8. l DL 1DL◆I + DL+z
+ Dt+z + DL+4 appears. Since it takes two clocks to set the row address Rm as described above, by switching the switch 8 from the terminal 8a to the terminal 8b side at time t, %, the result shown in FIG. At the information input terminal of the field memory 9, the input information is as shown in FIG. 2(h). From the above, field memory 9 in Figure 1
As shown in FIG. 2 (il), it is possible to write input information without missing it in the middle.

In the above embodiment, the address resetting operation takes two clocks, but this time can be set arbitrarily, and the switching signal can be written at any time when the signal can be written into the memory without any loss.

Furthermore, the second storage element is not limited to flip-flops and registers, but may be any commonly used semiconductor memory or delay element, as long as it has a function of delaying a signal by a necessary amount of time.

Further, the circuit from the output end of the A/D converter 4 in FIG. 1 to the input end of the field memory 9 may be composed of two or more elements having a memory function or a delay function, as shown in FIG. 4. In FIG. 4, 17 and 18 are delay elements each having a function of delaying a signal by a necessary time.

Furthermore, although the above embodiment shows that the second storage element is provided on the input side of the memory, it is possible to compensate for the loss of read information by applying it not only to the input side but also to the output side. .

〔Effect of the invention〕

As described above, according to the recording/reproducing device according to the present invention, by adding the second storage element, high-speed memory writing or reading operations can be performed without causing information loss, and in particular, It has a remarkable effect on high-speed, continuous information like a VTR.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a time chart diagram showing an example of the operation of the device shown in FIG. 1, FIG. 3 is an explanatory diagram of the memory page mode, and FIG. FIG. 7 is a diagram showing another embodiment of the invention. In the figure, 9 is a field memory, 7 is a shift register (second storage element), 8 is a switch, 14 is an address generation circuit, 12 is a switch control circuit, and 17 and 18 are delay elements (second storage element). be.

Claims (1)

[Claims] (1) In a device that stores digital information in a memory and reads out the stored information as necessary, when resetting the address of the memory while writing to or reading from the memory, the address associated with the resetting A recording/reproducing device comprising a second storage element for interpolating a lack of written information or a lack of continuity of read information due to interruption of writing or reading from the memory.