JPS62219049A - Out data timing coincidence circuit - Google Patents

Abstract

PURPOSE:To associate the timing when two piece of out data from both devices is outputted by simultaneously outputting data from both devices only when both character pattern generators generate signals showing the validity of data. CONSTITUTION:When a data valid signal DV2 in the character pattern generator 17 becomes active after a data valid signal DV1 in the character pattern generator 16 becomes active, at a point B where the signal DV1 becomes active the outputs of a NOR gate 11 and OR gate 14 are at a low level with an AND gate 12 closed, and a clock CLK1 is not supplied to the generator 16. On the other hand, the output of an OR gate 15 is at a high level with an AND circuit 13 open, and a clock CLK2 is supplied to the generator 17. The point when the clock CLK1 is supplied to the generator 16 is a point C where both signals DV1 and DV2 become active, and hence onward a piece of data are outputted at the same timing from both character pattern generators 16 and 17.

Description

[Detailed Description of the Invention] [Summary] In a duplex device that outputs a signal indicating the validity of data when data is held in an output buffer and then outputs data when a clock is applied, the first A gate means is provided to generate an output when both devices output a signal indicating the validity of data, and a second gate means is provided corresponding to both devices to output the output of the first gate means or the own device. When a signal indicating the validity of data is output, the clock is passed and applied to the device itself, so that the timing of out data of both devices is made to match. be able to.

[Industrial application field]

The present invention relates to a circuit for matching the timing of out data, and particularly in a duplex character pattern generation device, etc., by applying a clock pulse to both devices when the output signals from both devices match. This invention relates to an out-data timing circuit that matches the timing of data.

In order to increase the reliability of character pattern generators, etc., these are sometimes used in duplicate and the occurrence of errors is verified by matching the at data, but in this case, the timing of out data in both university pattern generators is always the same. It is necessary that they match.

[Conventional technology]

Conventionally, character pattern generating devices using mask ROMs and the like have rarely been used in duplicate, and therefore no consideration has been given to matching the timing of the output data.

[Problem that the invention seeks to solve]

FIG. 4 shows a character pattern generating device to which the present invention is applicable. In the figure, an address decoder 1 decodes an externally applied address signal and supplies it to a cell array 2 storing character patterns. At this time, the timing circuit 3 receives an output enable signal A from the outside.
A timing signal for decoding is supplied to the address decoder 1 in accordance with E. The character pattern data read out from the cell array 2 is sent to the timing circuit 3.
The data latch 4 is latched in response to a timing signal from the data latch 4, and its output is further held in the output buffer 5.

The timing circuit 6 generates a data valid signal DV indicating that the data in the output buffer 5 is valid in accordance with the timing signal of the timing circuit 3, and further generates a clock signal CLK from the outside when this signal is generated.
An output clock is applied to the output buffer 5 in accordance with the output clock, and data is thereby output from the output buffer.

When such character pattern generators are duplicated,
Even if the same address is given, the operation timings of both devices are different, so the timing of the data valid signal is different, and even if the same clock is given, the output data may not match, which is a problem.

[Means for solving problems]

In a duplex device that outputs a signal indicating the validity of data when data is held in an output buffer, and then outputs the data when a clock is applied, each of Provide means.

Reference numeral 101 denotes a first gate means, which generates an output when both of the above devices generate a signal indicating data validity.

Reference numerals 102 and 103 indicate second gate means, which are provided corresponding to each device and which are connected to the first gate means (101).
) is generated, or when a signal indicating data validity is generated from the own device, the clock is passed and output to the own device.

[For production]

When one device generates a signal indicating data validity and the other device does not generate a signal, the device generating the signal will not receive a clock and therefore will not output data. I can't.

When a signal indicating data validity is generated from both devices, a clock is applied to both devices at the same time and data is output, so the timing of out data coincides.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the present invention, in which 11 is a NOR gate, 12.13 is an AND gate, 14.15 is an OR gate, and 16.17 are first and second character pattern generators, respectively.

Further, FIG. 3 shows the timing of each part signal in the circuit of FIG. 2, and explains the operation of the circuit of the present invention.

In the figure, DVI and DV2 are data valid signals of the character pattern generators 16 and 17, respectively, and when they become low level, the output data of the respective character pattern generators becomes active. CLKl, CLK2
are external clocks supplied to the character pattern generators 16 and 17, respectively, and data is output from each output buffer L'7 corresponding to the pulse width.

Now, as shown in FIG. 3 (al), before the data valid signal DVI of the first character pattern generator 16 becomes active, the data valid signal DV2 of the second character pattern generator 17 becomes active at point A. When this happens, the outputs of the NOR gate 11 and the OR gate 15 are at a low level, so the AND gate 13 is closed and the clock CLK2 is not supplied to the character pattern generator 17. On the other hand, the output of the OR gate 14 is at a high level. , therefore, the AND gate 12 is open and the clock CLK1 to the character pattern generator 16 is supplied at point A. The clock CLK2 to the character pattern generator 17 is supplied by the data valid signal D.
V1. This is point B where both DV2 became active,
From this point onwards, from both character pattern generators 16.17,
Data with matching timing is output.

As shown in FIG. 3), when the timings at which the data valid signals DVI and DV2 of both character pattern generators become active coincide, the output of the NOR gate 11 and the OR gate 14.15 is at a high level. Ant games 1-12 and 13 are open, and the clock CLK is applied to the character pattern generation value ff116.17 at point B.
I and CLK2 are supplied, and from this point on, both character pattern generators 16 and 17 output data with matching timing.

As shown in FIG. 3(C), the character pattern generator 16
After the data valid signal DVI of the character pattern generator 17 becomes active, the data valid signal DV of the character pattern generator 17 becomes active.
2 becomes active, the data valid signal D
At point B where VI became active, Noah Gate】1,
The output of OR gate 14 is low level and AND gate 12
is closed and no clock CLK I is supplied to the character pattern generator I6. On the other hand, or gate 15
The output of is high level, the AND circuit 13 is open and 1, and the clock CLK for the character pattern generator 17 is
2 is supplied. The clock CLK1 is supplied to the character pattern generator 16 at the 0 point when both the data valid signals DVI and DV2 become active, and from this point on, both character pattern generators 16 and 17 detect timing coincidence. The data will be output.

In this way, in the circuit of the present invention, when the data valid signals in both character pattern generators are not generated simultaneously, the character pattern generator on the side to which the data valid signal is output has a clock for reading the output buffer. is not supplied, and the clock is supplied to both devices only when the data valid signals of both devices are aligned, and the timing of data output from both devices coincides.

〔Effect of the invention〕

As explained above, according to the present invention, data is simultaneously output from both devices only when both devices generate a signal indicating that data is valid, so it is possible to match the timing of out data of both devices. I can do it.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the invention, Fig. 3 is a time chart showing various signals in the circuit of Fig. 2, and Fig. 4 is a diagram showing the configuration of an embodiment of the present invention. 1 is a diagram showing a character pattern generator. 11...Noah Gate 12, 13...And Gate 14, 15...Or Gate 16, 17...Character pattern generator patent applicant
Fujitsu Co., Ltd. Agent Patent Attorney Hisashi Tamamushi Gobu (1 other person) Figure 1 showing the principle of the present invention f:J configuration Figure 1 Figure 1 showing one implementation of the present invention! Figure 3 is a time chart showing various evil signals in the circuit shown in Figure 2.

Claims (1)

[Claims] In a duplex device that outputs a signal indicating the validity of data when data is held in an output buffer, and then outputs the data when a clock is applied, both devices output the signal. a first gate means (101) that generates an output when the first gate means (101) or a signal of the device is output, and a second gate that passes a clock for the device when the output of the first gate means (101) or the signal of the device is output. An out data timing matching circuit characterized in that means (102, 103) are provided corresponding to each device.