JPS62217675A - Manufacture of surface light emitting diode - Google Patents
Manufacture of surface light emitting diodeInfo
- Publication number
- JPS62217675A JPS62217675A JP61059392A JP5939286A JPS62217675A JP S62217675 A JPS62217675 A JP S62217675A JP 61059392 A JP61059392 A JP 61059392A JP 5939286 A JP5939286 A JP 5939286A JP S62217675 A JPS62217675 A JP S62217675A
- Authority
- JP
- Japan
- Prior art keywords
- type
- film
- emitting diode
- active layer
- dry etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000001312 dry etching Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000010931 gold Substances 0.000 claims abstract description 17
- 229910052737 gold Inorganic materials 0.000 claims abstract description 17
- 238000007747 plating Methods 0.000 claims abstract description 11
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 27
- 238000005530 etching Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 238000000059 patterning Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、光通信、光情報処理等における光源として用
いられる面発光ダイオードの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a surface emitting diode used as a light source in optical communication, optical information processing, etc.
面発光ダイオードは、発光ダイオードのファイバー結合
パワーを向上するために円形メサ型にするとよいことが
知られている。このメサ型面発光ダイオードは、円形の
メサの上面に電極を形成している。It is known that surface emitting diodes can be formed into a circular mesa shape to improve the fiber coupling power of the light emitting diode. This mesa-type surface-emitting diode has an electrode formed on the top surface of a circular mesa.
このことは例えば「電子通信学会技術報告書」８４巻２
５９号０ＱＥ８４の１５頁から２０頁の論文や、米国雑
誌エレクトロニクス・レターズ（Ｅｌｅｃｔｒｏｎｉｃ
ｓＬｅｔｔｅｒｓ） ２１巻１５号４１８頁から４１９
頁の論文に説明されている。This can be seen, for example, in the ``Technical Report of the Institute of Electronics and Communication Engineers,'' Vol. 84, 2.
59 No. 0QE84, pages 15 to 20, and the American magazine Electronics Letters.
sLetters) Volume 21, No. 15, pages 418-419
It is explained in the paper on p.
従来の円形メサ型発光ダイオード（ＬＥＤ）を製造する
場合、半導体層をメサエッチングした後、ＳｉＯ□ （
酸化ケイ素）膜を形成し、次にフォトレジストによりメ
サ上面のＳ ｉ Ｏｚ膜を除去し、そこにｐ型電極を形
成している。When manufacturing a conventional circular mesa light emitting diode (LED), after mesa etching the semiconductor layer, SiO□ (
A silicon oxide film is formed, and then the SiOz film on the upper surface of the mesa is removed using photoresist, and a p-type electrode is formed there.
しかし、この方法において、円形のメサ上面のＳｉｎ、
膜をフォトレジストできれいに残りなくメサ上面だけ除
去するには、高精度のパターニングが必要であった。そ
の結果、このパターニングによる不良が起こりやすく、
メサ型発光ダイオードの特性が悪化し歩留りが下がると
いう問題があった。However, in this method, Sin on the top surface of the circular mesa,
High-precision patterning was required to remove only the top surface of the mesa using photoresist. As a result, defects due to this patterning are likely to occur,
There was a problem in that the characteristics of the mesa-type light emitting diode deteriorated and the yield decreased.
本発明の目的は、この電極形成時の工程を改良し、円形
メサ型発光ダイオードの特性を良好に保持すると共に電
極を歩留り良く形成できる面発光ダイ゛オードを提供す
ることにある。An object of the present invention is to provide a surface light emitting diode which can improve the process of forming electrodes, maintain the characteristics of a circular mesa light emitting diode well, and form electrodes with a high yield.
本発明の製造方法は、活性層を含む半導体層上に円形の
電極を形成する工程と、前記円形の電極の外側の輪状の
領域を除いてドライエツチング用のマスクを形成する工
程と、前記輪状の領域の下の前記半導体層を少なくとも
活性石を貫通するまでドライエツチングで除去する工程
を含むことを特徴とする。The manufacturing method of the present invention includes a step of forming a circular electrode on a semiconductor layer including an active layer, a step of forming a mask for dry etching except for an annular region outside the circular electrode, and a step of forming a mask for dry etching except for an annular region outside the annular electrode. The method is characterized in that it includes a step of removing the semiconductor layer under the region by dry etching until at least the activated stone is penetrated.
そして、好ましくは、ドライエツチング用のマスクとし
て金のメッキ膜または酸化チタン（ＴｉＯ□）膜を用い
ることを特徴とする。Preferably, a gold plating film or a titanium oxide (TiO□) film is used as a mask for dry etching.
本発明では、活性層を含む半導体層上に円形の電極金属
を形成し、その外側の輪状の領域を除いてドライエツチ
ング用のマスクを形成し、ドライエツチングにより発光
領域となる円形メサを形成する。In the present invention, a circular electrode metal is formed on a semiconductor layer including an active layer, a mask for dry etching is formed except for an annular region on the outside, and a circular mesa which becomes a light emitting region is formed by dry etching. .
この方法によると、はぼ平坦な表面にフォトレジスｉ・
でパターンを形成するので、パターン形成が容易であり
、目合わせの精度も低くてよい。従って、従来のような
電極形成における歩留りの低下がなくなる。According to this method, photoresist i.
Since the pattern is formed using the above method, pattern formation is easy, and alignment accuracy may be low. Therefore, there is no decrease in yield in electrode formation as in the conventional method.
また、ドライエツチングマスクとして金メッキ膜を用い
た場合、半導体層を塩素（ＣＩＺ）ガスを用いたドライ
エツチングで４〜５ｐエツチングしたとき金メッキ膜も
数−エツチングされる。しかし、金メッキ膜の厚さを１
０〜２０−と厚くしておけば、半導体層を所定の深さま
でエツチングする事は容易である。また、エツチング後
、残った金のメッキ膜はそのまま電極として使えるので
、金メッキ膜の厚さを制御する必要もない。Further, when a gold plated film is used as a dry etching mask, the gold plated film is also etched several times when the semiconductor layer is etched by 4 to 5 p by dry etching using chlorine (CIZ) gas. However, the thickness of the gold plating film is 1
If the thickness is set to 0 to 20 -, it is easy to etch the semiconductor layer to a predetermined depth. Further, since the remaining gold plating film after etching can be used as an electrode as it is, there is no need to control the thickness of the gold plating film.
さらに、ドライエツチングのマスクとしてＴｉＯ２膜を
用いた場合、半導体層を塩素ガスを用いたドライエツチ
ングでエツチングしたときのＩｎＰやＩｎＧａＡｓＰの
エツチング速度はＴｉｅ。Further, when a TiO2 film is used as a dry etching mask, the etching rate of InP or InGaAsP when a semiconductor layer is etched by dry etching using chlorine gas is Tie.
膜のそれの約１０倍である。従って、半導体層を５ｐエ
ツチングするにはＴｉｅ！膜を約０．５μ形成しておけ
ばよい。この方法では、ＴｉＯ□膜は薄膜で良いのでＴ
ｉｅ、膜の形成およびパターニングを容易にできる利点
がある。It is about 10 times that of the membrane. Therefore, for 5p etching of a semiconductor layer, Tie! It is sufficient to form a film with a thickness of about 0.5μ. In this method, since the TiO□ film can be a thin film, T
ie, there is an advantage that film formation and patterning can be facilitated.
このように、ドライエツチングを用いて円形メサを形成
すると、従来のような円形メサの上に電極を形成する際
の難しいパターニングが必要なく、歩留りの大幅な向上
が可能である。Forming a circular mesa using dry etching in this way eliminates the need for difficult patterning when forming an electrode on a circular mesa, as in the conventional method, and it is possible to significantly improve the yield.
以下、本発明を図面により詳細に説明する。 Hereinafter, the present invention will be explained in detail with reference to the drawings.
第１図は、本発明の一実施例の面発光ダイオードの構造
を示す断面図である。第２図は、第一の実施例の製造工
程図である。第３図は、第二の実施例の製造工程図であ
る。本実施例として材料にＩｎＰ／ＩｎＧａＡｓＰを用
いた面発光ダイオードの製造方法について説明する。FIG. 1 is a sectional view showing the structure of a surface emitting diode according to an embodiment of the present invention. FIG. 2 is a manufacturing process diagram of the first embodiment. FIG. 3 is a manufacturing process diagram of the second embodiment. In this embodiment, a method for manufacturing a surface emitting diode using InP/InGaAsP as the material will be described.
まず、第一の実施例を第２図を用いて説明する。First, a first embodiment will be described using FIG. 2.
ｎ型［ｎＰ基板ｌ上に結晶成長によりｎ型ＩｎＰ２（ｊ
２ＩＪ！Ｊ５−、キャリア密度Ｉ Ｘ Ｉ Ｏ”Ｃｆｆ
１−’）、アンドープＩｎＧａＡｓＰ活性層３（層厚１
．５１Ｍ、バンドキャップに相当する波長１．３−）
、Ｐ型［ｎＰ４ （層厚１４、キャリア密度ｌＸｌ０”
ＣＩ＋１−’） 、ｐ型１ｎＣ，ａＡｓＰ５ （Ｊｉ層
厚−、キャリア密度Ｉ Ｘ １０ ”ｃｍ−”、バンド
キャンプに相当する波長１．ＩＪ！ｍ）の半導体層を順
次形成する。n-type [n-type InP2 (j
2IJ! J5-, carrier density I X I O”Cff
1-'), undoped InGaAsP active layer 3 (layer thickness 1
．． 51M, wavelength corresponding to band gap 1.3-)
, P type [nP4 (layer thickness 14, carrier density lXl0''
CI+1-'), p-type 1nC, aAsP5 (Ji layer thickness -, carrier density IX10 "cm-", wavelength corresponding to band camp 1.IJ!m) semiconductor layers are sequentially formed.
次に、ＳｉＯ□絶縁膜６をＣＶＤにより形成した後、直
径１００Ｉ！ｍの円形の部分のみフォトレジストによっ
て除去する。次に全面にｐ型電極７として金、亜鉛（Ａ
ｕ、 Ｚ ｎ）を蒸着により形成する。これにより
、第２図（ａ）で示した構造となる。Next, after forming the SiO□ insulating film 6 by CVD, a diameter of 100I! Only the circular portion m is removed using photoresist. Next, gold, zinc (A
u, Zn) are formed by vapor deposition. This results in the structure shown in FIG. 2(a).
次に、フォトレジストにより同心円の輪状のレジスト１
２をｐ型電極７上に形成する。輪の外径を１００−１内
径を２０−とした。この部分が輪状の領域１４である。Next, a concentric ring-shaped resist 1 is formed using photoresist.
2 is formed on the p-type electrode 7. The outer diameter of the ring was 100-1, and the inner diameter was 20-1. This portion is the ring-shaped region 14.
次に金メッキを行うと、レジストの上には金メッキされ
ず、輪状の領域１４の内部の円と外部にのみ金メッキさ
れる。これによって、１０〜２０−の厚さの金メッキ膜
が形成され第２図（ｂ）で示した構造となる。When gold plating is performed next, the resist is not plated with gold, but only the inner circle and the outside of the annular region 14 are plated with gold. As a result, a gold plating film having a thickness of 10 to 20 mm is formed, resulting in the structure shown in FIG. 2(b).
次に、レジスト１２を洗浄して除去した後、塩素（Ｃ１
，）ガスとアルゴン（Ａｒ）ガスを用いたドライエツチ
ングにより、表面をエツチングした。Next, after cleaning and removing the resist 12, chlorine (C1
, ) gas and argon (Ar) gas, the surface was etched by dry etching.
輪状の領域１４ではｐ型電極７からＩｎＧａＡｓＰ活性
層３まで貫通してｎ型ＩｎＰ２に達するまで、半導体層
をエツチングした。このとき、輪状の領域１４の内部の
円と外部の円の間に金メッキｎ莫１３が２〜４−程度エ
ツチングされた。このようにして輪状の溝８が形成され
、その内部に直径２０ｔｒｍ、高さ４〜５／／ＩＩ＋の
円形メサ９が形成される。In the annular region 14, the semiconductor layer was etched from the p-type electrode 7 to the InGaAsP active layer 3 until reaching the n-type InP2. At this time, gold plating 13 was etched by about 2 to 4 mm between the inner circle and the outer circle of the annular region 14. In this way, an annular groove 8 is formed, and a circular mesa 9 having a diameter of 20 trm and a height of 4 to 5//II+ is formed inside the annular groove 8.
その後、基板１の反対側にｎ型電極１０を形成し、直径
１００−の光を取り出す窓ＩＩをフォトレジストにより
形成し、第２図（Ｃ）で示した構造にする。Thereafter, an n-type electrode 10 is formed on the opposite side of the substrate 1, and a window II having a diameter of 100 mm for extracting light is formed with photoresist to obtain the structure shown in FIG. 2(C).
第２図（Ｃ）では、ｐ型電極７の上に金メッキ膜１３が
残っているが、電極部としてそのまま使えるので第１図
と同等である。また、円形メサ９以外の部分は５ｉｎ２
絶縁膜６があるので電流は流れない。従って、円形メサ
の部分のみが発光領域となる。In FIG. 2(C), the gold plating film 13 remains on the p-type electrode 7, but since it can be used as an electrode part as it is, it is the same as in FIG. 1. In addition, the parts other than the circular mesa 9 are 5in2
Since there is an insulating film 6, no current flows. Therefore, only the circular mesa portion becomes a light emitting region.
このようにして、本発明による面発光ダイオードは製造
される。この方法では発光領域となる円形メサの上に電
極を形成する際、精度を必要とするフォトレジストのパ
ターニングが不要であり、それに伴う歩留りの低下がな
くなった。In this way, a surface emitting diode according to the present invention is manufactured. This method eliminates the need for photoresist patterning, which requires precision, when forming electrodes on the circular mesa that will serve as the light emitting region, and eliminates the accompanying drop in yield.
次に、第３図を用いて本発明による第二の実施例を説明
する。第２図において説明した第一の実施例のように、
ｎ型１ｎＰ基板１上に半導体層２〜５を形成し、その上
にＳｉｎ、絶縁膜６とｐ型電極７を形成する。これによ
って第２図（ａ）と同じ形になる。次に酸化チタン（Ｔ
ｉ Ｏ□）膜１５をスパッター蒸着によって０． ４
ｔｒｍ程度形成する。次に、レジスト１６を塗布し、フ
ォトレジストにより外径１００ｍ、内径２０−の輪状の
部分のみレジスト１６を除く。Next, a second embodiment of the present invention will be described using FIG. As in the first embodiment described in FIG.
Semiconductor layers 2 to 5 are formed on an n-type 1nP substrate 1, and a Sin insulating film 6 and a p-type electrode 7 are formed thereon. This results in the same shape as in Figure 2(a). Next, titanium oxide (T
iO□) film 15 was deposited by sputter deposition. 4
About trm is formed. Next, a resist 16 is applied, and only a ring-shaped portion with an outer diameter of 100 m and an inner diameter of 20 mm is removed using photoresist.
このレジスト１６をマスクとして、ＣＦ ａガスを主と
したガスを用いてドライエ・ノチングを行い、輪状の領
域１４のＴｉｅｔ膜１５膜上５チングして除去する。こ
のドライエツチングにおけるＴｉ０ｚＪ］Ｅｉとレジス
トのエツチング速度の比は１．２なので、０．５〜１．
０−の厚さのレジストを用いれば、Ｑ、５ｔａのＴｉｅ
、膜１５をエツチングするのは容易である。こうして第
３図（ａ）の形状になる。Using this resist 16 as a mask, dry etching is performed using a gas mainly composed of CFa gas, and the Tiet film 15 in the annular region 14 is etched and removed. In this dry etching, the ratio of the etching speed of Ti0zJ]Ei and the resist is 1.2, so the ratio is 0.5 to 1.
If a resist with a thickness of 0- is used, a tie of Q, 5ta is obtained.
, it is easy to etch the film 15. In this way, the shape shown in FIG. 3(a) is obtained.
次いで、レジスト１６を洗浄して除去した後、Ｃ１ｔと
Ａｒガスを用いたドライエツチングによって円形メサを
作るためのエツチングをした。これらのガスではｐ型電
極７や半導体層とＴ ｉ Ｏを膜１５のエツチング速度
の比は約１０である。従って、Ｔｉｅ、膜０．５−をエ
ツチングして除去する間にｐ型電極７と半導体層合わせ
て５−程度エツチングされるので、Ｉ ｎＧａＡｓ Ｐ
活性層３を貫通し、ｎ型１ｎＰ２に達する。このように
して輪状の溝８が形成され、中に直径２０ρ、高さ約５
１！ｒＲの円形メサ９が形成され、ここが発光領域にな
る。Next, after the resist 16 was washed and removed, dry etching was performed using Clt and Ar gas to form a circular mesa. With these gases, the etching rate ratio of the p-type electrode 7 or the semiconductor layer and the T i O film 15 is about 10. Therefore, while the Tie film is etched and removed, the p-type electrode 7 and the semiconductor layer are etched by about 5 cm in total.
It penetrates the active layer 3 and reaches the n-type 1nP2. In this way, an annular groove 8 is formed, with a diameter of 20ρ and a height of approximately 5.
1! A circular mesa 9 of rR is formed, which becomes a light emitting region.
次に、ｎ型電極１０と光を取り出す窓１１を形成し第３
図（ｂ）、即ち第１図の構造にする。Next, an n-type electrode 10 and a window 11 for extracting light are formed, and a third
The structure shown in FIG. 1 (b), that is, FIG.
この方法はＴｉＯ□膜と半導体層のドライエツチングに
よるエツチング速度比が大きいことを利用している。Ｔ
ｉＯ２膜を０．５１ｓ１程度形成しパターニングするこ
とにより容易にエツチングマスクが形成できる利点があ
る。この方法でも、従来のような難しいパターン形成の
必要がないため、歩留りが大幅に向上した。This method utilizes the fact that the dry etching speed ratio between the TiO□ film and the semiconductor layer is large. T
There is an advantage that an etching mask can be easily formed by forming an iO2 film of about 0.51 s1 and patterning it. With this method as well, there is no need for difficult pattern formation as in the conventional method, resulting in a significant improvement in yield.
第−及び第二の実施例では、［ｎ Ｐ ／ ｒ ｎ Ｇ
ａＡｓＰを材料として用いた。しかしＡｊ！ＧａＡｓ
／ Ｇ ａ Ａ ｓ等信の化合物半導体にも適用できる
。In the first and second embodiments, [n P / r n G
aAsP was used as the material. But Aj! GaAs
It can also be applied to compound semiconductors such as /GaAs etc.
以上説明したように、本発明による面発光ダイオードの
製造方法によれば、円形メサ及びその上の電極を容易に
形成できるので、従来に比べ大幅に歩留まりを向上させ
ることができた。As explained above, according to the method for manufacturing a surface emitting diode according to the present invention, the circular mesa and the electrodes thereon can be easily formed, so that the yield can be significantly improved compared to the conventional method.
第１図は、本発明の面発光ダイオードの製造方法による
一実施例の断面図である。
第２図は、第１図に示した一実施例を本発明の製造方法
によって作る第一の実施例の工程を示す断面図である。
第３図は、同様に第二の実施例の工程を示す断面図であ
る。
１・・・ｎ型ＩｎＰ基板 ２・・・ｎ型１ｎＰ３−１
ｎ Ｇ ａ Ａ ｓ Ｐ活性層 ４ ・Ｐ型ＩｎＰ
５・・・ｐ型ＩｎＧａＡｓＰ
６・・・ＳｉＯ□絶縁膜 ７・・・ｎ型電極８・・・
輪状の溝 ９・・・円形メサ１０・・・ｎ型電
極 １１・・・光を取り出す窓１２・・・レジス
ト １３・・・金メッキ膜１４・・・輪状の領域
１５・・・Ｔ ｉ Ｏ□膜１６・・・レジスト
代理人 弁理士 岩 佐 義 幸
第１図FIG. 1 is a sectional view of an embodiment of the method for manufacturing a surface emitting diode of the present invention. FIG. 2 is a cross-sectional view showing the steps of the first embodiment in which the embodiment shown in FIG. 1 is manufactured by the manufacturing method of the present invention. FIG. 3 is a sectional view similarly showing the steps of the second embodiment. 1...n-type InP substrate 2...n-type 1nP3-1
n Ga As P active layer 4 ・P type InP
5...p-type InGaAsP 6...SiO□ insulating film 7...n-type electrode 8...
Ring-shaped groove 9... Circular mesa 10... N-type electrode 11... Window for extracting light 12... Resist 13... Gold plating film 14... Ring-shaped region 15... T i O□ Membrane 16...Resist agent Yoshiyuki Iwasa, patent attorney Figure 1
Claims (3)
工程と、前記円形の電極の外側の輪状の領域を除いてド
ライエッチング用のマスクを形成する工程と、前記輪状
の領域の下の前記半導体層を少なくとも活性層を貫通す
るまでドライエッチングで除去する工程を含むことを特
徴とする面発光ダイオードの製造方法。(1) A step of forming a circular electrode on the semiconductor layer including the active layer, a step of forming a mask for dry etching except for the ring-shaped area outside the circular electrode, and a step of forming a mask for dry etching except for the ring-shaped area on the outside of the circular electrode. A method for manufacturing a surface emitting diode, comprising the step of removing the semiconductor layer by dry etching until at least the active layer is penetrated.
用いる特許請求の範囲第１項記載の面発光ダイオードの
製造方法。(2) A method for manufacturing a surface emitting diode according to claim 1, in which a gold plating film is used as a mask for dry etching.
ＴｉＯ＿２）膜を用いることを特徴とする特許請求の範
囲第１項記載の面発光ダイオードの製造方法。(3) Titanium oxide (
The method for manufacturing a surface emitting diode according to claim 1, characterized in that a TiO_2) film is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61059392A JPS62217675A (en) | 1986-03-19 | 1986-03-19 | Manufacture of surface light emitting diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61059392A JPS62217675A (en) | 1986-03-19 | 1986-03-19 | Manufacture of surface light emitting diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62217675A true JPS62217675A (en) | 1987-09-25 |
Family
ID=13111965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61059392A Pending JPS62217675A (en) | 1986-03-19 | 1986-03-19 | Manufacture of surface light emitting diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62217675A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01225378A (en) * | 1988-03-04 | 1989-09-08 | Omron Tateisi Electron Co | Semiconductor light emitting element and range/ photoelectric sensors equipped with same |
| WO2020106914A1 (en) * | 2018-11-21 | 2020-05-28 | Analog Devices, Inc. | Superlattice photodetector/light emitting diode |
-
1986
- 1986-03-19 JP JP61059392A patent/JPS62217675A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01225378A (en) * | 1988-03-04 | 1989-09-08 | Omron Tateisi Electron Co | Semiconductor light emitting element and range/ photoelectric sensors equipped with same |
| WO2020106914A1 (en) * | 2018-11-21 | 2020-05-28 | Analog Devices, Inc. | Superlattice photodetector/light emitting diode |
| US11695093B2 (en) | 2018-11-21 | 2023-07-04 | Analog Devices, Inc. | Superlattice photodetector/light emitting diode |
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