JPS62216422A - Josephson a/d converter - Google Patents

Abstract

PURPOSE:To convert even a small amplitude signal and perform A/D conversion with a high precision by making the method for input of relatively upper bits of an analog signal to be converted to comparators and that of relatively lower bits different from each other. CONSTITUTION:An input signal to be converted is inputted to comparators C1-C4 for lower four bits through a ladder type resistance circuit network consisting of eight resistances R to attain equivalent desired thresholds in lower bit comparators. Comparators C5-C8 for upper four bits have a common control line for input signal, and a current taking-out resistance Pn (n=5-8) is con nected to each comparator Cn (n=5-8), and the input signal current branched by the ladder type resistance circuit network is supplied to them. The length of the control line for input signal coupled to comparators C5-C8 is set to 1/2, 1/4, 1/8, and 1/6 successively, that is, the length of the control line for input signal coupled to one comparator is set to a half of that coupled to the preceding comparator.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention provides a high-speed analog converter ( (hereinafter referred to as "A/D converter").

[Conventional technology]

Figure 5 is from IBM, Technical Disclosure Plutin Wc/Volume 7, March 10th, 1970.
No. 30!3 page (IBM T, D, B, vo
l.

/7, A/OMarch/ri7j p, 303
3) is a circuit configuration diagram of a 3-bit A/D converter (hereinafter referred to as the "conventional method") disclosed by Mr. Tsuryope.

The present Jifuson A/D converter has the following operating principle. As shown in the figure, this A/D converter has three
Three three-junction superconducting quantum interferometers (hereinafter referred to as "SQU") Ol correspond to the bits.

02.03 is used as a comparator, and an analog signal to be converted (1a in the figure) is applied to each 5QUID as a control current to each common control current line. Here, the mark X is a Josephson junction, and Po (+1=/, 2.3.-, where n is large for the upper bit) is a resistor for taking out the output current. Each 5Q
The maximum Josephson current value of the UID is 12, that is, it has periodic threshold characteristics with respect to the control current value as shown in FIG. That is, On (n=/+2+3,...
), the control current value corresponding to one cycle at the threshold value is △
If Icn, △Icn/△Ic (n +
The inductance value of each 5QUID is chosen by varying the spacing of the junctions such that / ) = +. In such a configuration, when a pulsed bias current is commonly applied to each of the 5 QUIDs, if Ia is at the location marked * in Figure 6, that 5 QUID will undergo voltage transition, and at other locations, the 8 QUID will undergo voltage transition. It is easy to understand that this is not the case. Then, a potential difference occurs between both ends of the resistor Pn connected to the comparator 0, which has undergone voltage transition, and the voltage difference between both ends of the resistor pn, which is connected to the comparator On, which has not undergone voltage transition, is ov. As shown in the figure, the A/D converter classifies the analog signal to be converted into 2"-4 levels and encodes it into a 3-bit binary code (digital). It can be seen that it has the function of converting into a gray code.Although it is a gray code in the figure, a binary code etc. can be realized by shifting the starting point of the period in each 8QUID.In this example, a 3-bit However, it is easy to understand that in general, even in the case of n bits, n 5QUIDs are used as comparators to classify and encode the analog signal to be converted into 2n levels. Good morning.

In the case of the Josephson A/D converter based on this principle, the following three methods have been conventionally considered in order to realize equivalent threshold characteristics for each bit as shown in FIG.

(2) As in the conventional method, the self-inductance of each 5QUID is constructed by having a positive relationship from the lower bit to the upper bit.

■ As shown in Figure 7, each 5QUID (0/, 0
2°...), by configuring the length of the input signal control line coupled thereto to be 10 in order from the lower bit to the upper bit, each control line and each 5QUI
A method of configuring so that the mutual inductance between D is sequentially reduced to 1/2.

■ As shown in Figure r, each 5QUID (0/, 0
A method in which the amplitude of the analog signal current to be converted (control current) input to the converter (control current) is sequentially halved from the lower bit to the upper bit using a ladder resistor network.

In this method, the self-inductance and mutual inductance of each 5QUID are the same, but by controlling the amplitude of the input current to each 5QUID, they (self-inductance, t is mutual inductance) can be changed equivalently. It has the same functionality as .

However, it has become clear that each of these methods suffers from the following drawbacks, as the required conversion accuracy increases and the number of pits increases. That is, in the case of method (2), the 5QUID in each bit is different, and using the same process, many different self-inductances, such as ♂21 type, are designed and manufactured so that their relative values are sufficiently accurate. It's difficult to do that.

In the case of the method (■), the fringe effect of the control line and the influence of the stray inductance in each 5QUID are small.As with the method (■), using the same process, many different mutual inductances, for example two types, can be generated. of,
Designed so that its relative value is accurate enough! It was difficult and rare to make a B.

Method (2) does not have this drawback. However, in the case of this method, in the most significant bit, the signal amplitude becomes, for example, N pips (in the case of an A/D converter) + 200 cm compared to the original signal amplitude. On the other hand, when considering 8QUIDs that can be designed in reality, the current value at the threshold value/period is at least 0! About mk is necessary. Therefore, for example, if we consider an r-bit A/D converter, the input signal is actually converted digitally to r-bit precision.
For example, set the full scale amplitude to 0. j x2 ”-1
) = 4#mA, which requires an input signal having a large value, and has the disadvantage that it is practically impossible to perform human-to-digital conversion of minute amplitude analog signals.

[Purpose of the invention]

An object of the present invention is to provide a Josephson A/D converter that is capable of converting minute amplitude analog signals and also capable of high precision conversion.

[Structure of the Invention] The present invention provides an N-bit Josephine λ/D converter in which: (1) an input signal to be converted is inputted to a comparator of a relatively lower bit through a ladder resistor network; realizing the relative desired threshold in the bit comparator;
For relatively high-order bit comparators, the mutual inductance in each of the 5QUID comparators of the control lines magnetically coupled to them is relatively l, +1.

...Sequentially 1/
2, the coupling length of each control line is set to 11. The comparators may be formed so that their respective self-inductances become 1/2 sequentially as the relative 21, ++4-9, etc. become more significant bits, or alternatively, each of the above-mentioned methods may be used. The main feature of the present invention is that it is possible to convert minute amplitude analog signals with high precision by using a configuration method in which the lower and higher order configuration methods are reversed.

This method differs from the conventional technology in the input form of the converted signal to each comparator. A detailed explanation will be given below using specific examples.

〔Example〕

(Example/) Figure 1 is an example of the present invention, and is illustrated for the case of conversion accuracy r pits. At one end of each of the analog signal current (control current) input control lines in the quantum interferometer, a terminating resistor with a resistance value of & is connected directly or via a superconducting line with a characteristic impedance. The other end of each control line is connected to each m branch resistor of a ladder resistor network consisting of 2m resistors of resistance value 几, each corresponding to the upper N-m=μ bits of the remaining). In the superconducting quantum interferometer, seven common control lines for input signal current are installed, and the common control lines are connected to each other by branching at each branch of the ladder-shaped resistor network. The mutual inductance in each superconducting quantum interferometer of the common control line, which has a structure in which a signal input current is supplied and is magnetically coupled to the N-m superconducting quantum interferometers, is The coupling length of the common control line in each of the superconducting quantum interferometers is calculated by dividing the coupling length of the common control line in each superconducting quantum interferometer so that it becomes 1/2 relatively, especially as it becomes more significant. This is a J-eye/D converter characterized by its shape.

That is, as shown in FIG. 1, in the case of this A/D converter, the lower μ bit comparators (0/, 02. OJ.

04t), an equivalent desired threshold value in the lower bit comparator is realized by inputting the input signal to be converted through a ladder resistor network consisting of r (4tXJ) resistance values. Each comparator is turned on (n=/,
2.3. ≠) is a current extraction resistor pn (n=/,
2. J, ≠) are connected. Here, as shown in Fig. 1, one end of the input line of each comparator is terminated with a resistor of ordinary value, and the other end is connected to a branch resistor (几) of the ladder-shaped resistor network. The reason for this structure is to take impedance matching into consideration, and when matching is not absolutely necessary, both resistors may be combined (2 liters). This means that upper ≠ bits (Oj, CG, 07. OJ')
(The D comparators use a common input signal control line, and each comparator On (n = 3.6.7. completed) is connected to a current extraction resistor Pn (1 = j, &+71?) The structure is such that the input signal current that has been branched through the ladder resistor network is supplied to it.
The length of the control line for the input signal coupled to each comparator is determined from the lower bit (OJ'') to the upper bit (Or >), i.e., to the immediately upper bit (Or >), that is, to the immediately higher bit /2. Therefore, the mutual inductance in each of these 5QUID comparators is formed so that it becomes relatively smaller as it becomes more significant bits. However, it can be seen that the equivalent desired threshold value is realized in the upper bit comparator as well as in the case of the lower bit.

If not configured in this way, 1 at the 5QUID threshold
If the current value for the period is 0.3 mk, the full-scale amplitude of the input signal to be converted is OJ x 2" = μm, that is, the input signal is smaller than when using a conventional ladder resistor network. It can be seen that a sufficiently small signal can be converted since the full scale amplitude of is only 1/16.
It can be seen that the level of the control line length in the comparator of the upper φ bit is ≠ only the level υ, and the number of levels is such that sufficiently accurate relative accuracy can be achieved in the same process, and high-precision conversion is also possible. .

Here, in this example, μ is an equal portion of r bits of precision.
I distributed each bit to one of the above different input methods, but
Depending on the input maximum amplitude and the difficulty of the chip manufacturing process, it can be divided into, for example, 3 bits and j bits.
Of course, it may be divided into 11 unequal parts.

(Example 2) FIG. 2 shows another example of the present invention,
As in the first embodiment, the diagram shows a case where the conversion precision is t bits. As shown in the figure, in this example, the input method for the lower ≠ bit is the same as in the embodiment, but the upper ≠
Beep) (OJ″, OA.

Embodiment 1 shows that the comparators of 07, Of) are formed in the same way as in the conventional method, so that the self-inductance of each one becomes 1/2 sequentially as it goes to the upper bits. different from.

From this configuration, it can be easily understood that the effects of this embodiment are exactly the same as those of the first embodiment. Also, in this example, as in the first embodiment, the upper and lower bits of the r bits of precision are distributed to two different input methods, for example, 3 bits and j bits. Of course, it may be divided into unequal parts.

(Embodiment 3) FIG. 3 shows another embodiment of the present invention. In this example, the signal input method for relatively lower bits and the signal input method for relatively upper bits in Embodiment 1 are reversed. This configuration example has the same effect as the first embodiment.

(Embodiment μ) Figure ≠ shows another embodiment of the present invention, and in this example, the signal input method for relatively lower bits and the signal input method for relatively higher bits in Example 2 are reversed. This is a configuration example υ, and the effect is exactly the same as that of the embodiment λ.

〔Effect of the invention〕

As explained above, the present invention provides a method for inputting relatively high-order bits of an analog signal to be converted to a comparator and a method for inputting relatively low-order bits of the analog signal to a comparator in a seven-channel A/D converter. It has the advantage of using a different type of input method, being able to convert small amplitude signals, and performing highly accurate human/D conversion6.

[Brief explanation of drawings]

Part 1: According to the invention? One embodiment of the bit input A/D converter, FIG. 2, FIG. 3, FIG. Figure 6: Maximum current value versus control current characteristics in each comparator 5QUID of the present invention and the conventional A/D converter; 7C1 Conventional N-bit digital converter circuit configuration example. Another example of the configuration of the A/D converter; Figure 1: Another example of the configuration of the conventional N-bit λ/D converter.

Claims (4)

[Claims] (1) A fully parallel A/D converter that extracts N-bit digital signals in parallel from N comparators using Josephson elements, and the N comparators are current-controlled superconducting quantum interference The period of the periodic threshold characteristic of the maximum Josephson current value for the converted analog signal current input to each comparator is determined by the comparison from the lower bit comparator to the upper bit comparator. Josephson A/D that gradually doubles as the device grows
In the converter, the amplitude of the analog signal current in each of the superconducting quantum interferometers corresponding to the lower m bits of the N bits is sequentially converted from the lower bit to the upper bit using a ladder resistor network. An input signal current control line is connected to each of the superconducting quantum interferometers so that the current is 1/2, and one common control line to each of the superconducting quantum interferometers corresponding to the remaining upper N-m bits is connected to the input signal current control line. A common control line for input signal current is installed, and the common control line has a structure in which the signal input current that has been branched at the ladder resistor network is supplied, and The mutual inductance in each superconducting quantum interferometer of the common control line magnetically coupled to the conducting quantum interferometer is reduced to 1/2 from the lower bit to the upper bit. A Josephson A/D converter, characterized in that the coupling length of the common control line in a conduction quantum interferometer is formed. (2) A fully parallel A/D converter that extracts N-bit digital signals in parallel from N comparators using Josephson elements, and the N comparators are current-controlled superconducting quantum interference The period of the periodic threshold characteristic of the maximum Josephson current value for the converted analog signal current input to each comparator is determined by the comparison from the lower bit comparator to the upper bit comparator. Josephson A/D that gradually doubles as the device grows
In the converter, the amplitude of the analog signal current in the superconducting quantum interferometer corresponding to the lower m bits of the N bits is sequentially reduced by 1/1 from the lower bits to the upper bits using a ladder resistor network. An input signal current control line is connected to each of the superconducting quantum interferometers so that the input signal current control line is connected to each of the superconducting quantum interferometers so that the input signal current control line is connected to one input signal common to each of the superconducting quantum interferometers corresponding to the remaining upper N-m bits. A common control line for current is connected, and the common control line is supplied with the signal input current that has been branched at the ladder resistor network, and the N-m superconducting quantum In an interferometer, a Josephson A/D converter is characterized in that each self-inductance is formed so as to be halved successively from lower bits to upper bits. (3) A fully parallel A/D converter that extracts N-bit digital signals in parallel from N comparators using Josephson elements, and the N comparators are current-controlled superconducting quantum interference The period of the periodic threshold characteristic of the maximum Josephson current value for the converted analog signal current input to each comparator is determined by the comparison from the lower bit comparator to the upper bit comparator. Josephson A that gradually doubles as it becomes a vessel/
In the D converter, one input signal current common control line is installed common to each of the superconducting quantum interferometers corresponding to the lower m bits of the N bits, and The mutual inductance in each superconducting quantum interferometer of the common control line magnetically coupled to the conducting quantum interferometer is
The coupling length of the common control line in each superconducting quantum interferometer is formed so that it becomes 1/2 from the lower bit to the upper bit, and each of the coupling lengths corresponding to the remaining N−m upper bits is An input signal is input to each of the superconducting quantum interferometers so that the amplitude of the analog signal current in the superconducting quantum interferometers becomes 1/2 sequentially from the lower bit to the upper bit using a ladder resistor network. It has a structure in which a current control line is connected, and is characterized in that the output end of the common control line in the m superconducting quantum interferometers is connected to the input end of the ladder-shaped resistance network. Josephson A/D converter. (4) A fully parallel A/D converter that extracts N-bit digital signals in parallel from N comparators using Josephson elements, and the N comparators are current-controlled superconducting quantum interference The period of the periodic threshold characteristic of the maximum Josephson current value for the converted analog signal current input to each comparator is determined by the comparison from the lower bit comparator to the upper bit comparator. Josephson A/D that gradually doubles as the device grows
In the converter, one input signal current common control line common to each of the superconducting quantum interferometers corresponding to the lower m bits of the N bits is installed, and the m superconducting The self-inductance of each quantum interferometer is formed to be 1/2 from the lower bit to the upper bit, and the analog signal current in the superconducting quantum interferometer corresponding to the remaining upper N-m bits is a structure in which an input signal current control line is connected to each of the superconducting quantum interferometers so that the amplitude of the superconducting quantum interferometer is sequentially reduced to 1/2 from the lower bit to the upper bit using a ladder-shaped resistance network; A Josephson A/D converter, characterized in that the output end of the common control line of the m superconducting quantum interferometers is connected to the input end of the ladder-shaped resistance network.