JPS62213492A - Video signal field-frame converting circuit - Google Patents

Abstract

PURPOSE:To minimize flickers and to stably reproduce a picture by compensating, by means of gradation correction, the deterioration in the brightness of a high-level signal caused by a CCD delay element at the time of generating a frame video signal form a field video signal. CONSTITUTION:The one-field video signal FM-modulated and recorded in one track of a video floppy disk, is read by a reproducing magnetic head, and inputted to an input terminal 10. A demodulation circuit 12 demodulates said signal, and a luminance signal Y that includes a synchronizing signal S is obtained from the output 14. In the mean time, a switching pulse forming circuit 24 outputs pulses 28 switched at every one field, and supplies them to a changeover switch 16. Also, the demodulated output 14 is delayed by a delay circuit 20 for a half horizontal scanning period, gradation-corrected by a gamma correction circuit 34, and supplied to the switch 16. The switch 16 shifts at every field so that its two inputs are alternately outputted. Therefore, one-frame signal is outputted as a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal circuit, and particularly to a field/frame conversion circuit that converts a field video signal into a frame video signal.

11 For example, in an electronic still camera system that records still image video signals on a small-diameter video recording magnetic disk, or so-called video floppy, and plays back the video, one frame of image is converted into one field of video. As is well known, it is recorded on one track in the form of a signal.
When reproducing images on a screen such as a CRT, a stable image with less flickering can be obtained by combining two fields of one frame of image into one frame by field interlacing.

Therefore, in conventional video playback systems using electronic still cameras, the L-field video signal is
A pseudo interlaced field is created by reading data from the track, and both fields are reproduced on the screen of a video reproducing device such as a CRT. In other words, the first field uses the field video signal read from the track as it is, and the second field uses the same video signal for one horizontal scanning period (
A pseudo second field is created with a delay of 1/2 of IH), and this is interlaced with the first field.

Conventionally, a charge-coupled device ((, CD) is used to delay the video signal by 0.5H to create the second field.
delay elements are often used. However, the COD delay element has a somewhat low charge transfer efficiency, which causes the level of the signal to be output from it to decrease, resulting in a brightness difference between the first field and the second field, which causes There was a problem that flicker occurred in the reproduced video.

In order to solve this problem, in a patent application filed by the present applicant, Japanese Patent Application No. 58-233482, the level of the video signal of the second field that has passed through the CCD delay circuit is compared with that of the first field that does not pass through the delay circuit. The gain of the automatic gain control amplifier on the input side of the delay circuit was adjusted according to the difference between the two, so that there was no noticeable difference in the level of the video signals in both fields.

But CC01! Broadband elements tend to have low transfer efficiency for high-level signals. This difference in transfer efficiency reaches about 5z in some examples. Therefore, conventional automatic gain control has the disadvantage that flicker cannot be sufficiently removed in the case of high-luminance video signals.

OBJECTS It is an object of the present invention to provide a field-to-frame conversion circuit for video signals that can eliminate the drawbacks of the prior art and can minimize flicker even in high-luminance video signals.

According to the present invention, a field-interlaced frame conversion circuit for a video signal receives a field video signal, creates a pseudo-field video signal, and creates a field-interlaced frame video signal. When creating a frame video signal from , the video signal of one field of the two fields constituting one frame is divided into 1/2 of one horizontal scanning period of the field video signal. The gray level of one of the two field video signals is delayed by a charge-coupled device for a substantially equal period of time, and the gray level correction is performed on the undelayed field video signal and the delayed field video signal. The field interface is achieved by substantially compensating for the difference in gradation between the field video signal and the delayed field video signal, and alternately outputting the undelayed field video signal and the delayed field video signal every one field period. This creates a raced frame video signal.

Description of Examples.

Next, embodiments of a video signal field/frame conversion circuit according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, for example, one field of video signal which is FM modulated and recorded on one track of a video floppy is read by a reproducing magnetic head, amplified, and inputted to an input terminal 10. The input terminal 10 is connected to a demodulation circuit 12, and the demodulation circuit 12 is a circuit that demodulates such an FM video signal and outputs a luminance signal Y including a synchronization signal S at its output 14.

The output 14 is connected to one input terminal 1 of the changeover switch 1B and to the input 22 of the delay circuit 20. The switching pulse forming circuit 24 receives and inputs a signal PC output in synchronization with one revolution of the magnetic disk, for example, and inputs the signal PC, which is a rectangular wave that switches at that period and a period a that includes one vertical synchronizing signal period. A switching pulse in which only one side is switched to the other side is output as output 2. Output 2 is connected to a control input of a changeover switch 16, which selectively connects its inputs 18 and 30 alternately to its output 32 in response to switching pulses provided by control input 28. It is a circuit.

The delay circuit 20 is a delay circuit that delays the composite luminance signal Y+S input from the input 22 by a period substantially equal to 1/2 of one horizontal scanning period (IH) of the video signal, and outputs the delayed signal to the output 32. In this embodiment, it consists of a CCD delay element.

In this embodiment, the output 32 of the delay circuit 20 is connected to the γ correction circuit 3.
4 are connected. The γ correction circuit 34 is a gradation correction circuit that corrects the gradation of the composite luminance signal Y♦S inputted from the input 32, and its output 30 is connected to the other input terminal of the changeover switch 1B. The gradation correction characteristics of the γ correction circuit 34 are set to compensate for the reduction in signal level caused by the delay circuit 20.

In other words, the ccn delay element of the delay circuit 20 tends to have low transfer efficiency for high-level signals. This low transfer efficiency is due to the fact that the uniform gradation composite luminance signal input to the input 22 of the delay circuit 20 as shown in FIG.
The signal is delayed by 5H period and is outputted to the output 32 as a signal with the high level portion suppressed as shown in FIG. 2B. The gradation correction characteristic of the γ correction circuit 34 is such that it compensates for the reduction in the level of such a high level signal portion caused by the delay circuit 20, that is, it expands the high level suppressed signal portion, such as that shown in FIG. 2A. It is set so that the gradation is restored to the gradation shown in and output to the output 30.

Suppose there is no γ correction circuit 34 and the output 32 of the delay circuit 20
If it is configured such that it is connected directly to the input terminal 30 of the switch 1B, the signal level of the second field will be lower than that of the first field in the part where the level of the luminance signal Y is high, and this will cause the reproduced image to change. Flicker will occur.

Explain the operation. For example, an FM-modulated video signal of one field recorded on one track of a video floppy is continuously read by a reproducing magnetic head, amplified, and inputted from an input terminal 10 to a demodulation circuit 12 .

The demodulation circuit 12 demodulates such FllI video signal and outputs composite luminance signals Y and S at its output 14.

On the other hand, the signal PG is input to the switching pulse forming circuit 24, from which a switching pulse is formed and input to the changeover switch 18. This will cause switch 1
6, the connection state is alternately switched every l field period (IV), and in the first field, the signal on the signal line 18 is
Further, in the second field, the signals on the signal lines 30 are outputted to outputs 32, respectively.

During the first field period, signal line 18 is applied to output 32 at 1V.
Since it is connected for a period of time, the composite luminance signal Y+S outputted from the output 14 of the demodulation circuit 12 is outputted as it is to the output 32. When this is played back by a video playback device such as a CRT connected to the output 32 and thereafter, a first field screen is formed by field interlacing.

During the second field period, signal line 30 is applied to output 32 at 1V.
Since it is connected for a period of time, the composite luminance signal Y delayed by 0.5H from the output 14 of the demodulation circuit 12 passes through the delay circuit 20.
es is output at output 32. When played back with a video playback device, this forms the screen of the second field with field interlacing. In other words.

A second field is pseudo-formed by one field of video signal delayed by 0.5H in the delay circuit 20, and the first field is
It is inserted between the interlaced scan lines of the field.

As described above, the gradation correction characteristics of the γ correction circuit 34 are set to compensate for the level reduction of the high level signal portion caused by the delay circuit 20. Therefore, for example, the second
As shown in Figure A, signals with high luminance levels are transmitted to the delay circuit 20.
, it is delayed for a period substantially equal to 0.5H and then outputted, but at this time, the high brightness level signal portion is suppressed and suffers a level drop as shown in Figure 2B. and is output from the output 32. γ correction circuit 34
2 extends the level drop of such a high level signal portion caused by the delay circuit 20, and outputs it to the output 30 after restoring it to almost the gradation shown in FIG. 2A.

Output 32 via switch 16, as will be seen.
The composite luminance signal Yes outputted from the device has substantially the same signal level between the first field and the second field even in the portion where the luminance signal Y has a high level, and therefore is reproduced from this signal by the video reproducing device. The flicker caused by the delay circuit 20 is substantially removed from the video.

When the connection state of the switch 1B is thus alternately switched every IV period, a frame video signal interlaced in the pseudo second field is continuously outputted from the output 32.

Note that the embodiments described here are for explaining the present invention, and the present invention is not necessarily limited thereto, and modifications and variations that can be made by those skilled in the art without departing from the spirit of the present invention. Modifications are within the scope of this invention.

For example, in the embodiment described above, the γ correction circuit 34 was connected to the output 32 of the delay circuit 20, but instead of connecting the γ correction circuit 34 to the output 32 of the delay circuit 20 and the output 14 of the demodulation circuit. A circuit 34 may be provided. In this case, after the γ correction circuit 34 expands the high level gradation, the delay circuit 20 delays the 0 and 5H periods, and accordingly, the high level gradation is expanded. The composite luminance signal Y+S is output from the delay circuit 20 in a form very close to the original with the gradation suppressed.

Furthermore, if the purpose is simply to prevent flicker, a γ correction circuit is provided between the output 14 of the demodulation circuit 12 and one input 18 of the switch 1B, and the γ correction circuit 34 at the output of the delay circuit 20 is deleted. and the output 32 of the former is directly connected to the switch 16
In that case, the other γ correction circuit suppresses the gray level of the input signal in response to the high level gray level suppressed by the delay circuit 20. As a result, the gamma characteristics of the composite luminance signals Yes input to the re-inputs 18 and 30 of the switch 16 substantially match, and flicker is substantially minimized.

As described above, according to the present invention, when a frame video signal is created from a field video signal, the reduction in brightness of a high-level signal caused by the CCD delay element is compensated for by gradation correction. Therefore, flicker in the reproduced image caused by the CCD delay element is minimized, and a stable reproduced image can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal field session frame conversion circuit according to the present invention, and FIGS. 2A and 2B are waveforms showing examples of video signal waveforms appearing in each part of the circuit shown in FIG. It is a diagram. Theory of part codes 1B... Changeover switch 20... Delay circuit 24... Switching pulse forming circuit 34... Gamma correction circuit Patent applicant Fuji Photo Film Co., Ltd. Agent Writer Takao Maruyama Volume 2A Picture book 2Bm Time period

Claims (1)

[Claims] A field-to-frame conversion circuit for a video signal that receives a field video signal, creates a pseudo-field video signal, and creates a field-interlaced frame video signal, the circuit creating a frame video signal from the field video signal. At this time, the video signal of one field of the two fields constituting one frame is mixed with the video signal of the other field for a period substantially equal to 1/2 of one horizontal scanning period of the field video signal. one of the two field video signals is delayed by a charge-coupled device, and the gray level of one of the two field video signals is corrected; A field interlaced frame by substantially compensating for the difference in gradation between the signals and alternately outputting the undelayed field video signal and the delayed field video signal every one field period. A field/frame conversion circuit for a video signal, characterized in that it creates a video signal.