JPS62211687A - Display control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A display control circuit for a display device having a frame memory, which displays display contents such as image information written in the frame memory in units of pixels (dots).

By configuring it so that it can be read while shifting bit by bit, scrolling display can be done smoothly and at high speed.

[Industrial application field]

The present invention relates to a display control circuit provided in a raster scanning type display device having a frame memory.

Common display control methods include the code refresh method and the bitmap method.

Among these, the bitmap method has a frame memory (also referred to as a bitmap memory) that stores nine display contents in correspondence with bits for each pixel, and this is sequentially read out by raster scanning and displayed on the display screen.

This method allows any information to be displayed at any position, and is suitable for displaying not only 3 character information but also 1 graphic/image information, etc.

In addition, the storage capacity of the frame memory is usually much larger than the display area of the display screen.

By providing a scroll display function, for example, 8
Large figures of about 3rd edition are stored in the frame memory, and can be read on a display surface equivalent to 85th edition.

At this time, it is desirable that scrolling be performed smoothly and at high speed.

[Conventional technology]

Raster scanning display device with frame memory (3rd
(see figure), the display contents such as one figure/image information are written into the frame memory 3 pixel by pixel, and the display control section 4 sequentially reads them out and passes them to the display section 5 in synchronization with the synchronization signal for display. The display is performed by.

Writing data to frame memory 3.

It is usually performed under the control of a central processing unit (CPU), and generally writes multiple bits simultaneously in units of bytes or words.

In addition, during display, the 2 display control unit 4 controls the frame memory 3.
Stores the memory contents in multiple bits or words in units of bytes or words.
The nodes are read at the same time, converted into bit serial data, and sent to the display unit 5.

[Problem that the invention seeks to solve]

The horizontal width of the image information stored in the frame memory 3 is L bytes (8L dots), and the horizontal width of the display area of the display section 5 is! (81 dots) long, and continuously scrolling the image information stored in the frame memory 3 in the horizontal direction means that if we focus on the data of one dot line in the horizontal direction in the image information (4th (see figure), this is described in 1.2.3. ···like,
This means reading and outputting while shifting.

However, as mentioned above, since the unit of reading the storage contents in the frame memory 3 is byte or word,
1.2.3. The amount of shift between ... must be in units of bytes or words.

However, if the pixel density on the display surface is set to, for example, 4 dots per 1111+, there is a problem that the scrolling becomes a stepped movement of 2 mm or 4 mm.

To avoid this, there is a method in which the image information stored in the frame memory 3 is shifted one bit at a time and rewritten before being displayed. However, this method has the problem that it takes a long time to rewrite the frame memory 3, which slows down the scrolling speed.

That is, an object of the present invention is to enable smooth and high-speed scrolling.

[Means for solving problems]

As shown in the principle diagram of FIG. 1, the display control circuit according to the present invention reads a predetermined length of display content stored in a frame memory, for example, one byte or one word at a time, and temporarily stores it in a buffer 1. The read control circuit 2 is configured to read the stored contents cyclically bit by bit from a set read start bit address and output them.

[Effect]

In other words, in the display control circuit of the present invention, by setting the reading start bit address of the buffer l, the image information stored in the frame memory can be read from any bit, not at the end of bytes or words. As a result, smooth pixel-by-pixel scrolling can be performed without rewriting the contents of the frame memory.

〔Example〕

FIG. 2 is a configuration diagram of an embodiment of the present invention, in which the read control circuit 2 includes an address specifying section 21 that cyclically specifies each bit address of the buffer 1 bit by bit from a set read start bit address. and a first multiplexer (MPX) 22 that selects and outputs the storage content of the bit address specified by the address specification section 21 from among the storage contents of the buffer 1, and the address specification section 21 further includes: It is composed of a first register 23, a second selection circuit 24, a second register 25, and a +1 circuit 26.

When a display area on the frame memory 3 to be displayed on the display unit 5 is specified, the address of the first byte is set in the third register 7 via the third selection circuit 6 under the control of a host device (not shown). The contents are added by 1 by the fourth selection circuit 9 and the adder 10 during wrap-around of the contents of the second register 25 until the display for one scanning line is completed. When the display ends.

An offset value (difference between the address of the last byte of each scanning line and the address of the first byte of the next scanning line) is set in advance in the fourth register 8.

It is added to the storage contents of the third register 7 by the fourth selection circuit 9 and the adder 10, and the storage contents of the third register 7 specify the byte address of the frame memory 3.

On the other hand, when setting the address of the first byte of the display contents to the third register 7, at the same time, the display start address in bits within the first byte is sent to the first register 23, and the The contents of the first register 23 are selected by the second selection circuit 24 and set in the second register 25, and thereafter the 9 selection circuit 24 selects the +1 circuit 26.
The contents of the second register 25 are converted into a dot-by-dot display synchronization signal (not shown) by the +1 circuit 26.
increases in synchronization with , and sequentially selects the inputs of the first selection circuit 22 while wrapping around.

In this way, the stored contents of the frame memory 3 are read bit by bit from the display start bit address in the first byte of the designated display area and output to the display section 5, and the contents of the third register 7 are read out bit by bit from the display start bit address in the first byte of the designated display area. When the final byte address of the display contents set in advance in the fifth register 11 is reached and the contents of the second register 25 reach the contents of the first register 23, the display of one screen ends.

The end of the display of one screen is detected by the first coincidence circuit 2, the second coincidence circuit 13, and the AND circuit 14.

The detection signal is sent to the higher-level device.

Therefore, by updating the contents of the third register 7, fourth register 8, fifth register 11, and first register 23 in synchronization with the detection signal of the AND circuit 14 under the control of the host device. .

A desired area in the storage contents of the frame memory 3 can be displayed by scrolling in units of pixels (bits).

〔Effect of the invention〕

As explained above, in the display control circuit according to the second invention,
It is possible to designate and display a desired area bit by bit without rewriting the stored contents of the frame memory, and therefore smooth and high-speed scrolling display is possible.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a configuration diagram of the embodiment. FIG. 3 is an explanatory diagram of a conventional example. FIG. 4 shows an explanatory diagram of the problem. In the figure. 1 is a buffer, 2 is a read control circuit. Figure 1 Figure 3

Claims (2)

[Claims] (1) A display control circuit provided in a display device that reads display data stored in a frame memory and displays it by raster scanning, which comprises a buffer (1) that temporarily stores a predetermined length of data read from the frame memory; A display control circuit comprising: a read control circuit (2) that reads and outputs the stored contents of a buffer (1) bit by bit cyclically from a set read start bit address. (2) The read control circuit (2) includes an address specifying section (21) that cyclically specifies each bit address of the buffer (1) bit by bit from the read start bit address, and the specified address of the buffer (1). Claim 1 (1) further comprising a multiplexer (22) that selects and outputs the stored contents of the bit address.
Display control circuit described in ).