JPS62209909A - Ultra high frequency semiconductor circuit - Google Patents

Abstract

PURPOSE:To decrease an ultra high frequency electric power in the vicinity of a necessary frequency by having a sufficiently small reactance by the ultra high frequency in the vicinity of the necessary frequency at a resistance in a bias circuit and providing in parallel a capacitor having the capacity value which has a large reactance in the low frequency. CONSTITUTION:A capacity value cb of a capacitor 4b is set to have a sufficiently small reactance in the vicinity of a necessary frequency and to be a large reactance in a low frequency. When an FET 6 is an unstable action, for example, in the low frequency to facilitate to cause an oscillation, etc., an electric length l of a microstrip line 2 is sufficiently smaller than the wavelength, and therefore, by using a bias circuit 1b, in the low frequency, a resistance 3a is given as the load to the FET 6 and the unstable action of the oscillating, etc., is prevented. In the necessary frequency, the electric length l of the microstrip line 2 is a 1/4 wavelength, and therefore, the impedance when the bias circuit 1b is watched from a connecting point 10 of a bias circuit comes to be infinite. Thus, the consumption of the ultra high frequency electric power is minimized in the bias circuit 1b.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a bias supply circuit for an ultra-high frequency semiconductor circuit that has little loss of ultra-high frequency power and enables stable operation of a semiconductor element at low frequencies. [Conventional technology] Here, we will discuss one of the ultra-high frequency semiconductor circuits using semiconductor elements.
This will be explained using a field effect transistor (hereinafter abbreviated as FET) amplifier as an example. Fig. 5 shows an example of a PET amplifier using a bias circuit having a conventional configuration as shown in, for example, Japanese Patent Publication No. 57-15510. In Figure 5, (la) is the bias circuit, (2) is the microstrip line, (3a) is the resistor, (4a) is the H capacitor, (5) is the bias terminal (4-voltage terminal), (6) is the FB
T, +71 is the gate electrode of PET, (8) is F'ET
The drain 'rg, @, (91 is the source electrode of the FET, 10) is the contact point of the bias circuit, and l! is the electrical length of the microstrip line (2), Ra is the resistance (3a
), and Ca indicates the capacitance value of the capacitor (4a). In Fig. 5, the gate electrode (
7), the mount is configured to apply a bias voltage from the bias voltage terminal (5) via the resistor (3a) and the microstrip line (2). j is set to have an electrical length of 1/4 wavelength at the required frequency, and Ca
is set to a variable value so as to have a sufficiently small reactance down to frequencies as low as, for example, several 1003 G(z).

In Figure 5, at low frequencies where FET+61 is likely to cause unstable operation, such as excavation, the electrical length l of the microstrip line (2) is sufficiently short compared to the wavelength, so the bias circuit (1a) is The connection point u of the bias circuit in Figure 2 can be expressed by the equivalent circuit shown below.
al corresponds to the connection point of the bias circuit (1a) in Fig. 5. Due to the bias circuit (1a) in Fig. 5, the resistor (3a) is applied as a load to the FET +61 at low frequencies. [Problem to be solved by the invention] The bias circuit (1a) of the conventional FET amplifier shown in FIG. In the vicinity, at the required frequency that can be expressed by the equivalent circuit shown in Fig. 6, the electrical length l of the microstrip line (2) in Fig. 6 is a quarter wavelength, so the The impedance Rb when the bias circuit (la) is viewed from the connection point qol of the bias circuit is given by the following equation.

Therefore, the characteristic impedance of the microstrip line (2) in FIG.

When using the bias circuit (1a) in Fig. 5, the resistance given by equation 11) is FE in the vicinity of the required frequency.
Since it is connected in parallel to T (5), ultra-high frequency power at the required frequency is consumed, resulting in problems such as a decrease in gain and deterioration of noise figure. This was accomplished in order to solve the problems, and to obtain an ultra-high frequency semiconductor circuit that reduces ultra-high frequency power consumption at a required frequency and enables stable operation at low frequencies similar to the conventional configuration. With the goal.

[Failure to solve the problem]

In the ultra-high frequency semiconductor circuit according to the present invention, a capacitor having a capacitance value that has a sufficiently small reactance at ultra-high frequencies near a required frequency and a large reactance at low frequencies is connected in parallel to the resistor in the bias circuit. [Function] The ultra-high frequency semiconductor circuit according to the present invention is configured such that the bias circuit is a microstrip line having an electrical length of a quarter wavelength at a required frequency, a parallel circuit of a resistor and a capacitor, By configuring it with a series circuit of a grounded capacitor and a grounded capacitor, the consumption of ultra-high frequency power near the required frequency is reduced.
Furthermore, at low frequencies, the PET can operate stably. [Embodiment of the Invention] Fig. 1 shows a circuit of an FET amplifier, which is an example of an ultra-high frequency semiconductor circuit according to the present invention.
(lb) is a bias circuit, (4b) is a capacitor, and Cb is its capacitance value.

In Figure 1, the gate voltage of FET+61 (7
), the bias voltage is applied from the bias voltage terminal (5) via the resistor (3a) and the microstrip line (2). The electrical length of Ca is set to be one wavelength, and the capacitance value of Ca is set to have a sufficiently small reactance at a low frequency of, for example, several 1001 G (z).The capacitance value of Cb is It is set to have a sufficiently small reactance near the frequency and a large reactance at low frequencies.

In Fig. 1, at low frequencies where PET (61) tends to operate unstablely, such as fc, excavation, etc., the electrical length l of the microstrip line (2) is sufficiently short compared to the wavelength, so the bias circuit ( 1b) can be expressed by both circuits as shown in Fig. 2.The connection point of the bias circuit in Fig. 2 corresponds to 1101 in Fig. 1. By using the resistor (3a) at low frequencies, the resistor (3a) is applied as a load to the F'BT f61, making it possible to prevent unstable operation such as oscillation.

The bias circuit (lb) fl of the FET amplifier according to the present invention shown in FIG. 2)' electrical length l
is a quarter wavelength, so the impedance when the bias circuit (lb) is viewed from the connection point 11α of the bias circuit in FIG. 1 becomes infinite.

Therefore, in the vicinity of the required frequency, the consumption of ultra-high frequency power in the bias circuit (1b) of FIG. 1 is as follows.

The energy consumption is lower than that of the bias circuit (1a) of FIG. 5 with the conventional configuration.

Furthermore, in the above embodiment, the bias circuit (x
In b), a microstrip line (2) having a length of 1/4 wavelength at the required frequency was used.

In this case, a microstrip line of a predetermined length may be used, and in the vicinity of the Pf+ frequency, the bias circuit (1b) in Figure 1 can be replaced with a lossless microstrip line with short-circuited ends as shown in Figure 3. Since it operates as a part of a matching circuit, it has the advantage that one circuit can be made smaller.

Further, in the above embodiment, the bias circuit (1
The bias voltage terminal +51'& of b) was installed at the connection point between the parallel circuit of resistor (3a) and capacitor (4b) and capacitor (4a), but as shown in Figure 4, the microstrip line (2 ), resistor (3a) and capacitor (4
It may be provided at one reading point with the parallel circuit of b), and in that case, there is an advantage that the DC consumption 'I- in the bias circuit (1c) can be made zero.

Further, in the above embodiment, the FET amplifier with a common source is used, but the same effect can be obtained even if the FET amplifier is with a common gate or a common drain.

Furthermore, in the above embodiments, the case of the FET amplifier was explained, but in addition to the above, it can also be used as an excavator, a 4-phase amplifier, and a modulator.

It may be an ultra-high frequency semiconductor circuit such as a mixer or a limiter, and the same effect can be obtained by using a bipolar transistor, a diode, etc. in addition to FET as the semiconductor element.

Further, in the above embodiments, a microstrip line is used as the transmission line, but the same effect can be achieved using a transmission line such as a triplate line or a coaxial line.

〔Effect of the invention〕

As described above, the present invention provides a bias circuit for an ultra-high frequency semiconductor circuit. This makes it possible to reduce the consumption of ultra-high frequency power near the required frequency compared to conventional methods, making it possible to increase the gain of amplifiers, for example.

Effects such as lower noise of the excavator can be obtained.

[Brief explanation of drawings]

Fig. 1 shows a circuit of an FET amplifier according to an embodiment of the present invention, Fig. 2 shows an equivalent circuit at a low frequency of a bias circuit of an FET amplifier, and Fig. 3 shows a required frequency of a bias circuit of an FET amplifier according to this invention. FIG. 4 is an equivalent circuit of an FET amplifier according to another embodiment of the present invention, and FIG.
The figure shows a circuit of an FET amplifier with a conventional configuration, and FIG. 6 shows an equivalent circuit at a required frequency of a bias circuit of an FET amplifier with a conventional configuration. In the figure, (la), (lb), and (lc) are bias circuits, (2) is a microstrip line, (3a) is a resistor, (4a) and (4b) are capacitors, and (5) is a bias voltage terminal. , (6) is an FET. (7) is the gate 1-'4 pole, (8) is the drain electrode, (
9) is the connection point of the bias circuit on the source '#M, i side.

Claims (4)

[Claims] (1) In an ultra-high frequency semiconductor circuit having a semiconductor element such as a diode or a transistor, a first line for transmitting ultra-high frequency power in the ultra-high frequency semiconductor circuit,
Connect one end of a second line having a predetermined length, connect one end of a parallel circuit consisting of a resistor and a first capacitor to the other end of this second line, and connect the other end of this parallel circuit. is grounded via a second capacitor, and a bias voltage is applied from the other end of the second line to the second capacitor. (2) The ultra-high frequency semiconductor circuit according to claim 1, wherein the length of the second line is an electrical length of a quarter wavelength of a required frequency. (3) The ultra-high frequency semiconductor circuit according to claim 1 or 2, wherein the bias voltage is applied from a connection point between the parallel circuit and the second capacitor. (4) The ultra-high frequency semiconductor circuit according to claim 1 or 2, wherein the bias voltage is applied from a connection point between the second line and the parallel circuit.