JPS62209840A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE:To form far better element isolation layers than the element isolation layers made of polyimide and obtain semiconductor elements with high reliability by a method wherein the element isolation layers are made of the material practically same as the material of the semiconductor elements. CONSTITUTION:A plurality of semiconductor elements 21 and element isolation layers 29 which are provided between the semiconductor elements 21 and isolate the semiconductor elements 21 electrically and optically are provided on a same foundation 11. The element isolation layer 29 is composed of polycrystalline layers, i.e. a P-type AlGaAs polycrystalline layer 31 and an N-type AlGaAs polycrystalline layer 33. Therefore, the wafer structure is such that a plurality of light emitting elements are provided on the foundation 11 and polycrystalline layers are provided between the light emitting elements. The resistance values of the polycrystalline layers 31 and 33 are much higher than those of the semiconductor element forming layers 21. The heat resistant properties of the polycrystalline layers 31 and 33 are much better than those of resin such as polyimide. As the element isolation layer 29 is made of the same material as that of the semiconductor element isolating layer 21, various properties such as thermal expansion of the semiconductor element and that of the element isolation layer are practically the same.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention comprises a plurality of semiconductor elements on a substrate and an element isolation layer for electrically and optically separating these semiconductor elements individually. The present invention relates to a semiconductor device and a method for manufacturing the same.

(Prior Art) An integrated light emitting device is an example of a semiconductor device that includes a plurality of semiconductor devices and a device isolation layer on a base. Hereinafter, a conventional semiconductor device and its manufacturing method will be explained using this integrated light emitting device as an example.

An integrated light emitting device includes a plurality of light emitting devices as semiconductor devices on a base, and an element isolation layer between the light emitting devices to electrically and optically isolate the light emitting devices. It is used, for example, as a light source for discharging a photoreceptor in an electronic printer or as a light source for reading a fax machine.

Below, we will discuss the conventional integrated light emitting device, especially its details.
Embarrassing! , f1 Kojima tightening notification system: Ushisusha ``As a company, I will briefly explain.

As an example of a conventional integrated light emitting device, a light emitting device is formed in a pn junction region obtained by selectively thermally diffusing impurities into a plurality of predetermined regions of a base, and further, There was a structure in which a region in which impurities were not diffused was used as an element isolation layer. In this case, the base used is often an epitaxially grown layer obtained by vapor phase growth.

In addition, as another integrated light emitting element, etching grooves are formed in a laminate obtained by sequentially growing two layers and an n layer on a base by liquid phase growth, and the etching grooves are formed in the laminate by the above-mentioned grooves. There is a structure in which light emitting elements are formed in each of a plurality of divided regions, and a polyimide resin is buried in the grooves between these elements to serve as an element isolation layer.

There were also integrated light emitting devices manufactured using metal organic chemical vapor deposition (MOCVD) or the like. In order to manufacture such an element, first a mask layer made of a nitride film or the like is provided on the base, and then the base layer is exposed.
A light emitting element forming semiconductor layer is selectively grown in the region not covered by this mask layer and is used to form a light emitting element. Furthermore, it had a structure in which an element isolation layer was formed by embedding polyimide resin in the region where the mask layer was provided.

(Problems to be Solved by the Invention) However, in the case where the element isolation layer is made of polyimide resin as in the past, and this element isolation layer is used to separate elements such as integrated light emitting elements that generate heat, When used as a layer, this polyimide is adversely affected by the heat from the light emitting device, which makes conventional device isolation layers insufficiently reliable for the purpose of electrically and optically isolating semiconductor devices. The problem was that it could not be done.

Furthermore, even when polyimide is used as an element isolation layer for a semiconductor device that does not generate heat, for example, after the semiconductor device is formed, polyimide is buried in a trench for element isolation, or polyimide is placed around a light emitting element. A separate and complicated process was required. Because of this,
There is a problem in that the manufacturing cost of the semiconductor device increases.

In addition, when a light emitting element is formed in an underlying region where impurities are diffused and an element isolation layer is formed using a region where impurities are not diffused, the size of the light emitting element depends on the size of the region where impurities are diffused. will be determined. However, it is difficult to control the area of this diffusion region accurately, and this makes it particularly difficult to obtain semiconductor devices such as integrated light emitting devices in which a large number of light emitting devices each having a predetermined light emitting area must be precisely arranged. The problem was that it was extremely difficult.

By the way, when performing selective growth using organometallic vapor phase epitaxy, etc., for AJIGaAs, the mixed crystal ratio of Al is 0.3 or more, and the total pressure in the growth tank is 10To.
It has been reported that when the temperature exceeds r, a polycrystalline AJZ GaAs layer grows on the nitride film used as a mask layer.

The inventor of this invention is also responsible for such reports.
t31 ap P 1w L'a l Origins After conducting various experiments and studies to improve the quality of the original material, we found that during the process of growing a semiconductor layer for forming a semiconductor element using crystal growth technology. We have discovered that it is possible to simultaneously grow a polycrystalline layer that can be used as an isolation layer for semiconductor devices.

Therefore, an object of the first invention of this application is to provide a semiconductor device that includes an element isolation layer with excellent reliability between a plurality of semiconductor elements.

The object of the second invention of this application is a method for easily manufacturing a semiconductor device comprising a plurality of semiconductor elements accurately arranged and formed in a desired shape and a highly reliable element isolation layer between these elements. Our goal is to provide the following.

(Means for Solving the Problems) In order to achieve the object of the first invention of this application, according to the present invention, a plurality of semiconductor elements provided on the same substrate and a plurality of semiconductor elements provided between these semiconductor elements are provided. A second object of the present invention is a semiconductor device comprising an element isolation layer that electrically and optically isolates each semiconductor element, wherein the element isolation layer is composed of a polycrystalline layer. In order to achieve the above, according to the present invention, when manufacturing a semiconductor device including a plurality of semiconductor elements provided on the same substrate and an element isolation layer, the manufacturing process includes a plurality of semiconductor devices provided on the substrate. forming a mask layer having windows of;
In the same layer growth step, all or part of the semiconductor element forming layer is grown on the above-mentioned underlying region exposed through the above-mentioned window, and a polycrystalline layer for an element isolation layer is grown on the above-mentioned mask layer. It is characterized by

In other words, in the method for manufacturing a semiconductor device of the present invention, during the growth process of a semiconductor layer for forming a semiconductor element, which is performed after forming a mask layer, a layer growth process suitable for the structure of the semiconductor element is performed. This method includes the step of simultaneously and selectively growing a polycrystalline layer for element isolation on the semiconductor element forming layer and the mask layer above the region exposed through the window of the layer.

(Function) The semiconductor device of the present invention includes an element isolation layer made of a polycrystalline layer. The resistance value of this polycrystalline layer is much higher than that of the semiconductor element forming layer. Furthermore, the heat resistance of this polycrystalline layer is extremely superior when compared to that of resins such as polyimide.

Further, since this polycrystalline layer is made of the same material as the semiconductor element forming layer, the semiconductor element and the element isolation layer have substantially the same properties such as thermal expansion coefficient. Therefore, the element isolation layer made of polycrystalline layers has excellent reliability.

Further, according to the method for manufacturing a semiconductor device of the present invention, the base layer,
A semiconductor element forming layer is grown above the region exposed through the window of the mask layer. Therefore, the shape and arrangement of the semiconductor element can be specified by the window shape and arrangement of the windows in the mask layer.

Furthermore, it is possible to selectively grow a semiconductor element forming layer above the underlying region exposed through the window of the mask layer and a polycrystalline layer on the mask layer in the same layer growth process. Therefore,
Each semiconductor element is reliably isolated electrically and optically.

(Example) Hereinafter, an example of a semiconductor device of the present invention and a method for manufacturing the same will be described with reference to the drawings. It should be noted that these drawings are only schematic representations to the extent that the present invention can be understood, and the dimensions, shapes, and arrangement relationships of each component are not limited to the illustrated examples.

Further, the following embodiments will be explained using an example in which a semiconductor device is, for example, an integrated light emitting device.

It is also possible to integrate GaAs-based optical devices and Si-based electronic devices by crystal-growing a GaAs layer on a Si substrate, which is inexpensive, has excellent strength, has high thermal conductivity, and is available in large sizes. (For example, literature: Applied Physics Letters (Appli
ed Physics Letters), 44 [
10] (1984) P, 967-969, or Nikkan Kogyo Shimbun September 25, 1985, “High-performance electric power FE
TJ). Therefore, this embodiment will be explained using an example in which a Si substrate is used as the base component so that an integrated light emitting device with excellent heat dissipation effect can be obtained. First, the structure of the integrated light emitting device according to the present invention will be explained. .

FIG. 1 is a sectional view showing a main part of an integrated light emitting device according to the present invention, and hatching indicating the cross section is omitted to avoid complicating the drawing.

In FIG. 1, reference numeral 11 indicates a base, and in this embodiment, the base 11 is an n-type Si (silicon) substrate 13 and an n-type GaAsM 15 grown on this n-type silicon substrate 13.
It consists of: When the base has such a configuration, the heat from the light emitting elements formed on the base can be efficiently radiated by the Si substrate, which has a higher thermal conductivity than the GaAs substrate.

Further, on the upper side surface of the underlying n-type GaAs layer 15, a mask layer 19 is provided, each having a window 17 at a plurality of desired light emitting element forming positions. Also, multiple windows 1 in the base
On the upper side of the area exposed by 7, a semiconductor element forming layer 21 which will become a light emitting element is placed at a thickness of 1. An n-type GaAs single-crystal layer 23 and an n-type AlG
It is composed of an aAs single crystal layer 25 and a p-type Aj2 Ga As single crystal layer 27.

Further, a polycrystalline layer 29 is provided above the mask layer 19 as an element isolation layer for electrically and optically isolating each light emitting element 21, and in this embodiment, this polycrystalline layer 2
9 are provided in order from the mask layer 19 side.
As polycrystalline layer 31 and n-type AJ2 Ga As
It is composed of a polycrystalline layer 33.

Therefore, a wafer structure is obtained that includes a plurality of light emitting elements on the base 11 and a polycrystalline layer between these light emitting elements.

In addition, in this wafer structure, in order to prevent leakage current and leakage light from each light emitting element and improve the characteristics of the element, n
Type AjlG a As single crystal layer 25 and p type AM G
It is preferable that the position of the bonding surface of the a As single crystal layer 27 from the base is substantially the same as the position of the upper surface of the p-type AitGa As polycrystalline layer 31 from the base. Also, the problem of step coverage (details will be explained later)
In order to reduce this, it is preferable to configure the upper surface of the p-type AlGaAs single crystal layer 27 and the upper surface of the n-type J2GaAs polycrystalline layer 33 to form a substantially continuous flat surface.

Further, an insulating film 37 having a plurality of connection windows 35 at predetermined positions for connecting a partial surface region of the p-type AIL GaAs single crystal layer 27 of each light emitting element and a p-type electrode (described later) is provided.
It is provided over the surface of the p-type AfLGaAs single crystal layer 27 and the surface of the n-type AfiGaAs polycrystalline layer 33, which are the above-mentioned continuous flat surfaces.

Further, a p-type electrode 39 is provided on the insulating film 37, and an n-type electrode 41 is provided on the lower surface of the silicon substrate 13 to constitute this integrated light emitting device.

Next, an example of a method for manufacturing an integrated light emitting device according to the present invention will be described with reference to FIGS. 2(A) to 2(E). In these figures, the same components as in FIG. 1 are designated by the same reference numerals.

First, by metal organic chemical vapor deposition (MOCVD), n
Epitaxial n-type GaAs layer 15 on type St substrate 13
is formed to a layer thickness of several μm. Next, a nitride film or an oxide film is formed on the GaAs layer 15 by a suitable method.
After forming a film to a thickness of 1,000 mm, windows 17 are formed in each of the regions where a plurality of light emitting elements are to be formed using photolithography and etching techniques to obtain a wafer structure as shown in FIG. 2(A). Note that through this window 17, a part of the base 11 is exposed, and a mask layer 19 can be formed using the remaining film portion.

Next, a base layer 1 including a mask layer 19 is formed by MOCVD.
A GaAs single crystal layer is grown on 1. In this growth step, the GaAs layer does not substantially grow on the mask layer 19. Therefore, the GaAs single crystal layer 2 is selectively formed to a desired thickness only on the region of the base 11 exposed by the window 17.
3 can be grown. In this example, Ga
The thickness of the As single crystal layer 23 was approximately 1 μm.

Next, the mixed crystal ratio of A2 was set to about 0.4, and MOrυn
The m length of the hook AD('', mouth Δq(1)) is performed with Sr±t''#ray.In the growth process with such a mixed crystal ratio, the AiGaAs layer is formed on the mask layer 19. Therefore, the n-type AJ!GaAs single crystal layer 25 can be selectively grown only on the GaAs single crystal layer 23 (FIG. 2(B)). In this embodiment, the n-type AItGaAs layer 25 is grown at a total pressure of 0.1 to ITorr in the growth tank, and at a temperature of I1 of the raw material.
The crystal growth was performed under conditions where the 1/V ratio was set to 10 to 30 in terms of molar ratio. Moreover, this n-type AI1. The GaAs layer 25 was grown to a thickness of 2 μm.

Next, the mixed crystal ratio of A4 was set to about 0.2 to 0.3, and M
An n-type AILG a As layer is grown by OCVD. In the growth process with such a mixed crystal ratio, the base 1
1, p-type AMGaA is formed on the n-type ILG a As single crystal layer 25 corresponding to the upper side of the region exposed from the window 17.
The s-layer grows as a single crystal, while the p-type AILGaAs layer grows as a polycrystal on the mask layer 19. Also, n
Type AJ! Ga-As single crystal layer 25 and p-type +II G
The a As single crystal layer 27 constitutes a pn junction that contributes to light emission of the light emitting element. In this way, in the same layer growth process, p-type AItGa, which is a part of the light emitting element forming layer,
The As single crystal layer 27 can be grown on the upper side of the region exposed through the window 17 of the base 11, and the p-type lGaAs polycrystalline layer 31 as an element isolation layer can be selectively grown on the mask layer. I can do it.

Furthermore, in this growth process, p-type A is formed on the mask layer 19.
The iLGaAs polycrystalline layer 31 grows at a faster rate than the p-type AnGa
This is faster than the growth rate of the As single crystal layer 27. Therefore, in this embodiment, if the p-type A1GaAs polycrystalline layer 31 is grown to a thickness of about 3 μm, the P-type I
The upper surface of the tG a As polycrystalline layer 31 and the above-mentioned p-n junction surface are at the same position, so the second
A wafer structure as shown in Figure (C) can be obtained.

Next, a mask pattern 43 made of, for example, a nitride film is formed only on the p-type AiLG a As single crystal layer 27 by a suitable method.

Next, the mixed crystal ratio of A2 is changed to P type A4 Ga As layer 27
The mixed crystal ratio is made smaller than the mixed crystal ratio of
As step r, an n-type AlGaAs layer is grown on the wafer including the mask pattern 43 by MOCVD. In this growth step, n-type Af1. The G a As layer grows as a polycrystal, while it does not substantially grow on the mask pattern 43 . Therefore, n-type AJ2 is formed only on p-type JIGaAs polycrystalline layer 31.
The GaAs polycrystalline layer 33 can be selectively grown. Note that the growth of this n-type IlGaAs polycrystalline layer 33 is performed when the upper surface of this layer 33 is p-type AfLG.
By growing the aAs single crystal layer 27 to the same height as the upper surface thereof, a wafer as shown in FIG. structure can be obtained. If such a flat surface is configured, for example, these layers 27 and 33,
A p-type electrode 3 formed on these layers with an insulating film 37 interposed therebetween.
The problem of step coverage when performing insulation with 9 can be reduced.

Next, the mask pattern 43 is removed, and then, for example, a nitride film is formed on the wafer by a suitable method. next,
In order to expose a part of the p-type/l GaAs single crystal layer 27 of each light emitting element, a connection window 35 is formed in this nitride film, and an insulating film 37 is formed using the remaining nitride film. A wafer structure as shown in FIG. 2(E) is obtained.

Next, a connection window 3 is formed on this insulating film 37 by, for example, vapor deposition.
A P-type electrode 39 made of, for example, Zn--Au is formed to be connected to the p-type AnGaAs layer 27 via 5.

Further, on the lower side of the Si substrate 13, for example, Au-Ge-N
By forming an n-type electrode 41 consisting of i, an integrated light emitting device according to the present invention as shown in FIG. 1 can be manufactured.

Although the above-mentioned embodiments have been described under specific preferred conditions within the scope of the present invention, they are merely illustrative, and it is clear that the present invention is not limited only to these embodiments. be.

For example, the embodiments described above are based on metal-organic vapor phase epitaxy.
Bantoguchi sweat passing away (U; ÷ 1! Shih (mouth Hikyu h\1.
A semiconductor device using 1GaAs and 8ILGaAs and a method for manufacturing the same have been described. However, the present invention may be applied to any crystal growth technique and crystal material that allows selective growth and allows growth of a polycrystalline layer having a high resistance value on a mask layer.

For example, as a crystal growth technique, molecular beam epitaxial growth (
The same effect as in the example can be expected even when using the MBE method and setting the growth conditions to conditions suitable for this MBE method. or,
Crystal materials include InP, InGaP, and 1nGa.
AsP type etc. can be considered.

It is also possible to use the n-type Si substrate in the above-mentioned embodiment as a p-type Si substrate and make the conductivity type of each layer the opposite conductivity type. is used, the n-type GaA shown in the example is provided on this substrate.
The s-layer 15 becomes n-type due to the diffusion of Si into this layer. Therefore, when a p-type Si substrate is used, it is necessary to consider, for example, the position where the p-type electrode is provided.

Further, in the above-mentioned embodiment, the base is made of n-type Si and n-type GaAs.
Although the explanation has been given on an example in which the base is made of a GaAs substrate, the effects of the present invention can be expected even if the base is made of a GaAs substrate, although the heat dissipation effect is reduced. In this case, it is possible to form a semiconductor device without providing the n-type GaAs layer 15 used in the embodiment. Furthermore, the conductivity type can be easily changed to the opposite conductivity type to that in the embodiment.

Further, in the above-described embodiments, a part of the semiconductor element forming layer and a polycrystalline layer are grown in the same layer growth process. However, it is also possible to consider an application in which, for example, the semiconductor element formation layer is a single layer, this layer and a polycrystalline layer are grown in the same layer growth process, and then, for example, an FET or the like is manufactured in this semiconductor formation layer. . The present invention also applies to other semiconductor devices such as the above-mentioned FET, as well as rectifying diodes,
Alternatively, it is also possible to apply the present invention to a semiconductor device in which a large number of pin photodiodes and the like are integrated. Furthermore, the present invention may of course be applied to a semiconductor device in which many types of semiconductor elements are integrated on the same substrate.

(Effects of the Invention) As is clear from the above description, according to the semiconductor device of the present invention, the element isolation layer is composed of a polycrystalline layer made of substantially the same material as the material constituting the semiconductor element. . Therefore, the properties such as heat resistance of the device isolation layer according to the present invention are extremely superior when compared with conventional device isolation layers using polyimide. Therefore, a semiconductor element with excellent reliability can be obtained.

Further, according to the method of manufacturing a semiconductor device of the present invention, the shape and arrangement of the semiconductor element can be specified by the window shape and arrangement of the windows in the mask layer.

Moreover, the patterning of this mask layer can be performed with high precision using a conventional photoetching technique.

Furthermore, it is possible to selectively grow a semiconductor element forming layer above the underlying region exposed through the window of the mask layer and a polycrystalline layer as an element isolation layer on the mask layer in the same layer growth process.

Therefore, it is possible to provide a method for easily manufacturing a semiconductor device including a plurality of semiconductor elements accurately arranged and formed in a desired shape and a highly reliable element isolation layer between these elements.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a main part of an integrated light emitting device which is an example of a semiconductor device of the present invention, and FIGS. It is a manufacturing process diagram when used as an integrated light emitting device. 11--base, 13-n-type Si substrate 15
---N-type GaAs layer, 17-...Window 19...Mask layer 21-...Semiconductor element forming layer (light emitting element) 23...n
Type GaAs single crystal layer 25--n type Aj2GaAs single crystal layer 27-p type AI
LG a As single crystal layer 29 --- element isolation layer 31 - p-type AILG a As polycrystal layer 33 ---n
Type AJ! GaAs polycrystalline layer 35--connection window,
37--Insulating film 39-p-type electrode, 41-n
Type electrode 43--mask pattern. Patent applicant Oki Electric Industry Co., Ltd. tI: Shimoji
3/: P type A Kei, Asri introduction ^ layer/3: '72 type S+:, Curtain plate 3371 type Ae6LAS9
) mrBfits:'rt type Shin As1i, 3
5: #Seho I7: Winter Mi
37. Li color engetsu mo/'? , 77.71t
R-P"l electric ni 2I: Sato conductor industry TE type layer 4/: n-type electric yuzu 23, n-type craAs '4
'A Xilin 25: '7L Current IAleaAs Gakushui 27:
P type AI Cra ha 5 single 1g 5,42q knee! i, 5 i)・□(1) Akira (l Tsuta S 啄-1) I-kei Arisanzai 1 for this invention! Hikari t+'s UgN Hoko & 1 figure this! @lni β calculation 1 ro 5
Figure 2: Craftsmanship of treadmills, country of non-existence

Claims (2)

[Claims] (1) In a semiconductor device comprising a plurality of semiconductor elements provided on the same substrate and an element isolation layer provided between these semiconductor elements to isolate each semiconductor element, the element isolation layer is formed using a polycrystalline layer. What is claimed is: 1. A semiconductor device comprising: (2) When manufacturing a semiconductor device including a plurality of semiconductor elements provided on the same substrate and an element isolation layer provided between these semiconductor elements to separate each semiconductor element, a plurality of windows are provided on the substrate. In the same layer growth step, all or part of the semiconductor element formation layer is formed above the region of the base exposed through the window, and a polycrystalline layer for element isolation layer is formed on the mask layer. A method of manufacturing a semiconductor device, the method comprising growing a semiconductor device.