JPS62209793A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent the erroneous recognition of input binary information without having an influence upon a supply voltage and an earth voltage by giving a control signal to individual output means through delay means different in delay time. CONSTITUTION:In the read mode, the control signal is supplied from a control circuit 8 to delay circuits 21 simultaneously, and circuits 21 send the delay control signal to corresponding input/output circuits 7 at intervals. Even if plural cell information are all '1' or '0', currents are not conducted simultaneously through pMOSFETs Q1 or nMOSFETs Q2 as the result, and erroneous discrimination of address signals Axi and Ayi, external control signals CS, OE, and WE, etc., is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, such as a random access memory device, which outputs a plurality of output binary information in parallel.

[Conventional technology]

A conventional output circuit of this type includes one shown in FIG. 2, for example. In the figure, 1 indicates a semiconductor substrate, and in order to access any memory cell of a memory cell array 2 formed on the semiconductor substrate 1, an address signal Axi is sent to an address buffer 3 via an address terminal a. to form internal address signals Axi' and Axi'. These internal address signals Axi' and Ax
i' is decoded by the X decoder 4 and becomes a word line selection signal xj.

When a word line is selected by the word line selection signal xj,
Subsequently, the address signal Ayi is supplied to the address buffer 5 via the address terminal, and the address signal Ay i
Internal address signals Ayi' and Ayi formed based on
' is supplied to the X decoder 6. The X decoder 6 turns on the switch transistors s and s' based on the internal address signals Ayi' and Ayi', and outputs the address signal Ax i
, Ay i outputs the cell information stored in the memory cell designated by i to the data buses DBi and DBi.

The cell information thus read out is supplied in parallel to each individual's output circuit 7, and simultaneously outputted to the outside by control signals supplied from the control circuit 8 to each input/output circuit 7 at the same time. Here, the input/output circuit 7 is composed of complementary MOS transistors as shown in FIG. 3, and when outputting binary information rOJ, the p-channel MOS transistor Ql is always turned off. , n-channel MO
The S transistor Q is turned on or off based on the output control signal, and when outputting binary information "1", the p channel transistor Q is turned off while the n channel transistor Qz is turned off.
Turns on or off OS transistor Ql.

[Problem that the invention seeks to solve]

In the above conventional example, control signals are simultaneously supplied to each input/output circuit 7, and the p-channel MOS of the input/output circuit 7
Transistor Q1 or n-channel MO8) Transistor Q! on or off at the same time. Therefore, when the binary information to be output is all "0" or "1", the p-channel MOS transistor Qs or the n-channel MOS transistor Q are turned on simultaneously. Therefore, a large current flows from the stain source Vss to the external load circuit or from the external load circuit to the ground terminal GND due to the transistor Q1'l: or Q2 being turned on. Since the parasitic capacitance (isometrically represented by rCJ in FIG. 2) of the MO8I-transistor constituting each of the above circuits exists between the power supply Vss and the ground terminal GND, there is no risk of staining due to the large current. When the source voltage decreases or the ground voltage increases, the ground voltage or power supply voltage also fluctuates, and based on the values of the power supply voltage and the ground voltage, the address signal Ax i ,
There is a problem in that misidentification is likely to occur when determining the value of Ay i.

Therefore, it is an object of the present invention to provide an output circuit that does not affect the power supply voltage and ground voltage.

[Means, operations, and effects for solving the problem] In the output circuit according to the present invention, the plurality of output means are each provided with delay means having different delay times, and each control signal is outputted through the delay means. Since the information is sent to the output means, each output means does not output binary information at the same time, but sequentially outputs binary information at intervals. Therefore, if a plurality of output binary information are all "1" or r
Even with OJ, the reference potential and ground potential will not fluctuate due to the influence of a sudden large current. As a result, it is possible to obtain the effect that even when input binary information is discriminated with reference to the reference potential and the ground potential, there is no misidentification.

〔Example〕

FIG. 1 shows an embodiment in which the present invention is applied to a random access memory, and the same components in FIG. 1 as those in FIG. 2 are denoted by the same reference numerals, and the explanation thereof will be omitted. In the figure, 21 indicates a delay circuit provided corresponding to the input/output circuit 7. These delay circuits 21 may constitute the delay means of the present invention, or a plurality of delay circuits 21 may constitute the delay means. may be configured. In the read mode, control signals are supplied from the control circuit 8 to each delay circuit 21 at the same time, and after application of the control signal, the valley delay circuits 21 send out delay control signals to the corresponding input/output circuits 7 at intervals. As a result, all the multiple cell information to be output are "1"
Or even if it is "0", the current does not flow all at once through the p-channel MO8) transistor Q or the n-channel MO8) transistor Q2, and no large voltage fluctuation occurs in the power supply voltage and the ground voltage. As a result, address signals Ax i , Ay i and external control signals C8,
This eliminates the possibility of erroneously determining OE, WE, etc.

Furthermore, the present invention can be used not only as a random access memory but also as an output circuit for a microprocessor or the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional example, and FIG. 3 is an electric circuit diagram of each input/output circuit.

Claims (1)

[Claims] A plurality of output means for outputting a plurality of output binary information corresponding to the reference potential or the ground potential in parallel in response to a control signal based on the input binary information determined with reference to the reference potential and the ground potential. In the output circuit, each of the plurality of output means is provided with delay means having different delay times,
An output circuit characterized in that a control signal is sent to each output means via the delay means.