JPS62208132A - Electronic computer - Google Patents

Abstract

PURPOSE:To execute processing required for message sending within a short period and to improve the execution speed of small talk by changing the sequence of a microprogram when a method is to be found out during the execution of a program. CONSTITUTION:When a message sending is generated during the execution of small talk 80 after initializing a method cache and the method is to be found, the contents of a receiver are written from an ALU 110 to a receiver register 201 and a selector register 202 through a bus Y 107 and a hush circuit 206 hushes the receiver and selector and adds the hushed contents to an address line of a memory 217. The output of the register 201 is compared with the output receiver of the memory 217 by a comparator (1) 209, the contents of the register 202 is compared with the output selector of the memory 217 by a comparator (2) 210, and at the time of coincidence, '1' is outputted respectively. The memory 217 simultaneously outputs a method, an index and an effective flag. At the time of reading the method, the index is outputted to a bus 103 to control the execution sequence of a microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to computers running object-oriented languages, and more particularly to hardware method caching in Smalltalk-80 special purpose computers.

(Prior art) In recent years, in the field of electronic computers, object-oriented languages (objects with values and procedures as internal states) are being used instead of procedure-oriented languages (programs are written using procedures), which have traditionally been widely used. It has been proposed to use Smalltalk-80 is known as a typical object-oriented language. For more information on this, please refer to the following literature: Small Talk-80: The Language and Germans Implementation, Addison-Wesley, 11371, May 1983.
k-80: THE LANGUAGE AND I
TS IMPLE-MENTATION, ADDISO
N-WESLEY11371゜May 1983).

FIG. 4 is a block diagram showing an example of the configuration of a computer for executing Smalltalk-80. In the figure, a sequencer 101 is connected to a C bus 102 and an N bus 103, and a micro program memory 104 is connected to a C bus 102 and an N bus 103.
and C bus 102. Register AIO3 is connected to A bus 106 and Y bus 107, and register B108
is connected to B bus 109 and Y bus 107.

ALUllo has A bus 106, B bus 109, and Y pass 1.
07 and N bus 103. Also, C bus 102
From register AIO3, register B108, ALU
Connected to llo. Memory interface 111 is connected to A bus 106, Y bus 107, and external bus 112. Memory 113 is connected to external bus 112.

A control unit 114 controls the entire computer.

Next, to operate this computer, a three-phase clock as shown in FIG. 5 is supplied from the control section 114 to the entire computer. The computer operates in synchronization with this clock. The three-phase clocks are CLKI and CLK2.

When expressed as CLK3, the difference between CLKI and CLK2 is set to 20% of the clock period. The difference between CLK2 and CLK3 is also set to 20% of the clock cycle. pipeline·
As the timing within the stage, the rising edge of CLK2 is
o, C'LK3 rising 9 is T1, CLKI falling 9 is T1
2. T3 is the falling edge of CLK2, T4 is the falling edge of CLK3.
, CLKI start-up time is defined as T5, and CLK2 start-up time is defined as T6. FIG. 6 is a diagram showing the time relationship of this entire configuration. First, the sequencer 101 outputs the address of the microprogram to the N bus 103 from To to T4 in the first stage. The N bus 103 is an open collector bus and has negative logic. From T4 of the 1st stage to To of the 2nd stage, N bus 10
3 always remains in the "0" state. The micro program memory 104 receives the micro program address from the N bus 103 and starts accessing the memory.

The micro program memory 104 transparently latches the micro program address at the timing from T1 to T3, and holds it until T1 of the second stage. The micro program memory 104 stores the micro instructions obtained as a result of memory access at T3 in the first stage.
It is output to the C bus 102 from T1 to the second stage.

The C bus 102 is a three-state bus, and TI to T3 are in a high impedance state, allowing output from a plurality of micro program memories 104. Next, the register A 105 registers the C bus 1 at the timing from T3 of the lth stage to To of the second stage.
Transparently latch the contents of 02. C bus 10
2 C, it is confirmed at T5 of the lth stage. If the latched microinstruction specifies the output from register A 105, register AlO3 performs memory access from T5 in the first stage to T1 in the second stage, and from TO to T4 in the second stage. The obtained data is output to the A bus 106.

Similarly, register B108 is 2 from T3 in the first stage.
The contents of the C bus 102 are transversely latched at the timing of To in the second stage. If the latched microinstruction specifies output from register B108, then
Register B108 performs one stage of memory access at T5.
to T1 of the second stage, and the data obtained from TO to T4t of the second stage is transferred to the B bus 109.
Output to. Next, if specified by a microinstruction, AL
The UIIO transversely latches the contents of the A bus lO6 and the B bus 109 at the timing from T1 to T3t of the second stage, and performs an ALU operation. The calculation is performed at T2''! of the third stage, the result is latched,
Y from T2 of the 3rd stage to T6 of the 3rd stage
Output to bus 107. The Y path 107 is a three-state path, and is in a high impedance state from 9.To to T2, allowing output from a plurality of arithmetic units. Similarly, the A bus 106 and B bus 109 are three-state paths, and are high from T4 to the next TO.
In the impedance state, output from multiple registers is allowed. The ALU 110 outputs the result condition flag of the operation to the N path 103. The output timing is between TO of the third stage and T4. On the N path 103, the address of the microprogram from the sequencer 101 and the condition flag from the ALU 110 are wired ORed to perform condition skipping. When writing data to the memory 113 connected to the external path 112, the memory interface 111
receives address information and data to be written from the Y bus 107 and outputs it to the external bus 112.

When reading data from a memory or the like connected to the external bus 112 , the memory interface 111 receives address information from the Y bus 107 and outputs it to the external bus 112 . The memory interface 111 receives and receives data obtained as a result of memory access through the external bus 112 and outputs it to the A bus 106. The timing is as described above. Note that an example of an external bus is V
Examples include ME bus.

To execute Smalltalk-80 at high speed, a method cache is required to find the method to be actually executed from the message receiver and selector. The method cache is a table of about 1 to 4 words and is placed on external memory. Since the keys of the table are the receiver and selector, each having a length of about 16 bits, they are shortened to 10 to 12 bits using a hash function and point to one entry in the table. For example, the entries in the table are receiver, selector, method, primitive index, receiver as key, selector and receiver in two entries, if the selector matches, it is a human, method, primitive index. is valid. On the other hand, if they do not match, another method must be used to find the brimmy tape index. Conventional Smalltalk-8
The 0-only electronic computer achieved the above operations using microcode.

(Problem to be Solved by the Invention) However, in the device with the above configuration, it takes several tens of microinstruction steps and several memory accesses to obtain the method and brimitage index from the receiver and selector, which takes time. However, this has become a bottleneck in running Smalltalk-80.

The present invention eliminates the disadvantage of the method described above that it takes time to obtain a primitive index, and
The purpose of the present invention is to provide an electronic computer that can execute malltalk-80 at high speed.

(Means for Solving the Problems) The present invention is directed to an electronic computer that executes an object-oriented language, and in order to solve the problems of the prior art described above, the present invention provides a first means for maintaining a receiver that can be written directly from a microprogram. a second means for holding a selector that can be written directly from the microprogram; a third means for hashing the receiver from the first means and the selector from the second means and outputting it as a pointer; a fourth means that has a cache table for registration and outputs the receiver, selector, method, index, and valid flag using the pointer of the third means; and a fourth means that outputs the method from the fourth means to the path. a sixth means for comparing the receiver from the fourth means and the receiver from the first means; and a sixth means for comparing the selector from the fourth means and the receiver from the second means. an eighth means for performing a logical operation on the valid flag from the seventh means, the output of the sixth means, and the output of the seventh means;
a ninth means for controlling the sequence of the microprogram by outputting an index to the microprogram bus according to the calculation result of the eighth means; and a fourth means for outputting the receiver, selector, method, index, and valid flag from the microprogram to the microprogram bus A method cache consisting of a tenth means for simultaneously writing to the first means is provided.

(Function) When a message send method is requested during program execution, the first
A receiver is written in the first means, a selector is written in the second means, and both are held. The third means receives the receiver of the first means and the selector of the second means, hashes them, and outputs them as a pointer to the fourth means. The fourth means outputs an entry corresponding to the pointer from the third means, and the fifth means outputs the method among them to the bus. On the other hand, the sixth means compares whether the receiver from the first means and the receiver from the fourth means match. The seventh means compares whether the selector from the second means and the selector from the fourth means match.

The eighth means performs a logical operation on the output of the sixth means, the output of the seventh means, and the valid flag from the fourth means. For example, when the logical sum of the eighth means is "1", the ninth means
The means output the index to the microprogram bus and change the sequence of the microprogram. In addition, when the logical sum of the eighth means is O'', it means that no method or index is registered in the fourth means, so the tenth means is a receiver, selector, method, index, valid The flags are written to the fourth means at the same time.Through the above, it is possible to perform the necessary processing for message sending in a short time.
malltalk-80 can be executed at high speed. Therefore, the problems of the prior art described above are solved.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing in detail the structure of a method cache, which is a characteristic part of the computer of this embodiment, and FIG. 2 is a schematic block diagram of the computer of this embodiment. First, the overall configuration of the Miko computer will be explained with reference to FIG. A sequencer 101 is connected to a C bus 102 and an N bus 103, and a micro program memo! J104 is N bus 10
3 and connected to the C bus 102. Register AIO3 is connected to A bus 106 and Y path 107, and register B1
08 is connected to the B bus 109 and the Y path 107. A
L U 110 is A bus 106, B path 109,
It is connected to the Y path 107 and the N bus 103. Also, C
From the bus 102, register AlO3, register B1
08, connected to ALU 110.

Memory interface 1111dA bus 106,
It is connected to Y bus 107 and external bus 112. Memory 113 is connected to external bus 112. A control section 114 controls the entire system. method cache 1
15 is A bus 106, Y bus 107, C bus 1
02 and N bus 103. Everything except the method cache 115 is the same as a conventional electronic computer.

Next, the internal structure of the method cache 115 will be explained in detail based on FIG.

As shown in FIG. 1, a method cache 115,
Receiver register 201, selector register 202, driver 203, method register 204, multiplexer (1) 205, hash circuit 206, driver 20
7゜208, comparator (1) 209, (2)
210, drivers 211 and 212, multiplexer (2) 213, AND gate 214, open collector NAND driver 215, driver 216, memory 217, and controller i18. Regarding the connection relationship between each element, the Y bus 107 is connected to one input of the multiplexer (1) 205 and the input of the driver 203. A portion of the Y path 107 excluding the LSB is connected to each input of a receiver register 201, a selector register 202, and a method register 204. One input of the output hash circuit 206 of the receiver register 201, the input of the driver 207, and the comparator (1) 20
9, respectively. The output of the selector register 202 is the other input of the hash circuit 206, the input of the driver 208 and the comparator (2) 210.
are connected to one input of each. Hash circuit 2
The output of 06 is connected to the other input of multiplexer (1) 205. The output of multiplexer (1) 205 is connected to the address line of memory 217. The output of driver 207 is connected to the other input of comparator (1) 209 and to the I10 line of memory 217. The output of driver 208 is connected to the other input of comparator (2) 210 and to the I10 line of memory 217. The output of driver 203 is connected to the I10 line of memory 217 and one input of open collector NAND driver 215.

The output of method register 204 is connected to the driver 2110 input. The output of driver 211 is connected to the I10 line of memory 217 and the input of driver 216.

The output of driver 216 is connected to A-path 106.

Driver 216 always has rlJ on the LSB of A bus 106.
Output. The inputs of multiplexer (2) 213 are "0" and "1", respectively. Multiplexer (2) 21
The output of 3 is connected to the input of driver 212. The output of the driver 212 is ANDed with the VO line of the memory 217)
214. Comparator (1
) 209 is connected to the second input of AND gate 214. The output of comparator (2) 210 is AND
Connected to a third input of gate 214. AND game)
214 output is open collector NAND driver 2
15 is connected to the other input. The output of oven collector NAND driver 215 is connected to N path 103. A control unit 218 controls the entire method cache.

Next, the operation will be explained. First, to initialize the method cache, multiplexer (1) 205
to the Y bus 107 side, and multiplexer (2) 2
13 to the "0" side. Next, address O is applied from ALUIIO to the address line of memory 217 through Y path 107 and multiplexer (1) 205. next,
A write pulse is applied to memory 217 to activate driver 212 and write a "0" to the valid flag pit. In other words, the entry becomes invalid. memory 2
17 address from O to the end of the table entry, "0" is written to the valid flag bit in the same way as above, invalidating all entries in the table.

Next, while running Small talk-80, I received a message.

When a send occurs and a method is requested, the memory 217 is always in an active state and outputs data to the I10 line. Driver 207, driver 208, driver 203, driver 211, and driver 212 are disabled. Multiplexer (1) 205
selects the hash circuit 206 side.

First, the receiver is written into the receiver register 201 from the ALU 110 via the Y bus 107. Next, A.L.
The selector is written from Ullo to the selector register 202 via the Y bus 107. The writing timing is T5 of the third stage (see FIG. 6).

The hashing circuit 206 hashes the receiver, selector, and the memory 2 through the multiplexer (1) 205.
Add to address line 17. Figure 3 shows the hashish circuit 20.
FIG. 6 is a diagram showing an example of No. 6; In the example shown in FIG. 3, the receiver and selector are 16 bits, the cache table size is 4 words, and the address output to multiplexer (1) 205 is 12 bits. Memory 217 outputs the entry corresponding to the added address to line I10. Comparator (1) 209 is receiver register 20
The output of "1" is compared with the receiver output from the memory 217, and if they match, "1" is output. Comparator (2) 210 compares the output of selector register 202 and the selector output from memory 217, and outputs "1" if they match.

If both do not match, "0" is output.

At the same time, the memory 217 is outputting the method, index, and valid flag.

When reading a method from the method cache 115 using a microinstruction, from To to T4 in the second stage
Activate the driver 216 until the memory 21
The method from 7 is output to the A bus 106. Since the method is a pointer, rOJ is always output to the LSB of the A bus 106. At the same time as outputting the method to the A bus 106, the AND gate 214 outputs the valid flag from the memory 217 and the output of the comparator (1) 209.
Comparison (2) AND with the output of 210 is performed, and if the result is "1", the index is output from the open collector NAND driver 215 to the N bus 103 to control the execution sequence of the microprogram. The index is, for example, about 12 bits. The index is output to the N bus 103 between TO and T4 in the second stage.

On the other hand, when the output of the AND gate 214 is "0", the method is stored in the method cache 115.

Since the index was not registered, it is necessary to find a method and index using another method and register it in the cache table.

The method and index are determined by the microprogram, and the method is first written into the method register 204. The writing timing is T5 of the third stage. Next, the input of multiplexer (2) 213 is switched to the "1" side, the index is output from ALUIIO to Y bus 107, and at the same time a write pulse is applied to memory 217, driver 207, driver 208, driver 203,
Activate driver 211 and driver 212,
Write receiver, selector, method, index, and valid flag = 1 at the same time. The writing timing is 3
This is stage T5. Once written, the entry is valid, and when a method or index is later requested by the same receiver or selector, the method or index can be obtained as described above.

Although one embodiment of the present invention has been described in detail above,
According to this embodiment, the method cache can be directly controlled from the microprogram, and it can be determined in a short time whether or not the desired method and index are registered in the table using the hash circuit 206 and the comparators 209 and 210. Furthermore, by widening the index information to 12 bits and storing not only the primitive index but also the number of arguments, the number of temporary variables, the size of the context, etc., it is possible to quickly send messages in a short time. processing. Therefore, this embodiment is small.
k-80 can be executed at high speed.

(Effects of the Invention) As described in detail above, according to the present invention, it is possible to obtain a method and a brimmy tape index in a short time, so it is possible to provide a computer that can execute Smalltalk-80 at high speed. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of a method cache in an embodiment of the present invention, FIG. 2 is a block diagram showing the overall structure of an embodiment of the present invention, FIG. 3 is an explanatory diagram of a hash circuit, 4 is a diagram showing the configuration of a conventional Smalltalk-80 execution computer, FIG. 5 is a diagram showing a three-phase clock used in the computer shown in FIG. 4, and FIG.
FIG. 3 is a diagram showing bus timing according to a microprogram in the computer shown in the figure. 101...Sequencer, 102...C bus, 103
...N bus, 104...Micro program memory, 105...Register A, 106...N bus, 107...Y bus, 108...Register B,
109...B bus, 110...ALU. 111...Memory in and ace, 112...External bus, 113...Memory, 114...Control unit, 11
5... Method cache, 201... Receiver register, 202... Selector register, 203...
・Driver, 204...Method register, 205・
...Multiplexer (1), 206...No.1 switch circuit, 207, 208...Driver, 209, 21
0... Comparator (1), (2), 211,
212... Dry node, 213... Multiplexer (2), 214... AND gate, 215... Open collector NAND driver, 216... Driver, 217... Memory, 218... Control unit .

Claims (1)

[Scope of Claims] In an electronic computer that executes an object-oriented language, a first means for holding a receiver that can be written directly from a microprogram, a second means for holding a selector that can be written for directly from a microprogram, and a first means for holding a receiver that can be written directly from a microprogram. and a third means for hashing the receiver from the receiver and the selector from the second means and outputting it as a pointer, and a cache table for registering methods and indexes.
a fourth means for outputting a selector, a method, an index, and a valid flag; a fifth means for outputting a method from the fourth means onto a bus; a receiver from the fourth means and a receiver from the first means; a sixth means for comparing the selector from the fourth means and the receiver from the second means; a valid flag from the fourth means; an eighth means for performing a logical operation on the output and the output of the seventh means; and a ninth means for outputting an index to the microprogram bus according to the operation result of the eighth means and controlling the sequence of the microprogram. and tenth means for simultaneously writing receivers, selectors, methods, indexes, and valid flags from the microprogram to the fourth means.