JPH11306044A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expand a range in which PC trace is possible for the number of PC trace register means. SOLUTION: A data processor includes trace data registers 33a to 33d which successively store branching trace data that specify a branching origin and a branched party when a branching occurs to the instruction execution of a CPU 2, repeat number of times registers 34a to 34d, and control means 30, 31 and 32. The control means 30 to 32 have the repeat number of times registers corresponding to the branching trace data of the previous branching update the number of times data when the branching equal to the previous one occurs and obtains the trace data for another trace data register and initializes the corresponding repeat number of times register when a branching different from the previous one occurs. Even if the same branching is repeated by a repeat instruction or the like, the same trace data are blocked so that they are not stored in new trace data registers 33a to 33d.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to holding branch trace data for obtaining instruction addresses of a branch source and a branch destination when a branch whose instruction execution order is changed by a CPU (Central Processing Unit) occurs. So-called PC
The present invention relates to a data processor having a trace function, for example, to a technique effective when applied to a microcomputer that supports a repeat instruction.

[0002]

2. Description of the Related Art Some microcomputers have a PC trace function for supporting a user debug function on-board. A branch whose instruction execution order is changed by the CPU is caused by a branch instruction, an interrupt, an exception process, a repeat instruction, or the like. When the branch occurs, the PC trace function stores the branch trace data for acquiring the instruction addresses of the branch source and the branch destination in the PC.
This is a debug support function to be held in the C trace register. A plurality of sets of the PC trace registers are provided, and each time a branch occurs, the storage destination register is sequentially changed.

As an example of a document describing the PC trace function, see the Hitachi SH7410 Hardware Manual, 2nd edition (November 1997), pages 186 to 1
Pages 88 and 195-196.

[0004]

However, the conventional PC trace function retains the same branch trace data every time even if the same branch is repeated many times, so that the storage capacity is limited. A certain PC trace register is wasted and a wide range of PC trace cannot be performed.

An object of the present invention is to provide a data processor capable of performing PC tracing over a wide range even when the number of register means is limited.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the data processor is a CPU
And (2) a plurality of trace data registers (33a to 33d) for sequentially storing branch trace data for specifying a branch source address and a branch destination instruction address when a branch whose instruction execution order is changed by the CPU occurs. And a repeat count register (34a to 34d) provided in each of the trace data registers; and controlling storage of branch trace data in the plurality of trace data registers and storing count data in the repeat count register. Control means (30, 31, 32,
30a, 30b). To explain the function of the control means comprehensively, when the occurrence of a branch is detected and the branch is equal to the previous branch, the count data is stored in the repeat count register of the trace data register already having the corresponding branch trace data. Is updated, and when the branch is different from the previous branch, the current branch trace data is acquired in another trace data register, and the corresponding repeat number register is initialized.

As described above, even when the same branch is repeated many times by a repeat instruction or a loop, it is possible to prevent the same trace data from being stored in a new trace data register every time. Therefore,
The trace data register for the PC trace having a limited storage capacity is not wasted. Therefore, it is possible to perform PC trace over a wide range.

The control means (30, 31, 32) according to the first specific mode stores the branch trace data when a new branch occurs in the register means (33a-33d, 3).
4a to 34d), when the value is equal to the branch trace data already stored, the number of branches relating to the match is stored in the corresponding register means instead of acquiring new branch trace data, and a new branch is generated. If the branch trace data at that time does not match the branch trace data already stored in the register means, the register means is changed to acquire new branch trace data.

The control means (30a, 32) according to the second specific mode is adapted to acquire new branch trace data when a new branch is taken and the branch is repeated by execution of a repeat instruction. Instead, the number of branches related to the repeat instruction is stored in the corresponding register means,
If a new branch occurs and the branch is not a repetition by execution of a repeat instruction, the register means is changed to acquire new branch trace data. The second specific mode is that the circuit and function thereof are simplified as compared with the first specific mode in that new trace data input is suppressed only for a repeat instruction.

[0012] The control means (30b, 32) according to the third specific mode further changes the register means when a branch based on an interrupt occurs in the middle of a repeat instruction. To suppress the process of acquiring new branch trace data. According to this, even if an interrupt occurs in the middle of a repeat instruction, trace data is not held in a branch caused by the interrupt. If the processing or the program is normal, when the interrupt processing is completed, the processing of the CPU is returned to the processing at the time of occurrence of the interrupt.
The flexibility of the PC trace is increased in that the range of the C trace can be further expanded.

[0013]

FIG. 6 is a block diagram showing a microcomputer as an example of a data processor according to the present invention. Microcomputer 1 shown in FIG.
Is a single semiconductor substrate (semiconductor chip) made of, for example, single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
Formed. Although not particularly limited, the microcomputer 1 has an internal bus I-Bus and a peripheral bus P-Bus. These buses are provided with data, address, and control signal lines.

A central processing unit (C) is connected to the internal bus I-Bus.
PU) 2, user break controller (UBC) 4,
An X memory 5, a Y memory 6, and a bus state controller (BSC) 7 are connected. The bus state controller (BSC) 7 is connected to the peripheral bus P-Bus. Although not particularly limited, the peripheral bus P-Bus includes an interrupt controller (INTC) 10 and a direct memory access controller (DMAC) 1
1, a free running timer (FRT) 12, a serial communication interface (SCI) 13, a serial interface (SIO) 14, a user debug interface 15, and a system controller 16 are connected. In FIG. 6, reference numerals 17 and 18 denote input / output port circuits. The input / output port circuit 17 is interfaced with an external address bus, data bus and control bus. The input / output port circuit 18 is an external interface circuit for peripheral circuits.

The CPU 2 includes, but is not limited to, an integer unit 20 having an arithmetic and logic unit and a DSP unit 21 having a product-sum operation unit and the like. DS
The P unit 21 is assigned a DSP register 22, and the integer unit 20 is assigned a general-purpose register 23. In addition, a control register 24 is provided in the CPU 2. Instruction control such as instruction fetch and instruction decode in the CPU 2 is performed by the instruction control unit 25. The data fetch necessary for the operation is performed by the data control unit 26 based on a control signal output from the instruction control unit.
The CPU 2 fetches an instruction from an external memory or the like (not shown) and decodes the instruction with an instruction decoder of the instruction control unit 25, thereby performing data processing corresponding to the instruction using the integer unit 20 and the DSP unit 21. Do.

In consideration of the product-sum operation by the DSP unit 21, the X memory 5 and the Y memory 6 have a data path connected to the CPU 2 via dedicated buses X-Bus and Y-Bus. .

The bus state controller 7 has a CP
The bus cycle is controlled by controlling the access data size, the access time, the insertion of the wait state, and the like in accordance with the circuit to be accessed by U2 and DMAC 11 (address area to be accessed).

The microcomputer 1 is operated in synchronization with a clock signal output from a system controller 16. The interrupt controller 10 performs mask processing and arbitration for interrupt requests and exception processing requests from inside and outside the microcomputer 1.

The microcomputer 1 is not a microcomputer dedicated to evaluation but a so-called real chip.
The user break controller 4 and the user debug interface 15 realize a certain debugging function.

The user break controller 4 sets a break condition such as an instruction address and monitors whether the set break condition is satisfied.
Execution of the user program by PU2 is stopped. To stop the execution of the user program, a break interrupt or the like is used. The setting of the break condition is not particularly limited, but the BSC 7 and DMAC
11 is performed.

Furthermore, the user break controller 4
Execution of a branch instruction by PU2 or occurrence of an interrupt
When a branch is generated in the execution instruction of, this is detected, and data (branch trace data) that can specify a branch destination address and a branch source address is generated and output to the outside.
It has a C trace function. The output of the branch trace data is transmitted from the input / output port circuits 17 and 18 to BSC7 and DMA.
This is performed using C11.

FIG. 1 shows a first example of a PC trace circuit for realizing the PC trace function. In the figure, the PC trace circuit includes a shift control circuit 30, a comparator 31, an incrementer 32, trace data registers 33a to 33d, and a repeat number register 34.
a to 34d.

A branch whose instruction execution order is changed by the CPU 2 is caused by a branch instruction, an interrupt, an exception process, a repeat instruction, or the like. The repeat instruction has, as operands, an instruction start address, an instruction end address, and the number of repetitions. When the repeat instruction is executed, the process of branching the execution instruction to the instruction start address and executing the instruction up to the instruction end address is repeated by the repetition number. Such a repeat instruction can increase the efficiency of the repetition of the product-sum operation processing frequently used in digital signal processing. The instruction control unit 25 asserts a branch signal 35 when the branch occurs. That is, in the case of a branch instruction, a branch destination instruction address is output or a branch destination instruction is fetched. In the case of an interrupt, a head instruction address of a processing routine designated by the interrupt is output or the head instruction is fetched. In the case of a repeat instruction, the branch signal 35 is asserted when the instruction start address is output or when the start instruction is fetched.

The trace data registers 33a-33
Reference numeral d denotes a register for sequentially storing branch trace data for specifying each instruction address of a branch destination and a branch source when a branch whose instruction execution order is changed by the CPU 2 has a serial 4-stage shift register format. . In the example of FIG. 1, the branch trace data is the branch destination instruction address and the last executed instruction address before the branch. The repeat number registers 34a to 34d are provided corresponding to the trace data registers 33a to 33d, and similarly have a serial four-stage shift register format. The branch destination instruction address and the last executed instruction address before the branch are not particularly limited.
Output from

A shift register type repeat number register 34a-34d and a trace data register 33a-33
The shift control for the 33d is performed by the shift control circuit 30. The comparator 31 compares the branch destination information stored in the trace data register 33a with the branch destination instruction address.
The information of the branch source stored in 3a is compared with the last executed instruction address before the branch. Comparator 3
A state in which the comparison results of 1 and 2 do not match indicates that the immediately preceding branch has not been repeated. The state in which the comparison results of the two comparators 31 match indicates that the immediately preceding branch is repeated again. In the latter case, a loop is generated by a branch instruction, or the second and subsequent iterations are performed by a repeat instruction. In the former case, the shift control circuit 30
Performs a shift operation of the trace data registers 33a to 33d, and stores new trace data in the first stage. In the latter case, the shift operation by the shift control circuit 30 is suppressed by the signal 36, and instead, the value of the first-stage repeat number register 34a is incremented by one via the incrementer 32.

FIG. 2 shows a flowchart of the control operation by the PC trace circuit shown in FIG. The shift control circuit 30 monitors the instruction control unit 25 (S1) and determines whether the branch signal 35 has been asserted (S2).
When the branch signal 35 is asserted, it is determined whether the signal is repeat,
That is, it is determined whether or not the comparison result by the comparator 31 is a coincidence state (S3). If not, the trace data registers 33a to 33d and the repeat count registers 34a to 34d are shifted (S5), and the branch destination instruction address and the last executed instruction address before branch are stored in the register 33a. The register is reset to 0 (S6). On the other hand, if the result of the determination in step S3 is repeat,
5, the value of the repeat number register 34a is incremented by one without updating the trace data by S6.

Thus, even if the same branch is repeated many times by a repeat instruction or a loop, it is possible to prevent the same trace data from being stored in a new trace data register every time. Therefore,
The trace data register for the PC trace having a limited storage capacity is not wasted. Therefore, it is possible to perform PC trace over a wide range. Figure 7
In the case of the comparative example illustrated in
Since the storage destination register is sequentially changed, even if the same branch is repeated many times, the same branch trace data is held every time. As a result, a PC trace register having a limited storage capacity is wasted.

FIG. 3 shows a second example of a PC trace circuit for realizing the PC trace function. In the figure, the PC trace circuit is different from that of FIG. 1 in that the comparator 31 is omitted, and a shift control circuit 30a for receiving a repeat execution signal 37 is provided instead. Other configurations are the same as those in FIG. The repeat execution signal 37
Is asserted when a branch in a repeat instruction is repeated. In other words, the repeat execution signal 37 is asserted when the processing by the repeat instruction is repeated. When the repeat execution signal 37 is asserted, the branch signal 35 is always asserted. When the repeat execution signal 37 is asserted, the shift control circuit 30a outputs the trace data registers 33a to 33d and the repeat number registers 34a to 34d even if the branch signal 35 is asserted.
The shift operation for 34d is suppressed. Instead, the value of the repeat number register 34a is incremented by one using an incrementer.

As described above, the PC trace circuit of FIG.
Although the circuit configuration is simpler than that of FIG. 1, the data registers 33a to 33d, 34
The function is simplified as compared with FIG. 1 in that the shift operations a to 34d are suppressed. In other respects, it has the same effect as FIG.

FIG. 4 shows a third example of a PC trace circuit for realizing the PC trace function. In the figure, the PC trace circuit is different from the shift control circuit 30b in FIG. In contrast to the configuration of FIG. 3, the shift control circuit 30b is supplied with a status signal 38a indicating that a repeat command is being performed and an interrupt signal 38b. The status signal 38a is asserted when the instruction control unit 25 decodes the instruction code of the repeat instruction, and is negated when the processing for the number of repetitions specified by the repeat instruction is completed. The shift control circuit 30b can recognize that the repeat instruction is being executed or that a branch occurs during the execution of the repeat instruction, in other words, that the branch is in the middle of the repeat instruction, depending on the state of the status signal 38a being asserted. . When the shift control circuit 30b recognizes from the status signal 38a that it is in the middle of a repeat instruction, it updates the data in the trace data register 33a and updates the registers 33a to 33d and 34a even if a branch based on an interrupt occurs. 34d shift operation is suppressed. The occurrence of the branch based on the interrupt is recognized by the assertion of the branch signal 35 and the interrupt signal 38b.

Therefore, in the configuration of FIG. 4, even if an interrupt occurs in the middle of a repeat instruction, trace data is not held in a branch caused by the interrupt. If the processing or the program is normal, when the interrupt processing is completed, the processing of the CPU is returned to the processing at the time of the occurrence of the interrupt. The need for further expansion can be met, and flexibility can be increased.

FIG. 5 shows a fourth example of a PC trace circuit for realizing the PC trace function. In the figure, the shift control target by the shift control circuit 30c is flags 40a to 40d. The branch destination instruction address and the last executed instruction address before the branch are input gate 42a.
Through the trace data registers 33a through 33d
d. Repeat count registers 34a to 34d
Is selectively incremented by +1 by the incrementers 41a to 41d. +1 by the incrementers 41a to 41d
The operation is controlled by the assertion of the repeat execution signal 37. Operate any of the incrementers 41a to 41d,
Which of the input gates 42a to 42d is operated is controlled by the values of the flags 40a to 40d. The flags 40a to 40d indicate that when a branch is caused by the branch signal 35 and it is not a repetition by a repeat instruction,
The shift is performed by the shift control circuit 30c. Therefore, the same effect as in FIG. 1 can be obtained even if the above-mentioned trace data register is not a shift register type connected in series.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the number of trace data registers is not limited to four and can be changed as appropriate. The function actual module of the microcomputer is not limited to FIG. Further, the circuit block supporting the PC trace function is not limited to the user break controller.

In the above description, the invention made mainly by the present inventor is a DSP which is a field of application which is the background of the invention.
The case where the present invention is applied to a microcomputer having a unit has been described, but the present invention is not limited thereto.
It can be widely applied to data processors including U and executing instructions or commands.

[0036]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, even when the same branch is repeated many times by a repeat instruction or a loop, it is possible to prevent the same trace data from being stored in a new trace data register every time. Therefore, the trace data register for the PC trace having a limited storage capacity is not wasted. Therefore, it is possible to perform PC trace over a wide range.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first example of a PC trace circuit for realizing a PC trace function.

FIG. 2 is a flowchart showing an example of a control operation by the PC trace circuit shown in FIG.

FIG. 3 is a block diagram showing a second example of a PC trace circuit for realizing a PC trace function.

FIG. 4 is a block diagram showing a third example of a PC trace circuit for realizing a PC trace function.

FIG. 5 is a block diagram showing a fourth example of a PC trace circuit for realizing a PC trace function.

FIG. 6 is a block diagram generally showing a microcomputer as an example of a data processor according to the present invention.

FIG. 7 is a block diagram showing, as a comparative example, a PC trace circuit in which trace data is updated every time a branch occurs.

[Explanation of symbols]

Reference Signs List 1 microcomputer 2 CPU 4 user break controller 25 instruction control unit 30, 30a, 30b, 30c shift control circuit 31 comparator 32 incrementer 33a to 33d trace data register 34a to 34d repeat number register 35 branch signal 37 repeat execution signal 38a repeat instruction Signal 38b interrupt signal 40a-40d flag 41a-41d incrementer 42a-42d input gate

Claims (4)

[Claims] 1. A CPU, and a plurality of trace data registers for sequentially storing branch trace data for specifying an instruction address of a branch source and a branch destination when a branch whose instruction execution order is changed by the CPU occurs; A repeat count register provided in each of the trace data registers; and control means for controlling storage of branch trace data in the plurality of trace data registers and controlling storage of count data in the repeat count register. When the occurrence of a branch is detected and the branch is equal to the previous branch, the control means updates the count data on the repeat count register of the trace data register already having the corresponding branch trace data, If it is different from the branch of Toki data processor, characterized in that the corresponding repeat count register is initialized, is intended to acquire the trace data. 2. A CPU, and a plurality of register means for sequentially storing branch trace data for specifying an instruction address of a branch source and a branch destination when a branch whose instruction execution order is changed by the CPU occurs; Control means for controlling storage of branch trace data in a plurality of register means, wherein the control means stores the branch trace data when a new branch occurs in the branch trace data already stored in the register means. When they are equal to each other, the number of branches relating to the match is stored in the corresponding register means instead of acquiring new branch trace data, and the branch trace data when a new branch occurs is stored in the register means. If it does not match the trace data, change the register means and acquire new branch trace data. Data processor, characterized. 3. A CPU, and a plurality of register means for sequentially storing branch trace data for specifying an instruction address of a branch source and a branch destination when a branch whose instruction execution order is changed by the CPU occurs; Control means for controlling storage of branch trace data in a plurality of register means, the control means including, when a new branch is generated, the new branch trace data when the branch is repeated by execution of a repeat instruction. Is stored in the corresponding register means in place of the acquisition of the branch instruction, and if a new branch is generated and the branch is not repeated by execution of the repeat instruction, the register means is changed and a new branch trace is performed. A data processor for acquiring data. 4. The control unit according to claim 1, wherein when a branch based on an interrupt occurs in the middle of a repeat instruction, the control unit changes a register unit to suppress a process of acquiring new branch trace data. The data processor according to claim 3.