JPS62207084A - Synchronizing clock generation circuit - Google Patents

Abstract

PURPOSE:To attain a high precise synchronization clock generating circuit dividing the residual phase difference in a phase synchronization loop into a phase lag and a phase lead, and selecting one of the outputs of delay lines to which clock pulses outputted by the phase synchronization loop are inputted by using the digital amounts corresponding to the countings obtained by counting up/down the phase lag and the phase lead. CONSTITUTION:A digital phase-difference signal 24 is inputted to a multiplier 12 and amplified, inputted to a digital filter 13, whose output is inputted to a comparator 14 where it is compared with the value set in a setting switch 15 capable of setting the tolerance of phase difference. Thus the signal is decided to be a phase lag or phase lead, and to be or not to be within the tolerance. The output of the comparator 14 is gated by AND circuits 16 and 17 using counting pulses 25, and inputted to a reversible counter 18 as a forward counting pulse 26 or a backward counting pulse 27. The output of the counter 18 is inputted to a flip-flop group 20. The group 20 is made execute a latch action by a latch pulse 32 whose period is about a frame period, to output a phase- difference average in a frame period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous clock generation circuit that generates a clock for a signal processing system for a television image signal wrapped with dot interlace.

[Conventional technology]

FIG. 6 is a block diagram showing a conventional clock phase lock device disclosed in, for example, Japanese Unexamined Patent Publication No. 59-2210918, in which a fil/I'i analog-to-digital converter (21 digital image signals to a frame a frame synchronization pulse detector for detecting a synchronization pulse; (3) a horizontal synchronization gate circuit for extracting a horizontal synchronization part from the above-mentioned digital image signal; (41 is a horizontal synchronization detection circuit for detecting a horizontal synchronization pulse from the above-mentioned horizontal synchronization part; 5) is an internal synchronization generator that generates an internal synchronization pulse whose phase is controlled by the frame synchronization pulse and the horizontal synchronization bus A.
(7) is a phase detector f for detecting the phase difference between the horizontal synchronizing pulse and the internal horizontal synchronizing pulse;
an offset detector that detects an offset value between the output of il and the phase difference; (8) an adder that adds the output of the phase detector (6) and the offset value; (91, this adder (8)) This is a voltage controlled oscillator that generates a clock pulse whose phase is controlled according to the output of the oscillator.

It is a switch for switching the input terminal for the A dot interlaced image signal, the output terminal for the B clock pulse, and the frame synchronization pulse to be supplied to the S horizontal synchronization gate circuit (31).

Next, the operation will be explained. The input image signal with the dot interlace omitted is supplied from an input terminal A to an analog-to-digital converter fi+, where it is digitized to form a digital image signal. From this digital image signal, a frame synchronization pulse detector (2), a horizontal synchronization gate circuit (3), a horizontal synchronization pulse (41),
A frame sync pulse and a horizontal sync pulse are detected.

The frame synchronization pulse and the horizontal synchronization pulse are input to an internal synchronization generator (51) to form an internal horizontal synchronization pulse whose phase is controlled by them. The phase difference with the internal horizontal synchronizing pulse is detected.This phase difference voltage is applied to the voltage controlled oscillator (9) to generate a clock pulse whose phase is controlled according to the phase difference.

Further, an offset detector (7) having a time constant larger than that of the phase detector (6) is used to detect the phase detector (6).
It is added to the above phase difference via an adder (8) so as to cancel the residual offset value occurring in the output of (6), and is applied to the voltage controlled oscillator (91).

In addition, when the operation of the loop control system is stable, the frame synchronization pulse supplied to the horizontal synchronization gate circuit +31 via the switch S is changed to the internally generated frame synchronization pulse by switching the switch S to the contact C port) side. However, only when the phase difference between the horizontal synchronizing pulses is extremely large, or when the timing of the internally generated frame synchronizing pulses is off by t, the switch S is switched to the contact (a) side and the received image signal is Directly supply what is detected from the source.

In this way, the phase locking of the system clock for digitizing the human input image signal subjected to dot interlacing is performed with high precision.

[Problem that the invention seeks to solve]

Since the conventional phase synchronized clock generation circuit is configured as described above, the residual offset value of the phase difference is added as the control voltage of the voltage controlled oscillator, so the phase difference is replaced with a frequency deviation and offset detection is performed. Increasing the sensitivity of the device makes the system unstable, and it is difficult to optimize the phase-locked loop constant, which makes it impossible to control minute phase differences.

This invention was made to solve the above-mentioned problems, and it is a phase-locked clock generator that can accurately control the phase even if a slight phase difference appears when the system is in a phase-locked state. The purpose is to obtain a circuit.

[Means for solving problems]

The phase synchronized clock generation circuit according to the present invention includes a judgment circuit that inputs digitized phase detection data and inverts it depending on the state of the data, a reversible counter that performs counting in order or in reverse according to the output of the judgment circuit, and a latch circuit that holds the output of the reversible color signal, a variable delay circuit that delays the phase-controlled clock pulse, a decoder circuit that converts the digital data held in the latch circuit, and the output of the decoder circuit that outputs the variable delay. It is equipped with a multiplexer circuit that selects and outputs one of the plurality of outputs of the circuit.

[Effect]

In this invention, a judgment circuit determines whether the residual phase difference in the phase-locked loop is a phase lag or a phase lead, and a reversible counter is made to count forward or backward for a fixed period of time, and a digital quantity corresponding to this count value is calculated. Since one of the plurality of outputs of the variable delay circuit obtained by the decoder circuit and inputted with the phase-locked loop output clock pulse is selected by the decoder circuit output, a highly accurate phase-locked clock can be obtained.

[Kotobuki side of invention]

Hereinafter, a practical example of this invention will be explained with reference to the drawings. 1st
In the figure, (7) is an offset detector that detects the residual phase difference when the phase loop is locked. (
101L/i averager and the above offset detector (7)
Outputs the average value of the output over a certain period of time. G1) C is a phase shifter, which controls the phase of the tarock pulse by the output of the averager (IO) and works in the direction of canceling the residual phase difference in the loop. In addition, the same reference numerals as in the conventional example shown in FIG. 6 indicate equivalent parts.

FIG. 2 shows the offset detector (7) and averager [01].

The detailed configuration of phase shifter OB is shown. In FIG. 2, () is the digital phase difference signal from the phase detector (6). This digital phase difference signal is input to the multiplier @ and amplified. This amplified digital phase difference signal is input to digital filter αJ. The output of this digital filter (to) is input to a comparator α4) VC and compared with the value of the setting switch (to). Then, the output of this comparator α, along with the counting pulse (a), is AND
It should be input to the circuits 0υ and αη. (To), 127) is the phase difference discrimination store number, and the reversible counter 0 of the averager (1o)
8 is input. The carry/one digit down output (7), G1) of this reversible counter o8) is input to the OR circuit q9 together with the phase lock signal from the phase locked loop, and this output is used as the load pulse counter of the reversible counter (IIIC). The output of the reversible counter (to) is input to flip-flop group 4. The latch pulse (to) is input to the clock input terminal for this flip-flop group. The output is decoder circuit Q
1), and its output is input to the multiplexer circuit @.

On the other hand, the clock pulse whose phase is controlled by the phase-locked loop is transmitted to the tagged delay line of the phase shifter (lυ).
c). The multiplexer circuit (A) outputs one of the plurality of output terminals of the tapped delay line (A) as a resample clock ■.

Next, I will explain @saku. The method of detecting the phase from a digital input image signal using a horizontal synchronization portion uses an HD waveform inserted into a horizontal synchronization period of an input video signal as shown in FIG. For this HD waveform, for example,
This is stated in ``New transmission method for high-definition television (MUSE) J'' published by the NHK Broadcasting Technology Research Institute in June 1980.

FIG. 4 shows a diagram of the principle of phase detection, where (a) there is no t'1 phase difference, (b) there is a phase lead, and (0) there is a phase lag. This phase detection converts the input video signal into an analog
By latching the HD waveform of the digital video signal whose phase is controlled by a phase-locked loop by a digital converter or sampled by a sampling clock using a phase detection pulse generated by a resampling clock, a level corresponding to the phase difference is generated. This is to obtain a digital phase difference signal.

The above-mentioned digital phase difference signal is fed back by the phase-locked loop and is biased in the direction of reducing the phase difference, but if a crystal-controlled voltage-controlled oscillator is used in the above-mentioned phase loop, a residual phase offset will always occur. . The residual offset +-h of this phase can be detected by the above-mentioned digital phase difference signal.

In FIG. 2, the digital phase difference signal ■ is.

The signal is input to a multiplier (to), amplified, and input to a digital filter (to). This digital filter constitutes a low-pass filter and removes unnecessary high-frequency and jitter components. The output of the digital filter (to) is
The signal is input to the comparator α, and is compared with the value of the setting switch (to) that allows setting the permissible range of the phase difference, and it is determined that the phase lag or phase lead is within the permissible error. FIG. 5 shows an example of the relationship between the phase difference and the digital phase difference signal level and the judgment range of phase lead and lag, in which (a) the relationship between the it phase difference and the digital phase difference signal level, and (b) the phase Advance judgment range, (c) I/′! The phase delay determination range is shown. The output of the comparator α is gated by the AND circuit αe (G7) by the counting pulse (to) and inputted to the reversible counter (to) as the forward counting pulse (e) and the backward counting pulse (a). . The carry output and borrow output 01) of the reversible counter Q81 are input to the 11OR circuit a9, and its output becomes the load pulse of the reversible counter OgJ.

The above-mentioned reversible counter (to) has the value of Z2 of the total count value, that is, data representing 0 phase difference, set at the load value input terminal, and when the phase loop is not locked, the reversible counter (to) When overflows and falls below, the reversible counter (to) outputs data with a phase difference of 0. On the other hand, when the phase loop is locked and the reversible counter 0 does not overflow or underflow, the reversible counter (to) performs counting using the forward counting pulse (7) and the backward counting pulse (7), and performs the counting at any time. Output data.

The output of the above reversible counter (to) is the flip-flop group (
1) is input. Launch pulse of about frame period (
By a), the flip-flop group (1) performs a latch operation, and as a result, outputs, for example, the average value of the phase difference within a frame period.

The output of the above flip-flop group (a) is the decoder ■υ
is input.

On the other hand, the clock pulse c13i is output from the voltage controlled oscillator (9) of the phase-locked loop, is input to the tapped delay line (A), and is output from each of the multiple taps to generate clock pulses with different amounts of delay. It outputs and supplies it to multiple input terminals of a multiplexer.

The output of the decoder Qυ is input to the control terminal of the multiplexer (A), and the input that cancels out the residual phase difference is selected and output as the resample clock ■.

The analog-digital converter fil samples the input video signal and obtains a new phase difference signal using the resample clock (2). Through the above cycles, the phase difference is
It converges in the direction of disappearing.

In addition, in the above embodiment, NoJn+1) shown in Figure @3
Although we have described the case of phase detection characteristics using lines, N
(Even when using phase detection characteristics using 1, n lines, this can be easily handled by changing the connection of the tap delay line or reversing the counting direction of the reversible counter.

Furthermore, for other purposes, when a clock pulse having a different phase from the phase-locked loop output is required, the phase can be shifted to any position by changing the set value for comparison in the comparator.

〔Effect of the invention〕

As described above, according to the present invention, the residual phase difference in the phase-locked loop is determined as phase lag or phase lead, forward or reverse counting is performed for a certain period of time, and the digital quantity corresponding to this counted value is calculated. Since one of the outputs of the delay line having a plurality of taps into which the phase-locked loop output clock pulse is input is selected, a highly accurate synchronized clock generation circuit can be obtained.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a synchronous clock generation circuit according to an embodiment of the present invention, FIG. 2 is a detailed block diagram of an offset detector, averager, and phase shifter of this embodiment, and FIG. 3 is a block diagram of an HD waveform. Example, Figure 4 is an explanatory diagram of phase detection, ¥Jiff
l'l is a diagram showing the relationship between the phase difference and the digital phase difference signal level and the determination range of phase lead and phase lag;
The figure is a schematic block diagram of a conventional synchronous clock generation circuit. In the figure, (1) is an analog-to-digital converter, (
2) is a frame synchronization pulse generator, (3) is a horizontal synchronization gate circuit, (41-digit horizontal synchronization detector, (6) is an internal synchronization generator, (6) C phase detector, (7) H offset detector , (91 voltage controlled oscillators, (lO) is the averager, α1
) phase shifter, α◆ comparator, (to) ai constant switch, (
(g) is a reversible counter, c20t/i flip 70 knob group, Cυ is a decoder, (a) is a multiplexer, wire is a tapped delay line, (c) is a digital phase difference signal, function is a counting pulse, wire is forward counting The pulse, @ is the backward counting pulse, □□□ is the clock pulse, and (to) the sample clock pulse.

Claims (1)

[Claims] (1) An input image signal subjected to dot interlacing is digitized by an analog-to-digital converter to form a digital image signal, horizontal synchronization is detected from the digital image signal, and a phase-locked loop is used to convert the input image signal to the analog-to-digital converter. In a device that obtains a synchronized clock that synchronizes the phase of a resampling clock, an offset detection circuit detects the residual phase difference in the phase-locked loop from a digital phase difference signal, and the output of the offset detection circuit is set within a tolerance range. a reversible counter that performs forward or reverse counting according to the output of the comparator; and a plurality of output taps to which the clocks in the phase-locked loop are input and provide mutually different delay times. 1. A synchronous clock generation circuit comprising: a delay line having: a multiplexer that selects one of the outputs from a plurality of output taps of the delay line according to a digital value of the output of the reversible counter.