JPS62206872A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase step-up speed remarkably while reducing an area required for constituting a step-up circuit, and to cut chip cost by forming a capacitor for step-up so as to be superposed on a gate for an output MOSFET, using the gate as one electrode and shaping the capacitor for step-up in a capacitor having large capacitance. CONSTITUTION:A gate electrode 19 functions as one electrode of a capacitor C for step-up in combination, and the other electrode 25 consisting of polycrystalline silicon is shaped onto the gate electrode 19 through an oxide film 24 as a dielectric layer. A capacitor C for step-up constituted of the gate electrode 19, the oxide film 24 and the other electrode 25 is shaped so as to be superposed onto the gate electrode 19 for a vertical type MOSFET4. The gate electrode 19 for the vertical type MOSFET4 is formed particularly in a comparatively large area so as to extend over a plurality of channel regions, and shaped in a larger area when even a wiring section is included, thus forming the capacitor C for step-up in required large capacitance.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device including a power MOSFET and a booster circuit for boosting its gate drive voltage, and in particular to a semiconductor device that improves the boosting speed of the booster circuit. It is something.

[Technical background of the invention and its problems] In recent years, a power MOSFET, which is used as a switching element for various in-vehicle power loads, and an IC that constitutes peripheral circuits such as its drive circuit have been configured on a single chip. Semiconductor devices are being considered.

As the above-mentioned power MOSFET, a vertical MOSFET with a large current capacity and using a semiconductor substrate as a drain region is often used. In vertical MOSFETs, the drain region is the semiconductor substrate in which other ICs are also incorporated, so it is difficult to connect the power load to the drain. Therefore, vertical MOSFETs use a source follower connection in which the power load is connected to the source side. used in

By the way, in a vertical MOSFET connected as a source follower, the source potential increases when the MOSFET turns on, so that the gate source voltage V (JS) decreases, the on-resistance increases, and the power loss increases.

Therefore, a booster circuit for boosting the gate voltage is incorporated into the drive circuit to reduce power loss.

FIG. 7 shows an example of a conventional semiconductor device incorporating such a booster circuit, FIG. 8 shows its equivalent circuit, and FIG. 9 shows a clock signal for controlling the booster circuit.

The Tatsumi pressure circuit uses a charge pump type based on the Kotscroft-Walton circuit (IEEE
JOURNAL OF 5QLID-8TAT
E CIRCUITS, VOL.

5C-11, NO, 3, JIJNE 1976, P3
74 [on-Chip Hi
gh -Voltage Genera mouth on in MNOS I nteoratcd
C1rcuits Using an Im
proven Voltage Multiply
er TechniqueJ).

Reference numeral 52 in the booster circuit 51 in FIG. 8 indicates the power supply voltage Vd.
d input terminal, 53 is an output terminal for the boosted voltage vg, and between these input terminal 52 and output terminal 53 are diode-operated MOSFETs whose gates and drains are connected, and boosting capacitors 54a and 55a, 54b and 55.
A plurality of boosting stages each having pairs of b and - are arranged in accordance with the required boosted voltage.

The other ends of the capacitors 55a, 55c, . The other ends of the terminals 55b, . . . , 55n-+ are commonly connected to the input terminal 57b of the φ clock signal.

As shown in FIG. 7, the above-mentioned promotion circuit 51 is built into a p-well 59 formed in an n-type substrate 58 in order to be electrically isolated from other ICs. A power supply voltage V (jd) is connected to the substrate 58, the p-well 59 is set to the ground potential, and the junction between the substrate 58 and the p-well 59 is reverse biased. 61a, 61b, 61G, . . . The n+ region 62 formed in the oxide film 62 is a gate oxide film of a MOSFET or an oxide film that serves as a dielectric of a capacitor.
3a, 63b1... are polycrystalline silicon gate electrodes,
64a, 64b, . . . are polycrystalline silicon electric devices for forming capacitors.

A MOSFET 54a is formed by using the n+ region 61a as a drain and the n+ region 61b as a source, the oxide film 62, and the gate electrode 63a.
The next stage MOSFET 54b is formed by using the region 611) as a drain and the n+ region 61c as a source, together with the oxide film 62 and the gate electrode 63k).

In addition, a capacitor 55a for knee pressure is formed by the electrode 64a1 oxide film 62 and the n+ region 61b, and the electrode 64b
, the M film 62, and the n+ region 61C form the next stage capacitor 55b.

In this way, the MOSFETs 5'4a and 54b and the capacitor 55a155b are formed separately on the main surface of the substrate. Similarly, the following MOSFETs and capacitors of each step-up stage are formed, and the output terminal 53 is connected to the gate of the output MOSFET 4 connected as a source follower. 5 is a power load.

First, the first stage capacitor 55a is connected to the power supply voltage ■dd
Vdd-Vth (Vth is MOSFET54 a
(open-chain voltage). When the clock signal φ rises, the voltage at the node 56a connected by the capacitor 55a is boosted, and at the same time, the conduction of the MOSFET 54b is controlled and the boosted voltage is applied to the second stage capacitor 5.
5b is charged. At this time, the charging potential of the nodes 56a and 5]) is divided by a capacity M by both capacitors 55a and 55b. Next, at the rising edge of the clock signal φ, the voltage at the node 56b is boosted, and at the same time, the MOSFET 54c is controlled to be conductive, and the boosted voltage is transferred to the capacitor 5 in the third stage.
Charged to 5C.

In this way, each stage of capacitors 55a, 55b155
c1... is charged with the boosted voltage of the previous stage in a superimposed manner, and the potential of each node 56a, 56b, 56c,... increases sequentially, and the boosted voltage from the output terminal 53 is boosted to the required voltage value. Voltage ■9 is output, this is the output MO3FET4
is added to the gate to reduce power loss.

However, in the above-mentioned semiconductor device, the output MOSFET 4 for power (input capacitance 2
Since the booster circuit that drives the pF (pF) has a configuration in which booster stages each consisting of a diode-operated MOSFET and a capacitor are connected in multiple stages, the boosting speed decreases and the switching speed of the output MOSFET 4 decreases. There was a problem that the power loss could not be sufficiently reduced due to the slow speed. Further, there is a problem in that the area required for the configuration of the booster circuit increases, resulting in an increase in chip area, leading to an increase in cost.

[Object of the Invention] The present invention was made based on the above circumstances, and it significantly increases the boost speed to increase the switching speed of the output MOSFET, and also reduces the chip cost by reducing the area required for the configuration of the boost circuit. An object of the present invention is to provide a semiconductor device that can reduce the amount of noise.

[Summary of the Invention] In order to achieve the above object, the present invention forms a step-up capacitor with the gate of an output MO3FET as one electrode and stacks it on the gate of a 7b MOSFET. By using a capacitor from a human care shop, the power supply voltage can be boosted to the required voltage value in a single step-up stage, increasing the step-up speed and reducing the area required for the configuration of the step-up circuit. It is something.

[First Embodiment] The first embodiment of the present invention will be described below with reference to <A), (B) to
This will be explained based on FIG. This example uses the output MOS
This is applied to a semiconductor device using a vertical MOSFET as an FET.

First, the configuration will be explained. As shown in FIGS. 1A and 1B, the semiconductor substrate used is an n+ epitaxial layer 112 formed on an n+ substrate 1. High resistance n
''The portion of the epitaxial layer 2 is substantially a vertical MOSF
It becomes the drain of ET. Hereinafter, in this example, the above n
A +on-n- epitaxial substrate is referred to as an n-type semiconductor substrate 3.

On the main surface of the semiconductor substrate 3, a vertical MOSFET 4 and a capacitor C1nMO86, which is a component of the booster circuit U, are provided.
, pMO 87, diode 8, etc. are formed, respectively.

Among the above-mentioned elements, the vertical MOSFET 4 has a p-type channel region 15 on the main surface of the semiconductor substrate 3.
is formed, and an n+ source region 16 is formed within this channel region 15.

17 is a p+ contact region. Also n + source area j
A gate electrode 19 made of polycrystalline silicon is formed on the channel region 15 between the liIi 16 and the n- region of the semiconductor substrate 3, which becomes the drain region, with a gate oxide film 18 interposed therebetween.

21 is a PSG film, 22 is a source electrode formed of an AM film, and 23 is a guard ring for improving drain breakdown voltage.

In this embodiment, the gate electrode 19 also serves as one electrode of the boosting capacitor C, and the other electrode 25 made of polycrystalline silicon is formed on the gate electrode 19 with an oxide film 24 serving as a dielectric layer interposed therebetween. has been done. Therefore, vertical MOS
FET4 gate voltage If! 19, the gate electrode 1
9, an oxide film 24, and the other electrode 25, a boosting capacitor C is formed in a stacked manner.

In particular, the gate electrode 19 of the vertical MOSFET 4 is formed to have a relatively large area so as to span multiple channel regions, and is even larger if the wiring portion is included as shown in FIG. , the boost capacitor C can be of a required large volume. In addition, as shown in FIG. 1(A) and FIG. 1(B), each gate 1
The capacitors formed on 9.19 are connected in parallel and used as one boosting capacitor C.

Although the 4-voltage capacitor C is formed to have a large capacity as described above, the gate electrode 19 of the vertical MOSFET 4
Since the capacitors are stacked on top of each other, there is no need to take up any area on the main surface of the semiconductor substrate for forming the capacitors, unlike the conventional structure shown in FIG.

Further, in the diode 8, as shown in FIG. 1(A), a gate electrode 19 made of n+ polycrystalline silicon extends over the field oxidation WA 26, and a p'' polycrystalline silicon region 27 is connected to this. A diode 8 is formed by the junction between the n+ region 19a and the p+ region 27 of polycrystalline silicon.As will be described later, a boosted voltage is applied to the cathode of the diode 8, so that the field oxide film 26
By forming it on top, the problem of insulation with respect to the semiconductor substrate 3 and the like is solved.

Next, as shown in FIG. 1(B), nMO86 is applied to p1 well region ip! The substrate region 28 is composed of an n+ source region 29, an n+ drain region 31, a gate electrode 33 formed on a gate oxide film 32, and the like.

Further, the 0MO 87 is composed of a p+ source region 35, a p1 drain region 36, a gate electrode 38 formed on a gate oxide film 37, and the like, using an n diffusion region 34 whose resistivity is appropriately adjusted as a substrate region.

The booster circuit U is constructed as shown in FIG. 2 using the above-mentioned elements formed on the semiconductor substrate 3 as constituent elements.

2. Request number 9 is the input terminal for the control till voltage Vin, 1
0 is the input terminal of the power supply voltage ■dd, the input terminal 9 of the control voltage V1n is connected to the one-shot multivibrator 11, and the output terminal of the one-shot multivibrator 11 is connected to one side of the boost capacitor C via the inverter 12. connected to the electrode. The input terminal 10 of the power supply voltage Vd (j
It is connected to the other electrode of the capacitor C via.

The diode 8 is connected to prevent the boosted voltage from leaking to the power supply side.

As described above, in this embodiment, the boosting stage is composed of only one stage consisting of one each of large-capacity capacitor C1 and pMO87.

Further, the gate of the vertical MOSFET 4 is grounded via the nMO 86, and the input terminal of the control tll1m voltage vin is connected to the gate of the nMO 86 via the inverter 13.

The nMO86 is connected to ground the gates 1 to 1 of the vertical MO3F'ET4 and turn them off when the control voltage v1 (1 is at L level).

The other electrode of the capacitor C, the cathode of the diode 8, and the gate of the vertical MOSFET 4 are as follows:
Connections have already been made during the integral formation on the semiconductor substrate 3 described above.

Next, the action will be explained.

As shown in FIG. 3, the control voltage v1 input to the input terminal 9
When n rises from the L level to the H level, the one shot multivibrator 11 outputs an H level control signal e1 having a pulse width defined by its circuit constants. The control signal e1 at the "L" level is inverted by the inverter 12 and becomes the L level, and this L level signal causes the pMO
87 is controlled to be conductive, and the boosting capacitor C is charged with the power supply voltage Vdd.

When the control signal e1 changes to the L level after the specified time has passed, the output of the inverter 12 becomes the H level, and this H level
The charging voltage of capacitor C is boosted by the level signal.

The boosted voltage VQ is the capacitance of the capacitor C as C1 vertical MOS
If FET4(7)/7-tWfflecQs, then V
It is given by Q=Vdd-(2C+CQS)/(C+Co5).

In this embodiment, it is relatively easy to form the capacitance of the boosting capacitor C to be larger than the value of the gate capacitance Cgs, but if C=ccts, then v
a*i becomes 5Vdd, and the power supply voltage is boosted by 50%.

Furthermore, since the boosting stage is composed of one stage, the above boosting action is performed at extremely high speed, and the vertical MOSFET 4 is
The gate is driven by the boosted voltage ■Q and turns on,
A high speed switching operation is performed to energize the power load 5.

Therefore, even if the source potential of the vertical MOSFET 4 rises due to energization, a sufficiently high gate voltage Va is applied to the vertical MOSFET 4, so that its on-resistance does not increase and an increase in power loss is suppressed.

When the control voltage vin becomes L level, the nMO 86 is energized via the inverter 13, the gate voltage V (J becomes zero, and the vertical MOSFET 4 is turned off).

Next, a specific example will be described in comparison with a conventional example.

Assuming that the inverter 12 is composed of n-channel and p-channel MOSFETs, its characteristics are β-
8μA/V2, Vth=2V,! :L,, Capacity of boost capacitor C is 1000pF, vertical MOSFET4
Assuming that the gate capacitance cqs of is 1000 pF, the pulse width of control signal e1 is 15 μs, and Vdd-15■, VQhl
, the time required to boost the voltage by 5VdlC was approximately 30 μs.

In contrast, the conventional booster circuit 51 shown in FIG.
In this case, the number of step-up stages is 7, and each step-up capacitor is 5.
5a... capacitance M is 2pF, each MO8FE T 54
a... is β-8μA/V2, Vth=2V.

Assuming that the frequency of the clocks φ and φ was 1MH2, and that Vdd and the gate capacitance Cqs of the vertical MOSFET 4 were the same as described above, the time required to boost the voltage to VgWl and 5Vdd was about 2 ms.

Therefore, when comparing the boosting speeds of both of the above, the embodiment of the present invention is 60 to 70 times faster than the conventional one.

If a conventional device were to obtain a boosting speed equivalent to that of the embodiment of the present invention, it would be necessary to increase the size of both the MOSFET and the boosting capacitor to approximately 60 to 70 f8, resulting in a significant increase in chip area.

[Second Embodiment] FIG. 4 shows a second embodiment of the present invention. This embodiment is applied to a semiconductor device using a lateral MOSFET as an output MOSFET.

In addition, in FIG. 4, in (A) and (B) of the above-mentioned FIG.
Components or parts that are the same as or equivalent to those shown above are designated by the same reference numerals as described above, and redundant explanation will be omitted.

In the lateral MOSFET 14, a p-well 39 serving as a channel region is formed on the main surface of an n-type semiconductor substrate 3, and an n+ source region 40, an n+
A gate electrode 4f formed on the drain region 41 and the gate oxide llI42! It is composed of 43 mag.

A boosting capacitor C is formed by using the gate electrode 43 as one electrode, the oxide film 24 serving as a dielectric layer, and the other electrode 25.

Even when configuring the boost capacitor C on the gate electrode 43 of the horizontal MOSFET 14, compared to forming it in the substrate as shown in FIG. A capacitor with a comparative capacitance can be formed without taking any special measures.

The horizontal MOSFET 14 is used as an output MOSFET for relatively low power compared to the vertical MOSFET 4, but the effect of being driven by a boost voltage and suppressing the increase in power loss is almost the same as that of the first embodiment. The same is true.

[Third Embodiment] FIGS. 5 and 6 show a third embodiment of the present invention.

In this embodiment, a backup booster circuit is added to the booster circuit included in the semiconductor device of the first embodiment.

In FIG. 5, the main booster circuit U1 is constructed similarly to the booster circuit U in FIG. 2.

Reference numeral 44 in the backup booster circuit U2 is an oscillation circuit that oscillates a pulse signal e2, and is provided with a set terminal S and a reset terminal R, and an inverter 45 that inverts the control voltage Vin is connected to the reset terminal R.

The output terminal of the oscillation circuit 44 is connected to one electrode of the boosting capacitor C2 via another inverter 46, and the line for the power supply voltage Vdd is connected to the pMO 847 and the diode 4.
8 to the other electrode of the capacitor C2. The other electrode of the capacitor C2 serves as an output terminal for the backup boosted voltage, and this output terminal is connected via a diode 49 to the output terminal of the main booster circuit U1.

One of the purposes of the backup booster circuit U2 is to compensate for the drop in the boosted voltage of the main booster circuit U1 due to charge leakage through the pMO 86 and the diode 8, so its boosting speed is lower than that of the main booster circuit. It doesn't need to be as fast as U1.

Therefore, the boosting capacitor C2 does not need to have as large a capacity as the capacitor C1 on the main booster circuit Ui side.
It can be formed on a part of the gate type 19 of the vertical MOSFET 4 in FIG. Other pMO3
Similarly, the diodes 48 and 49 may have relatively small capacitance, and are formed in a part of the main surface of the semiconductor substrate 3.

Since these elements are small and small in number, only a small increase in area is required to form them.

To explain the action, control 17tf pressure Vin;/jCL
When rising from the level to the H level, the main booster circuit U1
As mentioned above, the pressure is increased at a high speed, for example, vo
*”+, boosted to 5Vdd.

On the other hand, in the backup booster circuit U2, when the control voltage Vin rises to H level, the oscillation circuit 44 starts oscillating, and the output side of the capacitor C2 becomes a small voltage every cycle of the pulse signal e2 with a fast repetition period. The level will be boosted step by step.

With this stepwise boost voltage, the boost voltage of the main boost circuit U1 is
Q is backed up and the output MO remains for a relatively long time.
Even when the SFET 4 is continuously driven, a decrease in the boosted voltage Vg for gate driving due to charge leakage etc. is compensated for.

Then, due to the backup action of the backup booster circuit U2, the boosted voltage VQ is finally boosted to a voltage level of about 2Vdd, and the power loss of the output MO3FET4 is further reduced.

When the control voltage Vin becomes L level, both booster circuits Li
, U2 are both reset, and the output MOSFET 4 is turned off by the action of nMO86 and the like.

[Effects of the Invention] As explained above, according to the present invention, the step-up capacitor is formed so as to be stacked on the gate of the output MOSFET with the gate of the output MO3FET as one electrode. can be made into a large-capacity capacitor, and the power supply voltage can be boosted to a new voltage value with one step-up stage. Therefore, the step-up speed is significantly increased, the switching speed of the output MOSFET is increased, and the power loss of the output MOSFET can be sufficiently reduced. Furthermore, since the area required for the configuration of the promotion circuit is reduced, there is an advantage that the chip area is reduced and chip cost can be reduced.

[Brief explanation of drawings]

FIG. 1 is a longitudinal sectional view showing a first embodiment of a semiconductor device according to the present invention, FIG. 2 is a circuit diagram showing an equivalent circuit of the above embodiment, and FIG. 3 is a timing diagram showing control signals, etc. of the above embodiment. 4 is a vertical cross-sectional view showing a second embodiment of the invention, FIG. 5 is a circuit diagram showing a third embodiment of the invention, and FIG. 6 shows control signals, etc. of the third embodiment of the invention. 7 is a longitudinal sectional view of a conventional semiconductor device, FIG. 8 is a circuit diagram showing an equivalent circuit of the conventional example, and FIG. 9 is a waveform diagram of a clock signal applied to the conventional example. 3: Semiconductor substrate, 4: Vertical MO3FET (output MOSFET), 9: Control voltage input terminal, 10: Power supply voltage input terminal, 14: Horizontal MOSFET (output MOSFET>, 19.
43: Gate electrode, 24: Oxide film serving as dielectric layer, 25: Other electrode of capacitor, C, CI, C2: Boosting capacitor, U, Ul, C
I2: Boost circuit. 'Patent applicant Nissan Motor Company! JL Car Co., Ltd.'#c2 Figure 3Σ Figure 5 Figure 6

Claims (1)

[Scope of Claims] A semiconductor device in which a power supply voltage charged in a boosting capacitor is boosted by an external control signal, and the gate of an output MOSFET is driven by the boosted voltage, the boosting capacitor being connected to the output MOSFET. A semiconductor device characterized in that the gate of the MOSFET is stacked on the gate of the output MOSFET as one electrode.