JPS6220581B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fetch notification device for a microprocessor that does not have a fetch notification function.

Logic analyzers, especially those with state and timing analysis capabilities, are extremely useful in locating hardware and software problems in microprocessor systems, including products developed based on microprocessors. It is effective for Due to the different characteristics of various commercially available microprocessors, special data acquisition modules, termed personality modules, are used in the electronics industry as an interface between logic analyzers and each microprocessor. That is, each personality module is essentially a hardware interface that connects the logic analyzer's input parameters to the limited characteristics of a particular processor, such as the definition of control lines, as well as address lines, It is adapted to the pin arrangement of data lines and control lines. In addition, the personality module is originally a data acquisition circuit for logic analyzers, so it
It is possible to configure a qualification circuit (a circuit that captures data only when a specific signal is input), and the logic analyzer samples only the qualified data and stores it in the limited capacity acquisition memory. Remember. Once the data is ingested into the logic analyzer, the data is
It may be displayed by a mnemonic (an easy-to-remember label) created by a particular processor's disk assembly (the reverse of assembly, turning a machine language program into a symbolic language program), or by other display formats available to the logic analyzer.

To facilitate proper disk assembly of microprocessor instructions into opcodes (opcodes) and mnemonics, and to display the disassembled mnemonic data, the first step is to fetch instructions. It is necessary to distinguish reading from operands. Data identification is then performed and only the appropriate data is stored in the acquisition memory. In particular, 6809
Microprocessors such as molds do not have a fetch notification function, and they store the desired information in the acquisition memory.
A significant amount of unnecessary or indistinguishable information is stored. Therefore, it is necessary to predict the fetch of an opcode in a series of microprocessor instructions.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a new fetch prediction device (state machine) for use in a personality module such as a 6809 microprocessor for a logic analyzer.

A feature of the present invention is that multiple byte opcodes are decoded and a fetish is predicted based on them.

Another feature of the invention is to automatically resynchronize the fetch notice state machine after an irregular opcode.

Other objects, features and advantages of the invention will become apparent to those skilled in the art from the following detailed description, taken in conjunction with the accompanying drawings.

The present invention is a fetch notification device (state machine) that predicts the fetch of an opcode in a series of instructions of a microprocessor such as the 6809 type which does not have a fetch notification function. Below, the 6809 type will be representative as a microprocessor without a fetish notification function. The predicted fetch is indicated in the form of one or more control signals that are applied to the word recognizer section of the logic analyzer, which transfers the data to the acquisition memory. to join. Considering that all 6809 microprocessor instructions require a certain number of clock cycles to execute, the number of clock cycles from the current instruction to fetching the next opcode is determined. The fetch notification state machine passively monitors the microprocessor bus and latches and decodes three consecutive bytes to label the next data bus read as an opcode fetch. Decide how long to wait beforehand. A read-only memory is used as a decoder, programmed with a number of decoder tables representing the number of cycles to wait for the next instruction. The decoded cycle number is loaded into a first counter (CNTR1) and a second counter (CNTR2) as required. The counters are then sequentially incremented (INC) to their final value and the fetch line indicates that the current cycle is in the fetch state.

The format of the decoded instruction determines the correct signal path through the fetch notice state machine. In order to determine the number of processor clock cycles required to execute a particular instruction, all three consecutive bytes must be decoded.
The first byte of the opcode is decoded to determine whether the next byte needs to be decoded. This decoding determines the format of the instruction and, for standard format instructions, the total number of clock cycles for the instruction. For multi-byte instructions, the first byte defines a subtotal of clock cycles;
This subtotal is added to the remainder of the required cycles as determined by decoding the next byte. Decoding the first byte sets various flag bits in the flag latches. These bits point to one of several different decoder tables needed to decode the next byte of the current instruction. The next state of the fetch notice state machine is determined by a logical combination of the current state and various input variables. The state machine clock is derived from the microprocessor clock, and the state machine clock
Inhibited during invalid memory address cycles and certain other cycles. By not clocking the state machine on these cycles, the number of these cycles is determined by the state machine and these cycles are ignored.

To facilitate understanding of the present invention, the relationship between the Fetch Predictor state machine (Fetch Predictor) and other portions of the logic analyzer's data acquisition system will first be described. In the block diagram of FIG. 1, a personality module 10 is connected between a system under test (SUT) 12 and a logic analyzer 14. Personality
Plug module 10 into the microprocessor socket of SUT 12 and connect it to the SUT
6809 type microprocessor 16 removed from 12
into the socket called Zero Insertion Force on Personality Module 10. As a result, the personality module 10 can be transferred to the microprocessor of the SUT 12.
It will be connected to the bus. Logic analyzer 14 is preferably a conventional logic state analyzer having a cathode ray tube display displaying the contents of an internal acquisition memory. Personality module 10 is microprocessor 1
6, it also includes a buffer driver 18, address signal lines, data signal lines, clock signal lines, and control signal lines to enable the logic analyzer 14 to acquire data. In the control line portion of the signal line between the buffer driver 18 and the logic analyzer 14,
Control logic and fetch annunciator 20 are provided. Personality module 10 allows the selected microprocessor to operate in conjunction with the logic analyzer's available address, data, control and clock lines as provided within SUT 12. Furthermore, the personality module makes decisions unique to the 6809 microprocessor in the standard configuration (format) of the logic analyzer and sets specific information. This information aids in the generalization of mnemonic disk assembly and display of the captured information. The fetch signal generated by the fetch predictor is fed to the word recognizer section of the logic analyzer to enable triggering and data identification at the instruction fetch.

FIG. 2 is a block diagram of a fetch predictor (state machine) and a portion of the control logic associated with the fetch predictor in accordance with the present invention. The abbreviations used in the explanation here and in the flowchart in FIG.
It is defined in "6809 Microprocessor Instruction Setting Mnemonic".

State clock generator 30 receives clock signal E from the 6809 microprocessor and generates a clock signal SCLK for the fetch predictor and an output clock signal for the logic analyzer.
Generate CLK. This clock signal CLK allows the logic analyzer to select the master state.
Generates a clock. It will be seen below that the state clock signal SCLK may be interrupted or inhibited under certain conditions.

Data latch 32 provides cycle decoder programmable read-only memory (PROM) 34 with 8-bit opcodes DA ₀ - DA ₇ from the microprocessor data bus.
Receive and latch. In this embodiment, inputs DA ₀ -DA ₇ are latched on the rising edge of the SCLK signal. The cycle decoder PROM 34 is a 2K word (one word is 8 bits) EPROM,
It stores seven decoder tables. These tables show the number of clock cycles required to execute each 6809 instruction. In this example, these tables were created from information found in the Motorola 6809 Microprocessor Manual. The latched 8-bit opcode on the signal line from data latch 32 is decoded by PROM 34. The decoded information of the output CT ₀ - CT ₃ is sent to a first counter (CNTR ₁ ) 36 and a second counter (CNTR ₂ ) 38 which are counter means.
tells the increment value to . Counters 36 and 38 are loaded with the complement of the number of cycles delayed and incremented to E or F in hexadecimal code. The F ₀ -F ₂ lines supply the status of various flag bits to flag latch 40. These states are clocked into the output of flag latch 40 on the rising edge of the SCLK signal. The output of flag latch 40 is connected to input/output formation logic circuit 42 and serves as the input address line for cycle decoder PROM 34. Cycle decoder PROM 34 uses these address inputs to point to one of several different decoder tables within the PROM. These tables help decode the next byte of the current instruction. The irregular opcode () signal line is one output line of the cycle decoder PROM34,
Indicates that the last opcode decoded was an irregular opcode. This signal causes the line from the input/output forming logic circuit 42 to the logic analyzer to be a "low" level, but is inverted to a "high" level in the firmware for the screen display. Thus data latch 32, cycle decoder PROM 34 and flag latch 40.
constitutes a decoding means.

The first and second counters 36 and 38 track the set number of cycles and indicate that the next instruction cycle is a fetch. To indicate this fetch, the first counter 36 outputs a count signal CNT ₁
=F, and the second counter 38 generates a count signal.
₂ = is generated. These signals are utilized by the input/output forming logic circuit 42. Signal line CT ₀ from cycle decoder PROM34 -
CT ₃ transmits information indicating the number of cycles required for the current instruction before executing the next instruction. input/
Load counter signals ₁ and ₂ from output forming logic circuit 42 cause counter 36 to
and 38 latches CT ₀ - CT ₃ information. SCLK
The signal causes counters 36 and 38 to increment until they reach their final counts, ie, CNT ₁ =F and ₂ =.

Skip state clock circuit 44 generates a signal for state clock generator 30. This signal inhibits generation of the SCLK clock for one cycle. In the cycle following the skipped cycle, the skip state clock circuit 44, which corresponds to the status code output from the stack to the data bus, outputs an interrupt (RTI) decoder 46.
Respond to returns from RTI signals. The clock signal from state clock generator 30 is routed to the RTI via an internal flip-flop.
Clock signals and inhibit signals. RTI
The signal indicates when a return from an interrupt instruction has occurred. Signals D and F0 are at "high" level, signal F1
When F2 and F2 are at a "low" level, the RTI signal is active.

Present state latch 50 holds the current state of the fetch notice state machine.
On the rising edge of the SCLK signal, the values of NEXTX, NEXTY, and NEXTZ are loaded into latch 50, resulting in the new current state. When the interrupt acknowledge ( ) signal is provided, the latched value is cleared and returns the state machine to state A of FIG. When the state machine is in any state, a signal is generated so that the fetch predictor can be resynchronized (the fetch always follows two cycles after the signal). Present state decoder 52 is 3
Line - An 8-wire decoder with separate output lines for each state of the state machine. These outputs simplify the input/output forming logic circuit 42. The input/output forming logic circuit 42 is a combination of individual logic gates determined from Boolean algebraic equations according to the desired inputs and outputs. The input formation logic part is the current state and CNT ₁ = F, ₂
The following states are generated from logical combinations of input variables such as =E, PAGE2/3 flag, OP ₊ flag, IOC, and #OPCYCLES =F. The output forming logic forms the output of the state machine by a logical combination of the current state and the input variables described above. This output is ₁ ,
INCCNT ₁ , ₂ , INCCNT ₂ ,,
₂ and is. Please note that input/
Output forming logic circuit 42, latch 50 and decoder 52 constitute logic control means.

Some status signals and all address signals from the SUT are input to buffer and detector circuitry 60.
to generate several control signals for the logic analyzer, state clock generator 30, and fetch enable logic circuit 62. The + signal is generated by the DMA or DEAD cycle detection portion of detector circuitry 60 and is useful to indicate the presence of a dead cycle or that the bus is being used by another controller. Bus access (BA) line from SUT is “High”
During one cycle of clock E, which follows the transition of this BA signal from a "high" level to a "low" level, the + line is defined as a "low" level. One cycle of this clock E is
This is an invalid cycle that follows the end of DMA transmission and the synchronization know cycle. Read-Write (R/
) signal is obtained from the SUT via the input buffer of circuitry 60. A valid memory address (VMA) signal is generated in the VMA detection circuitry of circuitry 60. An invalid memory address exists when the state of the address bus is FFFF, when the bus status (BS) is equal to zero, or when R/=1 indicating a read operation. of the circuit network 60
The VMA detection section further includes a fetch biasing logic circuit 6.
Generates ADO and FFFE+FFFF signals for 2.
The interrupt recognition detector portion of circuitry 60 generates signals for fetch activation logic circuit 62 and present state latch 50. A signal is generated when the BS signal is at a "high" level and the BA signal is at a "low" level. Fetch biasing logic circuit 62
provides the instruction fetch cycle () and ₊₂ signals to the logic analyzer.

The signal is the command fetch cycle (fetch-1)
Indicates that this has occurred. The ₊₂ signal indicates an instruction fetch cycle, where the first byte (fetch-1) or the next byte (fetch-1) of the instruction is
2) is fetched. That is, the fetch predictor anticipates a fetch at the edge of the clock, and since this clock edge latches the fetched data into the logic analyzer's memory, the corresponding memory read requires no data in the acquisition memory. The disassembled mnemonic, which can be labeled as a fetch, is displayed on the logic analyzer screen along with other information. and signals (inside the fetch energizing logic circuit 62), FFFE
When no signal is provided, a signal is generated.
The first signal is output from the input/output forming logic circuit 42 of the fetch predictor.
This signal marks the end of one complete sequence of the fetch notice state machine and indicates that the following cycle is a fetch. In preparation for the next cycle of the state machine, the flag is cleared. The 6809 microprocessor uses FFFE during the reset sequence.
The signal is decoded to exclude extraneous fetish predictions. When the signal is at a "low" level, it indicates that the microprocessor is performing a valid read. When this read is being performed, the VMA signal, R/signal,
All signals and + signals are "high"
level condition. Therefore, the processor is valid memory cycle, reads the contents of memory,
Not interrupt acknowledgment or DMA or invalid cycles.

₊₂ signal is Fetch-1 or Fetch-
2. This condition is _heralded by
Occurs when no DMA, invalid cycle, or access from the FFFE signal is being performed.
As mentioned above, _two signals indicating a Fetch-1 or Fetch-2 cycle are generated by the Fetch Predictor.

The above describes each part and operation of the fetish warning device. It takes a certain number of clock cycles to execute an instruction on the 6809 microprocessor, so
The number of clock cycles until the next opcode fetch is known from the current instruction. The Fetchi notice device decodes 3 consecutive bytes and displays the next data.
It also determines how long to wait before labeling a bus read as an opcode fetch.
Determines the number of clock cycles required to execute an instruction. When the 6809 microprocessor encounters a one-byte instruction, it routinely prefetches the next byte. When the microprocessor executes a one-byte instruction, the prefetched byte is discarded. These discarded prefetches appear as read cycles in the acquisition memory. Instruction formats are classified according to the number of bytes decoded, so
The total number of clock cycles per instruction is defined. This information can be obtained from a microprocessor programming manual, such as the Motorola 6809 Microprocessor Programming Manual. The format of the decoded instruction in combination with the various input variables determines the correct signal sequence to pass through the fetch notice state machine.
The first byte of the opcode is decoded to determine whether the next byte needs to be decoded. This determines the instruction format and, for standard format instructions, the total number of clock cycles per instruction. For multi-byte instructions, the first byte defines the minimum number of clock cycles to be added to the variable number of clock cycles (determined by decoding the next byte). This number of cycles is stored in two presettable counters 36 and 38. These counters internally track the number of clock cycles required for the microprocessor to execute any given instruction. The state machine then signals a fetch when each counter increments to its final value. The subsequent clock cycle is a fetch for the 6809 microprocessor. As mentioned above, the fetch predictor expects a fetch at the clock edge that latches the fetch into the logic analyzer, so it takes the corresponding memory read and labels it as a fetch in memory, disassembling the disassembled mnemonic from other Display on logic analyzer along with information. This information is also used for triggering and data acquisition.

FIG. 3 shows a flowchart of the Fetch Predictor. In this figure, Y and N represent affirmation and negation, respectively. As shown in this flowchart (in Figure 3,
The interrupt acknowledge signal (IAK) allows the Fetch Predictor to be conveniently synchronized to the 6809 microprocessor. The state machine always jumps to state A because the first instruction fetch of the interrupt service routine always follows three cycles after signal detection. In any state of the state machine, a reset and a corresponding signal are generated. Thus, the signals are tested in all states of the fetch notice state machine. It is only necessary to latch the data bus in state D or F depending on the particular input variable, but the data bus is latched in all states as a valid implementation. If an irregular opcode (IOC) is decoded in state D or F, the state machine returns to state D and attempts to resynchronize. State clock generator 30 is disabled on write, VMA, DEAD, DMA or synchronous acknowledge cycles. Particularly for stacked write operations, not clocking the write reduces the number of cycles to time. By not clocking invalid memory address cycles, the number of clocks in time is reduced, and furthermore, it is no longer necessary to know whether a branch operation is taken or not. invalid,
state in DMA or synchronous acknowledge cycle
By not clocking the machine, these cycle numbers are passed to the state machine. Therefore, fetches predicted for the next cycle following completion of the current instruction are inhibited until immediately following the completion of any number of invalid DMA or synchronization acknowledge cycles.

Standard Instructions For standard single-byte opcodes, the number of cycles is decoded in state D and stored in counter 36.
(CNTR ₁ ). If the instruction is a 2-cycle instruction (shortest), F is the counter 36
(CNTR ₁ ). Otherwise, the number of cycles completed until time minus two is loaded into counter 36 (CNTR ₁ ). Assuming the detected opcode is not irregular,
The next state will be E. When counter 36 equals F (CNTR ₁ =F), an instruction fetch cycle signal is generated and the next state is D. Otherwise, counter 36 would increment to F and many cycles would be required until the time before the signal was generated.

Standard+Instructions Standard+instructions have two bytes to be decoded. In state D, the first byte is decoded and loaded into counter 36. The opcode plus flag is then set and the ₊₂ signal (next fetch byte) is generated before proceeding to state F. opcode plus
Flag bits are cycle decoder PROM34
is fed back to the high-order digit address line, so a new decode table is addressed and decodes the second byte. The opcode plus flag is always set, so when the number of opcode cycles is not equal to F, the state machine branches to load counter 38 and proceed to state G. The reason for testing whether the number of cycles of the opcode is equal to F is to minimize the overall state machine time so as not to exceed the number of cycles of the shortest 2-byte instruction. In state G, E( ₂
Counter 38 is incremented for the number of cycles necessary to reach =E), after which the state machine advances to state E. Counter 3 again before returning to state D.
6 is incremented to F and a signal is generated.

Page 2 or Page 3 Instructions For these types of instructions, the first byte first indicates that the second byte needs to be decoded. In state D, counter 36 is loaded, but its value is ignored. Page 2 or Page 3 flag bit is set while state F
Previous signal and ₊₂ signal occur.
A new table is addressed again to set the flag bit. With these flag bits set and no opcode plus flag bits occurring, counter 36 is reloaded with the values in Table 2. Since this is not an opcode plus (standard +) instruction, the state machine advances to state E and increments counter 36 to F, as described above.

Page 2+ or Page 3+ Instructions These instruction types require 3 bytes to be decoded. The first byte only indicates whether it is a page 2 or page 3 instruction and sets the page 2 or page 3 flag bit. Counter 3 again
6 and ignored in state D. State F because the opcode plus flag is not set
The cycle decode table addressed by the page 2 or page 3 flag bit is loaded into counter 36. However, the second byte decoded indicates that this instruction is of the opcode plus form, and thus sets the opcode plus flag before returning to state F. Along with the page 2 or page 3 flag bit, the opcode plus flag bit is now set so that the third cycle decoder table is addressed and its output value is loaded into counter 38. Again, in state G, counter 38 is incremented to E, and subsequently in state E, counter 36 is incremented to F. A signal is generated as described above.

RTI Instruction The number of cycles required for an RTI instruction depends on whether the E bit in the stacked status code register is set.In state D, counter 36 is loaded with the number of cycles corresponding to the E bit that was not set. However, before proceeding to state F, the RTI flag bit is set. In state F, the RTI flag
The bit functions address a new cycle decoder table and the status code is taken from the stack and applied to the eight lower address lines of the decoder PROM. Therefore, when the E bit is set, the E bit in the status code register addresses that portion of the decoder table that contains the correct number of additional cycles needed. This number is loaded into counter 38 since the page 2 and page 3 flag bits are not set. In states G and E, counters 38 and 36 are incremented to their final values as described above before outputting the signal.

PUL Instructions PUL type instructions are loaded into counter 36 in state D and set the PUL flag bit. In state F, the PUL operand is PUL
In combination with the flag bit, the counter 38
Address the appropriate value to be loaded into. Conditions G and E follow, as described above. PULNothing
The instruction is a valid opcode that requires 3 cycles.

Table A (Instruction setting mnemonic for 6809 microprocessor) Instruction Contents ABX: Add the contents of accumulator B to the contents of index register X ADC: Add the memory value to the register with the carry ADD : Add the contents of the memory to the contents of the register AND: Put the logical OR result of the memory contents into the register ASL: Left arithmetic shift ASR: Right arithmetic shift BCC: Branch if the carry is cleared BCS: If the carry is set Branch if equal BEQ: Branch if equal BGE: Branch if greater than or equal to zero BGT: Branch if greater than or equal to BHI: Branch if greater than or equal to BHS: Branch if greater or equal BIT: Bit test BLE: Less than or equal to zero Branch if BLO: Branch if less than BLS: Branch if less than or equal to BLT: Branch if less than zero BMI: Branch if negative BNE: Branch if not equal BPL: Branch if positive BRA: Branch unconditionally BRN: Branch non-branch BSR: Branch to subroutine BVC: Branch if overflow flag is cleared BVS: Branch if overflow flag is set CLR: Clear CMP: Compare register and memory contents COM: 1's complement CWAI: Status code Clear and wait for interrupt DAA: Decimal addition correction of accumulator A DEC: Decrement EOR: Exclusive OR EXG: Register exchange INC: Increment JMP: Jump to effective address JSR: Jump to subroutine at effective address LD: Load memory contents into register LEA: Load effective address LSL: Logical left shift LSR: Logical right shift MUL: Multiplication between accumulators NEG: Two's complement NOP: No operation OR: Logical sum of register and memory contents PSH : Save register PUL: Restore register ROL: Rotate left ROR: Rotate right RTI: Return from interrupt RTS: Return from subroutine SBC: Subtract with borrow SEX: Two's complement extension ST: Store register contents in memory SUB : Subtract the contents of memory from the contents of a register SWI: Software interrupt SYNC: Synchronize with an external event TFR: Transfer data between registers TST: Test Although the above describes the preferred embodiment of the present invention, it will be appreciated by those skilled in the art. It will be apparent that various modifications may be made without departing from the spirit of the invention.
For example, although the preferred embodiment describes fetch notification in connection with a 6809 microprocessor, the invention is equally applicable to other microprocessor systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the relationship between the fetch predictor and other parts in the data acquisition system of a logic analyzer, FIG. 2 is a detailed block diagram of the fetch predictor state machine according to the present invention, and FIG. FIG. 2 is a flow chart explaining the operation of FIG. 2. FIG. 30...State clock generator, 32...Data latch, 34...Cycle decoder PROM,
36, 38...Counter, 40...Flag latch,
42...Input/output formation logic circuit, 50...Present state latch, 52...Present state latch
State decoder.

Claims (1)

[Claims] 1 decoding means coupled to the microprocessor for decoding the microprocessor's instruction data into the number of clock cycles required to execute each instruction; and counting the number of clock cycles and indicating the fetch of the opcode. A fetch notification device for a microprocessor, comprising counter means for generating a signal, and logic control means for generating a fetch signal in response to information from the decoding means and the signal from the counter means.