GB2110440A - Fetch prediction state machine for 6809 microprocessor - Google Patents

Abstract

A fetch prediction state machine predicts fetches of opcodes in a sequence of 6809 microprocessor instructions. The state machine passively monitors a data bus, and includes an instruction-cycle decoder 34 to determine the number of clock cycles until the next opcode fetch, and one or more counters 36, 38 which are incremented in turn to their terminal values, where-upon a fetch line is asserted. The state machine is particularly useful in the personality module of a logic analyzer to permit data qualification on fetches so that the proper data can be stored in acquisition memory. <IMAGE>

Description

SPECIFICATION Fetch prediction state machine for 6809 microprocessor Background of the invention Logic analyzers, particularly those with both state and timing analysis capabilities, are very useful in locating hardware and software problems in microprocessors, including microprocessor-based products under development. Because of different characteristics of various commercially-available microprocessors, specialized data acquisition modules, termed personality modules by the electronics industry, are provided for each microprocessor to interface with the logic analyzer. That is, each personality module is basically a hardware interface which adapts the input parameters of the logic analyzer to specific characteristics of a particular processor, such as control line definitions and address, data, and control line pin assignments.Also, since the personality module is essentially the data acquisition source for the logic analyzer, it is possible to construct specific data qualifiers so the logic analyzer samples and stores only qualified data in its somewhat limited acquisition memory. Once the data is so acquired by the logic analyzer, it may be displayed in the disassembled mnemonics of the particular processor, or any other display format of which the logic analyzer is capable.

In order to facilitate proper disassembly of a microprocessor's instructions into opcode mnemonics and provide the disassembled mnemonic data for display, it is necessary first that instruction fetches be distinguished from operand reads. Then data qualification may be done to store only the proper data in acquisition memory. In particular, the 6809 microprocessor does not have a fetch prediction capability, and consequently, large quantities of unwanted or indistinguishable information are stored in the acquisition memory along with the desired information. Thus, it is necessary to predict fetches of opcodes in a sequence of microprocessor instructions.

Summary of the invention In accordance with the present invention, a fetch prediction state machine is provided to predict fetches of opcodes in a sequence of 6809 microprocessor instructions. The predicted fetches are indicated in the form of one or more control signals which are applied to the word recognizer portion of the logic analyzer to permit data to pass to the acquisition memory. On the basis that all 6809 microprocessor instructions require a known number of clock cycles in which to execute, the number of clock cycles until the next opcode fetch may be determined from the current instruction. The fetch prediction state machine passively monitors the microprocessor bus, and it latches and decodes as many as three consecutive bytes in order to determine how long to wait before labeling the next data bus read as an opcode fetch.The decoder is a read-only memory programmed with a number of decoder tables which contain the number of cycles to wait until the next instruction. The decoded numbers of cycles are loaded into a first counter and a second counter as required. The counters are then incremented in turn to their terminal values, whereupon the fetch line is asserted to indicate that the now current cycle is a fetch.

The type of instruction decoded determines the correct path through the fetch prediction state machine. As many as three consecutive bytes may need to be decoded in order to determine the number of processor clock cycles required to execute a particular instruction. Decoding of the first byte of an opcode determines whether or not subsequent bytes need to be decoded. It determines instruction type, and for regular type instructions, defines the total number of clock cycles for the instruction. For multiple-byte instructions, the first byte defines a subtotal of clock cycles, which must be added to the balance of the required cycles, determined by decoding subsequent bytes. Upon decoding the first byte, various flag bits are set in a flag latch. These bits point to one of several different decoder tables needed to decode subsequent bytes of the current instruction.The next state of the fetch prediction state machine is determined by logical combinations of the present state and various input variables. The state machine clock is derived from the microprocessor clock and it is inhibited during write cycles, invalid memory address cycles, and certain other cycles. By not clocking the state machine on these types of cycles, the number of these cycles is transparent to the state machine, and they are thus ignored.

It is therefore one object of the present invention to provide a novel fetch prediction state machine for use in a 6809 microprocessor personality module for a logic analyzer.

It is a feature of the invention to decode multiple byte opcodes and predict fetches based upon them.

It is another feature of the invention to provide automatic resynchronization of a fetch predictor state machine after an illegal opcode.

Other objects, features, and advantages of the present invention will become apparent to those having ordinary skill in the art upon a reading of the following detailed description when taken in conjunction with the accompanying drawings.

Drawings Fig. 1 is a block diagram showing the relationship of the fetch predictor to other parts of a logic analyzer data acquisition system; Fig. 2 is a detailed block diagram of a fetch prediction state machine in accordance with the present invention; and Fig. 3 is a flow chart illustrating operation of the fetch prediction state machine of Fig. 2.

Detailed description of the invention To facilitate an understanding of the invention, it is helpful to know the relationship of the fetch predictor to the other parts of a logic analyzer data acquisition system. In the block diagram of Fig. 1, there is shown a personality module 10 connected between a system under test (SUT) 12 and a logic analyzer 14. The personality module 10 plugs into the microprocessor socket in the SUT 12, and the 6809 microprocessor 16 from the SUT is plugged into a zero-insertion force socket on the personality module 10. The effect is to connect the personality module 10 to the SUT microprocessor bus. The logic analyzer 14 suitably may be a conventional logic state analyzer having a cathode-ray tube display device for dispiaying the contents of an acquisition memory contained within the logic analyzer.The personality module 10, in addition to the microprocessor 1 6, includes a buffer driver 18, and a set of address, data, clock, and control signal lines to permit data acquisition for the logic analyzer 14. Located within the control line portion of the signal lines between the buffer driver 18 and the logic analyzer 14 is the control logic and fetch predictor 20. As can be seen, the personality module allows the selected microprocessor to operate as if it were in the system under test, with the address, data, control, and clock lines available to the logic analyzer.

Additionally the personality module provides personalized interpretstion and#set up information specific to the 6809 microprocessor, in a standard format for the logic analyzer. This information aids in mnemonic disassembly of acquired information, and customizing of displays.

The fetch signals which are generated by the fetch predictor are applied to the word recognizer portion of the logic analyzer to permit triggering and data qualification on instruction fetches.

Referring to Fig.2, there is shown a block diagram of the fetch prediction state machine in accordance with the present invention, and also shown is a portion of the control logic as it applies to the fetch predictor. Abbreviations used in the description and in the flow chart of Fig. 3 are defined in Table A, 6809 Microprocessor Instruction-Set Mnemonics at the end of this description.

A state clock generator 30 receives a clock signal E from the 6809 microprocessor and produces therefrom a clock signal SCLK for use by the fetch predictor, and an output clock signal CLK to be used by the logic analyzer to generate a master state clock. As will be seen later, the state clock signal SCLK may be interrupted or inhibited under certain conditions.

A data latch 32 accepts eight-bit opcodes from a microprocessor data bus and latches them for use by a cycle decoder programmable read-only memory (PROM) 34. In the embodiment built and tested, the inputs DAO-DA7 are latched on the rising edge of the SCLK signal. The cycle decoder PROM 34 is a 2K-word by a 8-bit EPROM containing seven decoder tables. The tables indicate the number of clock cycles each 6809 instruction takes for execution. These tables were produced from information contained in the Motorola 6809 Microprocessor Programming Manual for this embodiment. Signal lines from the data latch 32 carry the latched 8-bit opcode to be decoded by the PROM 34. The decoded information on the outputs CT0-CT3 tells a first counter 36 and a second counter 38 what their increment values will be.The counters 36 and 38 are loaded with a complement of the number of cycles to delay, and incremented to E or F in hexadecimal code. The FO-F2 lines carry the conditions of various flag bits to the flag latch 40.

These conditions are clocked to the outputs of the flag latch 40 on the rising edge of SCLK. The outputs of the flag latch connect to the input/output forming logic circuit 42 and serve as input addresses for the cycle decoder PROM 34.

The cycle decoder PROM 34 uses these addressing inputs to point to one of several different decoder tables within the PROM. These tables aid in decoding subsequent bytes of the current instruction. The illegal opcode IOC signal line is an output from the cycle decoder PROM 34 that indicates the last opcode decoded was an illegal opcode. This signal is asserted low as the I ioco line to the logic analyzer via an input/output forming logic circuit 42, but inverted high in the firmware for the screen display.

The first and second counters 36 and 38 track the number of cycles to wait before indicating that the next instruction cycle is a fetch. To signal this event, the first counter 36 generates a count signal CNT1=F and the second counter 38 generates a count signal CNT2=E. These signals are used by the input/output forming logic circuit 42. Signal lines CT0-CT3 from the cycle decoder PROM 34 carry information indicating the number of cycles the current instruction will take before the next instruction is executed. Load counter signals LDCNT1 and LDCNT2 from the input/output forming logic circuit 42 latch the CT0-CT3 information. The SCLK signal increments the counters until the terminal count is reached when CNT1=F and CNT2=E are asserted.

A skip state clock circuit 44 generates a SKIP signal for the state clock generator 30, which disables the generation of the SCLK clock for one cycle. The cycle following the skipped cycle corresponds to the condition code being pulled off the stack and placed on the data bus. The skip state clock circuit 44 is responsive to a return from interrupt (RTI) signal from an RTI decoder 46. A clock signal ETTL from the state clock generator 30 clocks the RTI signal through an internal flip-flop to deactivate the SKIP signal. The RTI signal indicates when a Return from Interrupt instruction occurs. The active state of the RTI signal is generated when signals D and F0 are high and signals F1 and F2 are low.

A present state latch 50 holds the current state of the fetch prediction state machine. With the rising edge of SCLK, the NEXT X, NEXT Y, and NEXT Z values are loaded into the latch and become the new present state. When an interrupt acknowledge (IAK) is received, the latched values are cleared, forcing the state machine back to state A. Since fl may be asserted while the state machine is any of its states, this provides a method of resynchronizing the fetch predictor (a fetch will always follow two cycles after an IAK signal). The present state decoder 52 is a threeline to eight-line decoder which provides individual output lines corresponding to each state of the state machine. These outputs simplify the input/output forming logic.The input/output forming logic circuit 42 is a combination of discrete logic gates derived from Boolean algebra expressions in accordance with desired inputs and outputs. The input forming logic portion generates the next state from a logical combination of the present state and input variables such as CNT1=F, CNT2=E, PAGE 2/3 Flag, OP+ Flag, OP+, IOC, and &num;OPCYCLES=F. The output forming logic portion generates outputs from the state machine by using a logical combination of the present state and the input variables previously listed. The outputs include LDCNT1, INCCNT1, LDCNT2, INCCNT2, lOCO, ENIFC2, and CLRFLGS.

Several status and all address lines from the SUT are applied to input buffer and detector network 60 to produce several control lines for the logic analyzer, the state clock generator 30, and a fetch enable logic circuit 62. The DMA+DEAD signal is produced by the DMA or dead cycle detector portion of the detector network 60, and is useful in signaling that dead cycles exist, or that the bus is in use by other controllers. The DMA+DEAD line is defined as being asserted low whenever the Bus Available (BA) line from the SUT is high, and for one E clock cycle following the transition of BA from high to low. The latter is the trailing dead cycle following the termination of DMA transfers and Syne Acknowledge cycles. The read-write (R/W) signal is available from the SUT via the input buffer portion of the circuit 60.The Valid Memory Address (VMA) signal is produced by the VMA detector circuit portion of network 60. An invalid memory address exists when the state of the address bus is FFFF, when the bus status (BS) is equal to zero, or when Rip=1, indicating a read operation. The VMA detector portion of network 60 also produces the ADO and FFFE+FFFF signals for use by the fetch enable logic circuit 62. An interrupt acknowledge detector portion of network 60 generates the IAK signal for the fetch enable logic circuit 62 and the present state latch 50. The signal is produced when BS is high and BA is low. The fetch enable logic circuit 62 supplies the logic analyzer with instruction fetch cycle (IFC) and IFC+IFC2 signals. The IFC signal indicates that an instruction fetch cycle (Fetch-1) occurred.The lFC+iFC2 signal indicates an instruction fetch cycle in which the first (Fetch-1) or subsequent bytes (Fetch-2) of an instruction were fetched. That is, the fetch predictor anticipates the fetch in time for the clock edge that latches it into the memory of the logic analyzer, so that the corresponding memory read can be labeled as a fetch in acquisition memory, and the disassembled mnemonics may be displayed on the Logic Analyzer's screen along with other information. The IFC signal occurs when CLRFLGS and ENIFC (internal to FETCH ENABLE LOGIC 62) are asserted, and FFFE is not.

The first line, CLRFLGS, is from the input/output forming logic circuit 42 of the fetch predictor. This line indicates the end of one complete sequence through the fetch predictor state machine, and that the following cycle will be a fetch. The flags are cleared in preparation for the next cycle through the state machine. FFFE is decoded to exclude the extraneous prediction of fetches during 6809 microprocessor reset sequences.

When ENIFC is asserted low, it indicates that the microprocessor is doing a valid read. When this occurs, the VMA, the R/W, the IAK,and DMA+DEAD lines are all in the high state. Thus, the processor is indicating a valid memory cycle, is reading memory, and is not an interrupt acknowledge or DMA or dead cycle. The lFC+lFC2 line indicates a Fetch-1 or a Fetch-2 is taking place. This occurs when predicted by ENIFC2 and when the processor is not doing any of the following transfers: a write, an invalid memory cycle, an interrupt acknowledge, a DMA, a dead cycle, or an access from FFFE. As mentioned previously, ENIFC2, indicating a Fetch1 or Fetch-2 cycle, is generated by the fetch predictor.

Now that all of the parts of the fetch predictor have been described, the operation thereof may be discussed. On the basis that all 6809 microprocessor instructions require a known number of clock cycles in which to execute, the number of clock cycles until the next opcode fetch may be determined from the current instruction.

The fetch predictor can decode up to three consecutive bytes to determine the number of clock cycles required to execute an instruction, in order to determine how long to wait before labeling the next data bus read as an opcode fetch. When the 6809 microprocessor encounters a a one-byte instruction, it does a prefetch of the next byte as normal. If the microprocessor was executing a one-byte instruction, the pre-fetched byte will be discarded. These discarded pre fetches will appear as read cycles in the acquisition memory. Instruction types have been categorized, according to the number of bytes to be decoded, so the total number of clock cycles per instruction may be defined. This information is available in the microprocessor programming manual, for example, the Motorola 6809 Microprocessor Programming Manual.The type of instruction decoded combined with various input variables, determines the correct path through the fetch prediction state machine.

Decoding of the first byte of an opcode determines whether or not subsequent bytes need to be decoded. It determines the instruction type, and for regular type instructions, defines the total number of clock cycles per instructions. For multiple byte instructions, the first byte defines some minimum number of clock cycles which must be added to a variable number of clock cycles (determined by decoding subsequent bytes). Storage of the number of cycles is provided by two presettable counters 36 and 38, which internally track the number of clock cycles required by the microprocessor to execute any given instruction. Once each counter has in turn incremented to its terminal count, the state machine predicts a fetch. The following clock cycle should be a 6809 microprocessor fetch.As mentioned previously, since the fetch predictor anticipates the fetch in time for the clock edge which latches it into the logic analyzer, the corresponding memory read may be labeled as a fetch in the acquisition memory, and the disassembled mnemonics may be displayed by the Logic Analyzer along with other information.

This information may also be used for triggering and data qualification.

Refer now to the fetch predictor flow chart shown in Fig. 3. As shown in the flow chart, IAK, the interrupt acknowledge, provides a convenient method of synchronizing the fetch predictor to the 6809 microprocessor. Since the fetch of the first instruction of an interrupt service routine always follows three cycles after the detection of TAIT, the state machine always jumps to state A. A reset and its corresponding 1 can occur when the state machine is in any state, and hence lAK is tested for in all states of the fetch prediction state machine. Note that although it is only necessary to latch the data bus in states D or F, depending on certain input variables, it is latched in every state as a matter of convenient implementation.If an illegal opcode (IOC) is decoded in states D or F, the state machine returns to state D and attempts to resynchronize. The state clock generator 30 is inhibited on writes, VMA, dead, DMA, or sync acknowledge cycles. By not clocking on writes, the number of cycles to time out is reduced, particularly for stack write operations. By not clocking on invalid memory address cycles, the number of cycles to time out is reduced, and further, it is no longer necessary to know whether or not a brach operation was taken. By not clocking the state machine on dead, DMA or Sync Acknowledge cycles, the number of those cycles becomes transparent to the state machine.

Consequently, the fetch that would have been predicted for the next cycle following the completion of the current instruction is inhibited until immediately following the completion of any number of dead-DMA, or Sync Acknowledge cycles.

Regular instructions For a Regular single byte opcode, the number of cycles is decoded in state D and loaded into counter 36 (CNTRi). If the instruction is a two cycle instruction (the shortest there is), an F is loaded into counter 36 (CNTR1); otherwise the complement of the number of cycles to time-out, minus 2, is loaded into counter 36 (CNTR1).

Assuming the opcode detected was not illegal, the next state becomes E. If counter 36 equals F (CNTR1 F), the Instruction Fetch Cycle IFC line will be asserted and the next state will be D.

Otherwise, counter 36 will be incremented to F, taking as many cycles as is necessary to time-out prior to issuing the IFC.

Regular+ instructions A Regular+ instruction has two bytes to be decoded. In state D, the first byte is decoded and loaded into counter 36. Then the Opcode Plus flag is set, and IFC and lFC+IFC2 (subsequent fetch bytes) are asserted prior to progressing to state F.

Since the Opcode Plus flag bits are fed back into the higher order address lines of the Cycle Decoder PROM 34, a new decoding table is addressed for decoding the second byte. Because the Opcode Plus flag is already set, the state machine branches to load counter 38 and then progresses to state G, if the number of opcode cycles is not equal to F. The reason for testing if the number of opcode cycles is equal to F is to minimize the time overhead of the state machine so as to not exceed the number of cycles of the shortest two-byte instruction. In state G, counter 38 is incremented for as many cycles as is necessary to reach E (CNTR2=E), whereupon the state machine proceeds to state E. Again, counter 36 is incremented to F and IFC is asserted prior to returning to state D.

Page 2 or Page 3 instructions For these types of instructions, the first byte serves primarily to indicate that a second byte needs to be decoded. Although counter 36 is loaded in state D, this value is ignored. The Page 2 or Page 3 flag bits are set while IFC and lFC+lFC9 are asserted prior to state F. Again a new table is addressed due to the set flag bits. Since these flag bits are set, and the Opcode Plus flag bit is not, counter 36 is reloaded with a value from the second table. Because this is not an Opcode Plus (Regular+) instruction, the state machine progresses to state E and increments counter 36 to F as before.

Page 2+ or Page 3+ instructions These types of instructions require decoding of three bytes. The first byte indicates only that it is a Page 2 or Page 3 instruction and correspondingly sets the Page 2 or Page 3 flag bits. Again counter 36 is set and ignored in state D. The cycle decode table, addressed by the Page 2 or Page 3 flag bits in state F, is loaded into counter 36 since the Opcode Plus flag is not set.

The second byte decoded, however, indicates that this instruction is also an Opcode Plus type and consequently sets the Opcode Plus flag prior to returning to state F. A third cycle decoder table is now addressed, and its output value is loaded into counter 38 since the Opcode Plus flag bit is now set in addition to the Page 2 or Page 3 flag bits.

Again, counter 38 is incremented to E in state G, following which counter 36 is incremented to F in state E. IFC is asserted as before.

RTI instruction The number of cycles required for an RTI instruction is totally dependent on whether or not the E bit of the stacked condition code register is set. In state D, counter 36 will be loaded with the number of cycles corresponding to the E bit not set, and the RTI flag bits will be set prior to progressing to state F. In state F, a new cycle decoder table is addressed as a function of the RTI flag bits, and the condition code is pulled off the stack and input on the eight lower address lines of the decoder PROM. Consequently, the E bit of the condition code register addresses that portion of the decoder table containing the correct number of additional cycles required when the E bit is set. This number is loaded into counter 38 because the Page 2 and Page 3 flag bits are not set.In states G and E, counters 38 and 36 are incremented to their terminal values as before, prior to outputting IFC.

PUL instruction PUL type instructions load counter 36 and set the Pul flag bits in state D. In state F, the Pul operand in combination with the Pul flag bits, address the proper value to be loaded into counter 38. States G and E follow as before. A Pul Nothing instruction is a valid opcode requiring three cycles.

Table A Instruction set Instruction Description ABX Add Accumulator B into Index Register X ADC Add with Carry into Register ADD Add Memory into Register AND Logical AND Memory into Register ASL Arithmetic Shift Left ASR Arithmetic Shift Right BCC Branch on Carry Clear BCS Branch on Carry Set BEQ Branch on Equal BGE Branch on Greater Than or Equal to Zero BGT Branch on Greater BHI Branch if Higher BHS Branch if Higher or Same BIT Bit Test BLE Branch if Less than or Equal to Zero BLO Branch on Lower BLS Branch on Lower or Same BLT Branch on Less than Zero BMI Branch on Minus BNE Branch Not Equal BPL Branch on Plus BRA Branch Always BRN Branch Never BSR Branch to Subroutine BVC Branch on Overflow Clear BVS Branch on Overflow Set CLR Clear CMP Compare Memory from a Register COM Complement CWAI Clear CC bits and Wait for Interrupt DAA Decimal Addition Adjust DEC Decrement EOR Exclusive OR EXG Exchange Registers INC Increment JMP Jump JSR Jump to Subroutine LD Load Register from Memory LEA Load Effective Address LSL Logical Shift Left LSR Logical Shift Right MUL Multiply NEG Negate NOP No Operation OR Inclusive OR Memory into Register PSH Push Registers PUL Pull Registers ROL Rotate Left ROR Rotate Right RTI Return from Interrupt RTS Return from Subroutine SBC Subtract with Borrow SEX Sign Extend ST Store Register into Memory SUB Subtract Memory from Register SWI Software Interrupt SYNC Synchronize to External Event TFR Transfer Register to Register TST Test While I have shown and described herein the preferred embodiment of my invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from my invention in its broader aspects. For example, while the preferred embodiment is specifically adapted to predict fetches associated with the 6809 microprocessor, the principles taught herein may be applicable to other microprocessor systems as well. Therefore, the scope of the present invention should be determined only by the following claims.

Claims (8)

Claims

1. A state machine for predicting fetches in the instruction cycle of a microprocessor, comprising in combination: a clock signal generator operable in synchronism with a microprocessor clock; means coupled to a microprocessor bus for decoding bytes of instruction data into numbers of clock cycles required for execution of each instruction; means for counting said numbers of clock cycles and generating terminal count signals indicative of opcode fetches; and logic control means responsive to logical combinations of state and input variables including information from said decoding means and terminal count signals from said counting means for generating fetch signals; wherein said decoding means, counting means, and logic control means operate in synchronism with said clock signal.

2. A state machine in accordance with claim 1, wherein said decoding means comprises a data latch and a read-only memory containing instruction cycle decoder tables.

3. A state machine in accordance with claim 2, wherein said decoding means further comprises a flag latch which receives flag bits from said readonly memory to address particular decoder tables stored in said memory.

4. A state machine in accordance with claim 1, wherein said counting means comprises at least one presettable counter.

5. A state machine in accordance with claim 1, wherein said logic control means includes a logic forming circuit, a present state latch, and a present state decoder coupled in a loop.

6. A state machine in accordance with claim 1 further including means for inhibiting said clock signal generator under certain predetermined conditions.

7. A state machine in accordance with claim 1 further including means for resynchronizing the state machine following detection of an illegal opcode.

8. A state machine for predicting fetches in the instruction cycle of a microprocessor substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.