JPS62204349U - - Google Patents
Info
- Publication number
- JPS62204349U JPS62204349U JP9384286U JP9384286U JPS62204349U JP S62204349 U JPS62204349 U JP S62204349U JP 9384286 U JP9384286 U JP 9384286U JP 9384286 U JP9384286 U JP 9384286U JP S62204349 U JPS62204349 U JP S62204349U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor elements
- heat sink
- parallel
- semiconductor device
- molded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案の一実施例によるモールド形半
導体素子を示す断面図、第２図は本考案の並列接
続の回路図、第３図ａ，ｂは本考案に使用される
半導体素子の２つの例の斜視図、第４図は従来の
モールド形半導体装置の一例を示す断面図、第５
図は従来のモールド形半導体装置の直列接続の回
路図である。
１，９……半導体素子、２……素子取付板、３
……放熱板、４……ネジ、５，６……絶縁板、７
……樹脂、８……インサート電極、１０……連結
線、Ａ……アノード、Ｋ……カソード。
FIG. 1 is a sectional view showing a molded semiconductor device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of parallel connection of the present invention, and FIGS. 3 a and b are two views of a semiconductor device used in the present invention. FIG. 4 is a sectional view showing an example of a conventional molded semiconductor device, and FIG. 5 is a perspective view of two examples.
The figure is a circuit diagram of a series connection of conventional molded semiconductor devices. 1, 9... Semiconductor element, 2... Element mounting plate, 3
... Heat sink, 4 ... Screw, 5, 6 ... Insulation plate, 7
... Resin, 8 ... Insert electrode, 10 ... Connection line, A ... Anode, K ... Cathode.
Claims (1)
有したモールド形半導体装置において、複数個の
半導体素子を素子取付用孔に取りつけ放熱基板上
に一体的に平行配置し、前記半導体素子を並列接
続し周囲を樹脂で被覆したことを特徴としたモー
ルド形半導体装置。 In a molded semiconductor device having a plurality of semiconductor elements and a heat sink in the same device, the plurality of semiconductor elements are mounted in element mounting holes and arranged integrally in parallel on a heat sink, and the semiconductor elements are placed in parallel. A molded semiconductor device characterized by being connected and covered with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9384286U JPS62204349U (en) | 1986-06-18 | 1986-06-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9384286U JPS62204349U (en) | 1986-06-18 | 1986-06-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62204349U true JPS62204349U (en) | 1987-12-26 |
Family
ID=30956768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9384286U Pending JPS62204349U (en) | 1986-06-18 | 1986-06-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62204349U (en) |
-
1986
- 1986-06-18 JP JP9384286U patent/JPS62204349U/ja active Pending
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